CN115732538A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN115732538A CN115732538A CN202211098278.8A CN202211098278A CN115732538A CN 115732538 A CN115732538 A CN 115732538A CN 202211098278 A CN202211098278 A CN 202211098278A CN 115732538 A CN115732538 A CN 115732538A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 74
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 48
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- 229910052698 phosphorus Inorganic materials 0.000 claims description 20
- 239000011574 phosphorus Substances 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 11
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
The application provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. Firstly, providing a wide band gap substrate, then forming a wide band gap epitaxial layer on the wide band gap substrate, and then forming a first gate oxide layer on one side of the wide band gap epitaxial layer, which is far away from the wide band gap substrate; and finally, forming a second gate oxide layer on one side of the first gate oxide layer, which is far away from the wide band gap substrate, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or a non-doped silicon oxide layer. The semiconductor device and the manufacturing method thereof have the advantages of reducing interface state density and improving channel mobility.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
Silicon carbide, as an important third-generation semiconductor material, has the advantages of high forbidden band width, high critical breakdown electric field, high thermal conductivity and the like. Therefore, compared with the traditional silicon-based power device, the silicon carbide power device has the advantages of higher breakdown voltage, higher switching speed, higher working temperature and the like, and has very wide application prospects in the fields of new energy automobiles, photovoltaic power generation, electric vehicle traction and the like.
The preparation of the gate oxide structure is the core process of the SiC MOSFET device, and the problem of SiC/SiO in the process of forming SiO2 by SiC thermal oxidation needs to be solved 2 A large number of defects occur at the interface, particularly carbon clusters, so that the interface state density is high, the channel mobility is low, the forward current capacity of the SiC MOSFET is greatly limited, and even a series of problems of gate oxide reliability are caused.
Thus, in the prior art, siC is oxidized to SiO 2 Thereafter, the SiC/SiO may be passivated by annealing in a nitrogen-doped atmosphere 2 Interface, reducing the interface state density. However, due to oxidized SiO 2 The thickness is generally thicker, so after annealing in the atmosphere of high-temperature nitrogen doping, siC/SiO 2 The nitrogen element content at the interface is not high, and the reduction of the interface state density is limited.
In summary, siC/SiO exists in the prior art 2 The content of nitrogen element at the interface is not high, and the density of interface state is high.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which aim to solve the problem of SiC/SiO in the prior art 2 The content of nitrogen element at the interface is not high, and the density of interface state is high.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, embodiments of the present application provide a semiconductor device, including:
a wide bandgap substrate;
a wide bandgap epitaxial layer disposed on the wide bandgap substrate;
the first gate oxide layer is arranged on one side, far away from the wide band gap substrate, of the wide band gap epitaxial layer and is a nitrogen and phosphorus doped silicon oxide layer;
the second gate oxide layer is arranged on one side, far away from the wide band gap substrate, of the first gate oxide layer; the second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.
Optionally, the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer.
Optionally, the thickness of the first gate oxide layer is
And/or the presence of a gas in the gas,
the second gate oxide layer has a thickness of
Optionally, in the first gate oxide layer, the doping concentration of P is greatest at the interface between the wide bandgap epitaxial layer and the first gate oxide layer.
Optionally, the second gate oxide layer is a nitrogen-doped silicon oxide layer, and the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.
Optionally, the doping concentration of P in the first gate oxide layer is 1E13/cm 3 -1E15/cm 3 。
Optionally, the doping concentration of N in the first gate oxide layer is 1E14/cm 3 -5E16/cm 3 。
Optionally, the wide bandgap substrate is a silicon carbide substrate; and/or
The wide band gap epitaxial layer is a silicon carbide epitaxial layer.
In a second aspect, the present application further provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device including:
providing a wide band gap substrate;
forming a wide bandgap epitaxial layer on the wide bandgap substrate;
forming a first gate oxide layer on one side of the wide band gap epitaxial layer far away from the wide band gap substrate; the first gate oxide layer is a nitrogen and phosphorus doped silicon oxide layer;
and forming a second gate oxide layer on one side of the first gate oxide layer far away from the wide band gap substrate, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.
Optionally, the step of forming a first gate oxide layer on a side of the wide bandgap epitaxial layer remote from the wide bandgap substrate comprises:
and manufacturing a phosphorus-doped third gate oxide layer based on one side of the wide band gap epitaxial layer far away from the wide band gap substrate.
And annealing the third gate oxide layer doped with phosphorus in a nitrogen-doped atmosphere to form the first gate oxide layer.
Optionally, the fabricating a phosphorus-doped third gate oxide layer based on a side of the wide bandgap epitaxial layer away from the wide bandgap substrate comprises:
forming a phosphorus-doped silicon layer on one side of the wide band gap epitaxial layer far away from the wide band gap substrate by utilizing an in-situ doping process;
and carrying out thermal oxidation on the phosphorus-doped silicon layer to form a third gate oxide layer.
Optionally, the fabricating a P-doped third gate oxide layer based on a side of the wide bandgap epitaxial layer away from the wide bandgap substrate comprises:
manufacturing a polycrystalline silicon layer on the basis of one side of the wide band gap epitaxial layer, which is far away from the wide band gap substrate;
manufacturing a P-doped polycrystalline silicon layer through an ion implantation or diffusion process;
and carrying out thermal oxidation on the polycrystalline silicon layer to form a P-doped third gate oxide layer.
Optionally, the step of forming a second gate oxide layer on a side of the first gate oxide layer away from the wide bandgap substrate comprises:
depositing SiO on the side of the first gate oxide layer far away from the wide band gap substrate 2 Layer of undoped SiO 2 A second gate oxide layer; or the like, or, alternatively,
depositing a polysilicon layer based on the side of the first gate oxide layer away from the wide band gap substrate;
oxidizing the polysilicon layer to form undoped SiO 2 And a second gate oxide layer.
Optionally, the step of forming a second gate oxide layer on a side of the first gate oxide layer away from the wide bandgap substrate comprises:
forming a second gate oxide layer in the nitrogen-doped atmosphere; and the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.
Optionally, the thickness of the first gate oxide layer is smaller than the thickness of the second gate oxide layer.
Optionally, the first gate oxide layer has a thickness of
And/or the presence of a gas in the atmosphere,
the thickness of the second gate oxide layer is
Compared with the prior art, the method has the following beneficial effects:
the application provides a semiconductor device and a manufacturing method thereof, which comprises the steps of firstly providing a wide band gap substrate, then forming a wide band gap epitaxial layer on the wide band gap substrate, and then forming a first gate oxide layer on one side of the wide band gap epitaxial layer, which is far away from the wide band gap substrate; and finally, forming a second gate oxide layer on one side of the first gate oxide layer, which is far away from the wide band gap substrate, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or a non-doped silicon oxide layer. According to the manufacturing method of the semiconductor device, the first gate oxide layer and the second gate oxide layer are manufactured on the basis of the surface of the wide band gap epitaxial layer, and the first gate oxide layer is a silicon oxide layer doped with nitrogen and phosphorus, so that the doping concentration of the interface between the first gate oxide layer and the wide band gap epitaxial layer is high, the interface state density is reduced, and the channel mobility is improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram of a hierarchical structure for manufacturing a semiconductor device according to the prior art.
Fig. 2 is a schematic diagram of another hierarchical structure for manufacturing a semiconductor device according to the prior art.
Fig. 3 is an exemplary flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a first hierarchical structure of a semiconductor device according to an embodiment of the present application.
Fig. 5 is an exemplary flowchart of the sub-step of S106 in fig. 3 provided in an embodiment of the present application.
Fig. 6 is a schematic diagram of a second layer structure of a semiconductor device according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a third hierarchical structure of a semiconductor device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The term "a-based side away from the wide bandgap substrate is made/deposited B" means that for a, two sides are included, a front side and a back side, respectively, with the back side facing the wide bandgap substrate and the front side facing the opposite direction of the wide bandgap substrate, and B is connected to the front side of a. The term "forming B on a" means forming B on the front side of a.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
As described in the background art, the preparation of the gate oxide structure is the core process of the SiC MOSFET device, and the current process for manufacturing the gate oxide structure is as follows:
as shown in FIG. 1, a SiC wide band gap epitaxial layer is grown on a SiC wide band gap substrate, and then the top SiC wide band gap epitaxial layer is oxidized to form SiO by a thermal oxidation process 2 The structure of the gate oxide layer after oxidation is shown in figure 2.
However, prior art SiO formation by thermal oxygen processes 2 In the process, siC/SiO 2 A large number of defects, particularly carbon cluster defects, can occur at the interface, resulting in high interface state density and low channel mobility. The interface state density can be effectively reduced by optimizing the links of the oxidation process and the annealing process of the gate oxide structure, so that the mode commonly used in the industry at present is to oxidize SiC into SiO 2 Thereafter, the SiC/SiO may be passivated by annealing in a nitrogen-doped atmosphere 2 Interface, reducing interface state density.
However, as shown in FIG. 2, sinceOxidized SiO 2 The thickness of the gate oxide is generally 40-60nm, and the thickness is relatively thick, so that after annealing in a high-temperature nitrogen-doped atmosphere, siC/SiO 2 The nitrogen element content at the interface is not substantially high, and there is a limit to the reduction of the interface state density.
In view of the above, in order to solve the above problems, the present application provides a method for manufacturing a semiconductor device, in which a first gate oxide layer and a second gate oxide layer are disposed, and the thickness of the first gate oxide layer is set to be relatively thin and the doping concentration is set to be high, so as to increase the doping concentration at the interface and further reduce the interface state density.
The following is an exemplary description of a method for fabricating a semiconductor device provided in the present application:
as an alternative implementation, referring to fig. 3, the method for manufacturing a semiconductor device includes:
s102, providing a wide band gap substrate.
And S104, forming a wide band gap epitaxial layer on the wide band gap substrate.
S106, forming a first gate oxide layer on one side of the wide band gap epitaxial layer far away from the wide band gap substrate; wherein the first gate oxide layer is a nitrogen and phosphorus doped silicon oxide layer.
And S108, forming a second gate oxide layer on one side of the first gate oxide layer, which is far away from the wide band gap substrate, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or a non-doped silicon oxide layer.
The first gate oxide layer and the second gate oxide layer jointly form a gate oxide structure, and the first gate oxide layer is thinner than the second gate oxide layer, and meanwhile, the first gate oxide layer is a silicon oxide layer doped with nitrogen and phosphorus, and the doping concentration of the first gate oxide layer is higher, so that the doping concentration at the interface of the first gate oxide layer and the wide band gap epitaxial layer is also relatively higher, the interface state density can be reduced, and the channel mobility of the device can be improved.
The materials of the wide band gap substrate and the wide band gap epitaxial layer are not limited in the present application, for example, a SiC wide band gap substrate, a Si wide band gap substrate, a sapphire wide band gap substrate, or the like may be used as the wide band gap substrate, homoepitaxy or heteroepitaxy may be used as the wide band gap epitaxial layer, and for example, a SiC wide band gap substrate and a SiC wide band gap epitaxial layer are taken as an example, and the structure after growing the wide band gap epitaxial layer is shown in fig. 1. Since the epitaxial growth process is relatively mature, the epitaxial growth process is not described in detail, for example, a wide bandgap epitaxial layer may be grown by a vapor phase epitaxial process.
After growing the target thickness of the wide band gap epitaxial layer, referring to fig. 4, it is necessary to continue growing the gate oxide on the surface of the wide band gap epitaxial layer, where the gate oxide is typically SiO 2 The oxide layer, i.e. the first gate oxide layer and the second gate oxide layer are both SiO 2 And (3) a layer. For the convenience of illustration, the gate oxide is SiO 2 The layers are illustrated. Alternatively, in order to remove impurities on the surface of the wide bandgap epitaxial layer, after the wide bandgap epitaxial layer is grown, a standard RCA cleaning process needs to be performed on the wide bandgap epitaxial layer. In addition, the oxide layer provided by the application is the gate oxide, which can be SiO 2 And oxidizing the layer. It should be noted that the ratio of the hierarchical structures in fig. 4 is only illustrative and does not represent an actual ratio, for example, in an actual manufacturing process, the thickness of the first gate oxide layer is relatively thin.
In order to improve the doping concentration at the interface, when the gate oxide structure is manufactured, a first gate oxide layer with higher doping concentration is manufactured on the surface of the wide bandgap epitaxial layer, and then a second gate oxide layer is manufactured, so that the thicknesses of the first gate oxide layer and the second gate oxide layer reach the preset thickness.
As an implementation manner, referring to fig. 5, S106 includes:
and S1061, manufacturing a P-doped third gate oxide layer on the side, far away from the wide band gap substrate, of the wide band gap epitaxial layer.
And S1062, annealing the third gate oxide layer doped with phosphorus in a nitrogen-doped atmosphere to form the first gate oxide layer.
N-type doping refers to doping in which majority electrons are doped, and is typically P (phosphorus) or N (nitrogen), so in the process of the present application, a P-doped third gate oxide layer may be first formed on the surface of the wide bandgap epitaxial layer, and then annealed by an annealing process. Generally, annealing needs to be performed in a high temperature environment, for example, annealing in an atmosphere at 1250 ℃ for 30min and annealing in an atmosphere of argon for 90min.
Through the annealing process, the P element can be pushed to the interface of the gate oxide layer and the wide-band-gap epitaxial layer based on the high-temperature diffusion principle, and the first gate oxide layer is formed. It can be understood that the first gate oxide layer and the third gate oxide layer are actually P-doped gate oxide layers, except that the distribution of the doped P in the third gate oxide layer is more uniform, and the doped P in the first gate oxide layer is mainly distributed at the interface between the gate oxide layer and the wide band gap epitaxial layer because the first gate oxide layer is subjected to an annealing process.
If the wide band gap epitaxial layer adopts SiC wide band gap epitaxial layer, the first gate oxide layer is SiO 2 Layer, then after annealing, actually pushes the P element to SiC/SiO 2 At the interface, siC/SiO 2 The phosphorus element content at the interface is higher, and the channel mobility of the device is improved.
In one implementation, S1061 includes:
s1061-1, forming a phosphorus-doped silicon layer on one side, far away from the wide band gap substrate, of the wide band gap epitaxial layer by utilizing an in-situ doping process;
and S1061-2, performing thermal oxidation on the silicon layer to form a third gate oxide layer.
In this implementation, a specific process for growing the P-doped polysilicon layer is not limited, and for example, in-situ PH doping may be performed by LPCVD (Low Pressure Chemical Vapor Deposition) at 550 ℃ 3 A silicon layer is deposited and then thermally oxidized at a high temperature of 750 c to form a P-doped polysilicon layer, and the P-doped layer structure is shown in fig. 6. Wherein the in-situ doping refers to introducing a gas containing impurities, such as PH, while depositing the silicon layer 3 Or B 2 H 6 So that the silicon layer is uniformly doped. The silicon layer doping of the process is more uniform, the process is simpler, and the cost is lower. Of course, the first gate oxide layer doped with P may also be grown by other processes, for example, CVD process or molecular beam epitaxy process, which is not limited herein.
It should be noted that, in order to ensure higher doping concentration at the interface, the subsequent process can continue to dope on the basis of doping PThe N, N-doped hierarchy is shown in FIG. 7. In order to ensure that the doping concentration in the first gate oxide layer is sufficiently high in this application, the thickness of the first gate oxide layer needs to be set to be low to achieve better doping, and optionally, the thickness of the first gate oxide layer is set to be
In another implementation, S1061 includes:
and S1061-3, manufacturing a polycrystalline silicon layer on the side, far away from the wide band gap substrate, of the wide band gap epitaxial layer.
And S1061-2, manufacturing the P-doped polycrystalline silicon layer through an ion implantation or diffusion process.
And S1061-3, performing thermal oxidation on the polycrystalline silicon layer to form a P-doped third gate oxide layer.
That is, in the present application, not only the in-situ doping process may be used to fabricate the first gate oxide layer, but also the process of depositing intrinsic polysilicon first and then doping may be used to fabricate the P-doped gate oxide layer, for example, a polysilicon thin film may be grown intrinsically by LPCVD, and then a phosphorus-doped gate oxide layer may be formed by ion implantation or furnace tube diffusion process. And oxidizing the polysilicon into silicon dioxide by using a thermal oxidation process to form a P-doped third gate oxide layer.
The third gate oxide layer is manufactured in the mode, on one hand, the SiC thermal oxidation in the prior art is not required to be utilized to form SiO 2 The process avoids the defects of carbon clusters introduced in the thermal oxidation process, reduces the interface state density and improves the channel mobility. On the other hand, in the prior art, the doping concentration of the interface is actually not high due to the integral annealing after the gate oxide structure is manufactured. In the application, annealing is performed after the third gate oxide layer is manufactured, and the thickness of the third gate oxide layer is small and is only
Therefore, the doped P element can be pushed to the interface of the third gate oxide layer and the wide band gap epitaxial layer during annealing to form the first gate oxide layer. So that in the first gate oxide layer, the side close to the wide band gap epitaxial layerThe doping concentration of the wide band gap epitaxial layer is larger than that of the side far away from the wide band gap epitaxial layer, namely the content of P element at the interface is higher, and the mobility of the channel is improved.
To further increase the doping concentration at the interface, in an alternative implementation, S1062 includes:
and annealing the P-doped third gate oxide layer in a nitrogen-doped atmosphere to form a first gate oxide layer.
Alternatively, when annealing the third gate oxide layer, the first gate oxide layer doped with phosphorus and nitrogen may be formed by annealing at 1250 ℃ for 30min in an atmosphere doped with nitrogen, and annealing at 90min in an atmosphere of argon, wherein the atmosphere doped with nitrogen includes, but is not limited to, nitrogen, nitric oxide, nitrous oxide, and the like.
Since the thickness of the first gate oxide layer is relatively thin, only
Therefore, when annealing is carried out in the nitrogen-doped atmosphere, the nitriding effect is better, and the contents of the P element and the N element at the interface are higher; in addition, because the annealing process is also finished at high temperature, N element can be pushed to the interface, the content of P element and N element at the interface is improved, and the channel mobility of the device is further improved.
In an optional implementation mode, the doping concentration of P in the first gate oxide layer is 1E13/cm 3 -1E15/cm 3 The doping concentration of N in the first gate oxide layer is 1E13/cm 3 -1E15/cm 3 . In addition, when the second gate oxide layer is manufactured, the manufacturing process of the second gate oxide layer is not limited in the present application, wherein the second gate oxide layer includes a nitrogen-doped silicon oxide layer and a non-doped silicon oxide layer.
When producing the undoped second gate oxide layer, as an alternative implementation, siO may be deposited on the basis of the side of the first gate oxide layer facing away from the wide-bandgap substrate 2 Layer, thereby forming undoped SiO 2 A second gate oxide layer, e.g. a layer of SiO deposited by an LPCVD process 2 And the medium enables the thickness of the first gate oxide layer and the second gate oxide layer to reach a preset gate oxide thickness set value. For example, the first gate oxide layer has a thickness of
The second gate oxide layer has a thickness of
As another alternative implementation mode, a polysilicon layer can be deposited on the side of the first gate oxide layer far away from the wide-band gap substrate, and then the polysilicon layer is oxidized to form undoped SiO 2 A layer.
When the doped second gate oxide layer is manufactured, as an alternative implementation manner, the second gate oxide layer may be formed in a nitrogen-doped atmosphere, so that the second gate oxide layer doped with N is formed. And the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer. For example, the thickness of the second gate oxide layer is 15 to 80 times of the thickness of the first gate oxide layer, and as an alternative implementation, the thickness of the first gate oxide layer is
The second gate oxide layer has a thickness of
Certainly, after the gate oxide structure is fabricated, processes such as defining an active region and an electrode are also needed, and the processes are conventional processes, so that details are not repeated in the embodiments of the present application.
In summary, the method for fabricating a semiconductor device provided by the present application includes in-situ doping PH 3 Or a silicon film is deposited in an ion implantation mode, so that the silicon film is doped more uniformly, the production efficiency and the production cost are saved, and meanwhile, siC/SiO 2 Phosphorus at the interface can improve the channel mobility of the device. And forming a first gate oxide layer (SiO) by oxidizing the silicon thin film at 750 deg.C 2 Media) to reduce formation of SiO due to thermal oxygen of SiC 2 The carbon cluster generated in the process can reduce the interface state density, and simultaneously, the phosphorus element is further promoted by high-temperature diffusion during annealing, so that the wide-band-gap epitaxial layer and the second-band-gap epitaxial layer are formedAn interface of a gate oxide layer (SiC/SiO) 2 Interface) is higher, and the channel mobility of the device is improved. In addition, the first gate oxide layer is thin, so that the first gate oxide layer is favorable for nitridation with the first gate oxide layer during annealing in the N-doped atmosphere, the N content at the interface is increased, and the channel mobility of the device is further increased.
Based on the foregoing implementation manner, an embodiment of the present application further provides a semiconductor device, which is prepared by the above manufacturing method, where the semiconductor device includes:
the wide band gap epitaxial layer is positioned on the surface of the wide band gap substrate, the first gate oxide layer is positioned on one side, far away from the wide band gap substrate, of the wide band gap epitaxial layer and is a nitrogen and phosphorus doped silicon oxide layer, and the second gate oxide layer is positioned on one side, far away from the wide band gap substrate, of the first gate oxide layer. The second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.
In one implementation manner, the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer, and the doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.
As an implementation manner, in order to ensure that the nitridation effect of the first gate oxide layer is better, the thickness of the first gate oxide layer is smaller, and optionally, the thickness of the first gate oxide layer is
And when the first gate oxide layer is manufactured, the P element and the N element can be pushed to the interface of the first gate oxide layer and the wide band gap epitaxial layer through an annealing process, so that the doping concentration of P at the interface between the wide band gap epitaxial layer and the first gate oxide layer is the maximum.
Optionally, the first gate oxide layer comprises N-doped and P-doped SiO 2 A second gate oxide layer comprising doped or undoped SiO 2 And (3) a layer. And the doping concentration of P in the first gate oxide layer is 1E13/cm 3 -1E15/cm 3 . The doping concentration of N in the first gate oxide layer is 1E14/cm 3 -5E16/cm 3 。
In summary, the present application provides a semiconductor device and a method for fabricating the same, which includes providing a wide bandgap substrate, forming a wide bandgap epitaxial layer on the wide bandgap substrate, and forming a first gate oxide layer on a side of the wide bandgap epitaxial layer away from the wide bandgap substrate; and finally, forming a second gate oxide layer on one side of the first gate oxide layer, which is far away from the wide band gap substrate, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or a non-doped silicon oxide layer. According to the manufacturing method of the semiconductor device, the first gate oxide layer and the second gate oxide layer are manufactured on the basis of the surface of the wide band gap epitaxial layer, and the first gate oxide layer is a silicon oxide layer doped with nitrogen and phosphorus, so that the doping concentration of the interface between the first gate oxide layer and the wide band gap epitaxial layer is high, the interface state density is reduced, and the channel mobility is improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (16)
1. A semiconductor device, characterized in that the semiconductor device comprises:
a wide bandgap substrate;
a wide bandgap epitaxial layer disposed on the wide bandgap substrate;
the first gate oxide layer is arranged on one side, far away from the wide band gap substrate, of the wide band gap epitaxial layer and is a nitrogen and phosphorus doped silicon oxide layer;
a second gate oxide layer disposed on a side of the first gate oxide layer away from the wide bandgap substrate; the second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.
2. The semiconductor device of claim 1, wherein a thickness of the first gate oxide layer is less than a thickness of the second gate oxide layer.
3. The semiconductor device according to claim 2, wherein the first gate oxide layer has a thickness of
And/or the presence of a gas in the gas,
the thickness of the second gate oxide layer is
4. The semiconductor device of claim 1, wherein a doping concentration of phosphorus in the first gate oxide layer is greatest at an interface between the wide bandgap epitaxial layer and the first gate oxide layer.
5. The semiconductor device according to any one of claims 1 to 4, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer, and a nitrogen doping concentration of the first gate oxide layer is larger than a nitrogen doping concentration of the second gate oxide layer.
6. The semiconductor device according to claim 4, wherein a doping concentration of phosphorus in the first gate oxide layer is 1E13/cm 3 -1E15/cm 3 。
7. The semiconductor device according to claim 6, wherein a doping concentration of N in the first gate oxide layer is 1E13/cm 3 -1E15/cm 3 。
8. The semiconductor device according to any one of claims 1 to 7, wherein the wide bandgap substrate is a silicon carbide substrate; and/or
The wide band gap epitaxial layer is a silicon carbide epitaxial layer.
9. A semiconductor device manufacturing method, characterized by comprising:
providing a wide band gap substrate;
forming a wide bandgap epitaxial layer on the wide bandgap substrate;
forming a first gate oxide layer on one side of the wide band gap epitaxial layer far away from the wide band gap substrate; the first gate oxide layer is a nitrogen and phosphorus doped silicon oxide layer;
and forming a second gate oxide layer on one side of the first gate oxide layer far away from the wide band gap substrate, wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.
10. The method of fabricating a semiconductor device according to claim 9, wherein the step of forming a first gate oxide layer on a side of the wide bandgap epitaxial layer remote from the wide bandgap substrate comprises:
manufacturing a phosphorus-doped third gate oxide layer on the basis of one side of the wide band gap epitaxial layer, which is far away from the wide band gap substrate;
and annealing the third gate oxide layer doped with phosphorus in a nitrogen-doped atmosphere to form the first gate oxide layer.
11. The method of fabricating a semiconductor device according to claim 10, wherein fabricating a phosphorus doped third gate oxide layer based on a side of the wide bandgap epitaxial layer remote from the wide bandgap substrate comprises:
forming a phosphorus-doped silicon layer on one side of the wide band gap epitaxial layer far away from the wide band gap substrate by utilizing an in-situ doping process;
and carrying out thermal oxidation on the phosphorus-doped silicon layer to form a third gate oxide layer.
12. The method of fabricating a semiconductor device according to claim 10, wherein fabricating a P-doped third gate oxide layer based on a side of the wide bandgap epitaxial layer remote from the wide bandgap substrate comprises:
manufacturing a polycrystalline silicon layer on the basis of one side of the wide band gap epitaxial layer, which is far away from the wide band gap substrate;
manufacturing a P-doped polycrystalline silicon layer through an ion implantation or diffusion process;
and carrying out thermal oxidation on the polycrystalline silicon layer to form a P-doped third gate oxide layer.
13. The method of fabricating a semiconductor device according to claim 10, wherein the step of forming a second gate oxide layer on a side of the first gate oxide layer remote from the wide bandgap substrate comprises:
depositing SiO on the side of the first gate oxide layer far away from the wide band gap substrate 2 Layer of undoped SiO 2 A second gate oxide layer; or the like, or, alternatively,
depositing a polysilicon layer based on a side of the first gate oxide layer away from the wide bandgap substrate;
oxidizing the polysilicon layer to form undoped SiO 2 A second gate oxide layer.
14. The method of fabricating a semiconductor device according to claim 9, wherein the step of forming a second gate oxide layer on a side of the first gate oxide layer remote from the wide bandgap substrate comprises:
forming a second gate oxide layer in a nitrogen-doped atmosphere; and the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.
15. The method of manufacturing a semiconductor device according to claim 9, wherein a thickness of the first gate oxide layer is smaller than a thickness of the second gate oxide layer.
16. The method of manufacturing a semiconductor device according to claim 9, wherein the first gate oxide layer has a thickness of
And/or the presence of a gas in the gas,
the second gate oxide layer has a thickness of
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| EP3021353A4 (en) * | 2013-07-11 | 2017-02-15 | Fuji Electric Co., Ltd. | Silicon-carbide semiconductor device and method for manufacturing silicon-carbide semiconductor device |
| CN111326573A (en) * | 2018-12-14 | 2020-06-23 | 深圳比亚迪微电子有限公司 | Field effect transistor, preparation method and electronic equipment |
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| CN114300533A (en) * | 2021-12-27 | 2022-04-08 | 浙江大学杭州国际科创中心 | Gate oxide structure and preparation method |
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