CN115715087A - Pickup structure of memory device and method of manufacturing the same - Google Patents

Abstract

The invention provides a pick-up structure of a storage device and a manufacturing method thereof. The substrate has a memory cell region and a peripheral pickup region adjacent thereto. The pick-up electrode strips are parallel to the first direction and are arranged on the substrate in an extending mode along a second direction different from the first direction. Each pickup electrode bar includes a main body portion located in the peripheral pickup region and an extension portion extending from the main body portion to the memory cell region. The main body portion is defined by a plurality of fork-shaped patterns of the first mask layer. The extension part has a width smaller than that of the main body part and has a side wall surface aligned with that of the main body part.

Description

Pickup structure of memory device and method of manufacturing the same

Technical Field

The present invention relates to a semiconductor structure, and more particularly to a pick-up (pick-up) structure for a memory device and a method of fabricating the same.

Background

In a semiconductor memory device process, a Self-aligned Double Patterning (SADP) process is used to fabricate small-sized word lines, select gates, and pick-up (pick-up) electrodes corresponding to the connected word lines. However, in the SADP process, if the overlay shift (overlay shift) between the etching masks at different positions exceeds the process tolerance, the line width of the select gate is difficult to reach the target dimension. To improve overlay control, high resolution photolithography processes must be employed. Without increasing the overlay control, the select gates may be patterned prior to removing the sacrificial material layer. However, when the pickup electrode is defined later, the line width of the pickup electrode is difficult to reach the target size. The yield and reliability of the memory device will be reduced when the contact is made above the pick-up electrode. Therefore, there is a need for a novel method of manufacturing a memory device that can solve or improve the above-mentioned problems.

Disclosure of Invention

The invention provides a pickup structure of a storage device, which comprises a substrate and a plurality of pickup electrode strips. The substrate has a memory cell region and a peripheral pickup region adjacent thereto. The plurality of pickup electrode strips are parallel to a first direction, extend along a second direction different from the first direction and are arranged on the substrate. Each pick-up electrode strip comprises a main body part and an extension part. The main body portion is located in the peripheral pick-up area and is defined by a plurality of fork-shaped patterns of a first mask layer. The extension part extends from the main body part to the memory unit area, wherein the extension part has a width smaller than that of the main body part, and the extension part has a side wall surface which is aligned with a side wall surface of the main body part.

Each of the fork-shaped patterns includes a first bar pattern, a second bar pattern and a connection pattern, the first bar pattern and the second bar pattern are parallel to the first direction and extend along the second direction, the connection pattern is used for connecting the first bar pattern and the second bar pattern, wherein the first bar pattern and the second bar pattern are used for defining the main body portion.

A multi-layer resist structure covering the first and second bar patterns for forming the extension portion connected to the main body portion by using the connection pattern, wherein the first and second bar patterns form the main body portion.

The pick-up electrode strips at least comprise a first pick-up electrode strip, a second pick-up electrode strip, a third pick-up electrode strip and a fourth pick-up electrode strip which are sequentially arranged along the second direction, and the main body parts of the pick-up electrode strips have the same width.

One of the fork-shaped patterns defines a first pick-up electrode strip and a second pick-up electrode strip, and the other of the fork-shaped patterns defines a third pick-up electrode and a fourth pick-up electrode. The first and second pickup electrode strips are symmetrically arranged with each other, and the third and fourth pickup electrode strips are symmetrically arranged with each other.

The extension portion of the first pick-up electrode strip is spaced apart from the extension portion of the second pick-up electrode strip by a first distance, and the main body portion of the first pick-up electrode strip is spaced apart from the main body portion of the second pick-up electrode strip by a second distance, and wherein the first distance is greater than the second distance.

The extension of the third pick-up electrode strip is separated from the extension of the fourth pick-up electrode strip by a third distance, and the main body of the third pick-up electrode strip is separated from the main body of the fourth pick-up electrode strip by a fourth distance, and wherein the third distance is greater than the fourth distance and the second distance.

The extension portion of the second pick-up electrode strip is spaced apart from the extension portion of the third pick-up electrode strip by a third distance, and the main body portion of the second pick-up electrode strip is spaced apart from the main body portion of the third pick-up electrode strip by a fourth distance, and wherein the third distance is equal to the fourth distance and the second distance.

The pick-up electrode strips at least comprise a first pick-up electrode strip, a second pick-up electrode strip, a third pick-up electrode strip and a fourth pick-up electrode strip which are sequentially arranged along the second direction, wherein the main body part of the first pick-up electrode strip and the main body part of the second pick-up electrode strip have a first length, the main body part of the third pick-up electrode strip and the main body part of the fourth pick-up electrode strip have a second length, and the first length is greater than the second length.

The invention also provides a manufacturing method of the memory device, which comprises providing a substrate; a first mask layer, a sacrificial material layer and a second mask layer are sequentially formed on a substrate, wherein the substrate is provided with a memory unit area and a peripheral pick-up area adjacent to the memory unit area.

Forming a first pattern and a second pattern in the second mask layer, wherein the first pattern corresponds to the memory cell region and includes a plurality of first bar patterns and a plurality of second bar patterns arranged in parallel to each other, and the second pattern corresponds to the peripheral pickup region and includes a plurality of fork-shaped patterns connected to the plurality of second bar patterns, wherein the fork-shaped patterns include a third bar pattern, a fourth bar pattern, and a connection pattern, the third bar pattern and the fourth bar pattern are parallel to a first direction, and the connection pattern is used to connect the third bar pattern and the fourth bar pattern; transferring the first pattern and the second pattern of the second mask layer to a sacrificial material layer to enable the sacrificial material layer to be provided with a first strip pattern, a second strip pattern and a fork-shaped pattern; removing the second mask layer with the first pattern and the second pattern; forming a plurality of spacing layers on the first mask layer, so that two opposite side walls of each first bar-shaped pattern and two opposite side walls of each second bar-shaped pattern of the sacrificial material layer are provided with a corresponding spacing layer; performing first etching on the first mask layer by using the sacrificial material layer and the spacing layer as an etching mask; after the first etching, removing the sacrificial material layer and leaving the spacer layer; and performing a second etching on the first mask layer by using the spacer layer as an etching mask to enable the first mask layer to have a third pattern.

The method further includes forming a multi-layer resist structure on the substrate before the second etching and covering the spacer layer and the first mask layer, such that the spacer layer and the multi-layer resist structure are used as an etching mask during the second etching.

The multi-layer resist structure further covers the spacer layer of the first stripe pattern, the third stripe pattern and the fourth stripe pattern and the first mask layer, so that the connection pattern is removed during the second etching.

The manufacturing method of the memory device further comprises the steps of forming a target layer on the substrate before sequentially forming the first mask layer, the sacrificial material layer and the second mask layer; and transferring the third pattern into the target layer after forming the third pattern.

After the third pattern is transferred into the target layer, a plurality of pickup electrode stripes parallel to a first direction are formed on the target layer corresponding to the peripheral pickup area, and the pickup electrode stripes are arranged on the substrate along a second direction different from the first direction. Each pick-up electrode strip comprises a main body part and an extension part. The main body part is located in the peripheral pick-up area, wherein the main body part is defined by a third strip-shaped pattern and a fourth strip-shaped pattern. The extension part extends from the main body part to the memory unit area, wherein the extension part has a width smaller than that of the main body part, and a side wall surface of the extension part is aligned with a side wall surface of the main body part, and the extension part is formed by etching the connecting pattern.

The main body portions of the pick-up electrode bars have the same width. The pick-up electrode strips at least comprise a first pick-up electrode strip, a second pick-up electrode strip, a third pick-up electrode strip and a fourth pick-up electrode strip which are sequentially arranged along the second direction, the main body parts of the first pick-up electrode strip and the second pick-up electrode strip have a first length, the main body parts of the third pick-up electrode strip and the fourth pick-up electrode strip have a second length, and the first length is greater than the second length.

Drawings

FIG. 1 is a schematic plan view of a mask pattern layer used for manufacturing a memory device according to an embodiment of the present invention;

FIGS. 2A-2H, 3A-3H, and 4A-4H are cross-sectional views of memory devices at various stages of manufacture according to various embodiments of the present invention, wherein FIG. 2A is a cross-sectional view taken along line I-I ' of FIG. 1, FIG. 3A is a cross-sectional view taken along line II-II ' of FIG. 1, and FIG. 4A is a cross-sectional view taken along line III-III ' of FIG. 1;

FIG. 5 is a schematic plan view of a mask structure for fabricating a memory device according to an embodiment of the present invention; and

FIG. 6 is a schematic plan view of a target layer for fabricating a memory device according to an embodiment of the invention.

Reference numbers:

100 substrate

101a first pick-up electrode strip

101b second pick-up electrode strip

101c third pick-up electrode strip

101d fourth pick-up electrode strip

102 target layer

102a1 select gate structure

102a2 word line structure

102v2 extension

102z main body part

103,105 side wall surfaces

110,130 hard mask layer

110a1,120a1,130a1,132a1 first stripe pattern

110a2,120a2,130a2,132a2 second stripe pattern

110v1,120v1,130v1,132v connection pattern

110x1,120x1,130x1,132x third stripe pattern

110y1,120y1,130y1,132y fourth stripe pattern

110a3 fifth stripe pattern

110v2 sixth stripe pattern

120 layers of sacrificial material

120a3,130a3 first striped Pattern after trimming

120a4,130a4 second Bar Pattern after trimming

120v2,130v2 connection pattern after trimming

120x2,130x2 third Bar Pattern after trimming

120y2,130y2 fourth striped Pattern after trimming

132 mask pattern layer

132b fork-shaped pattern

140 spacer liner

140a spacer layer

150 bottom layer

152 intermediate layer

154 Top Pattern layer

154a seventh striped pattern

156 multilayer resist structure

d1 first distance

d2 second distance

d3 third distance

d4 fourth distance

d5 fifth distance

d6 sixth distance

L1: first length

L2 is the second length

R1 memory cell region

R2 peripheral pickup area

W1 first line width

W2 second line width

W3 third line width

Detailed Description

As shown in fig. 1, fig. 2A, fig. 3A, and fig. 4A, a substrate 100 having a memory cell region R1 and a peripheral pickup region R2 adjacent thereto is provided. A target layer 102, a hard mask layer 110, a sacrificial material layer 120, and a multi-layer mask structure are sequentially formed on the substrate 100 to cover the memory cell region R1 and the periphery pickup region R2 of the substrate 100. The target layer 102 may be a single layer or have a multi-layer structure. When the target layer 102 is a single layer, the material of the target layer 102 may include a metal or other suitable conductive material. In addition, when the target layer 102 has a multi-layer structure, the target layer 102 may include a conductive layer and one or more dielectric layers disposed thereon.

The hard mask layer 110 may comprise polysilicon or other suitable mask material. In addition, the sacrificial material layer 120 may include carbon or other suitable material. The multi-layered mask structure includes an optional hard mask layer 130 and a mask pattern layer 132 (also referred to as a second mask layer) disposed thereon. The mask pattern layer 132 may include a photoresist material and may be formed through a photolithography process. The hard mask layer 130 may serve as an anti-reflective layer and may comprise silicon nitride, silicon oxynitride, or other suitable anti-reflective material. The multi-layer mask structure is used as an etching mask for a subsequent etching process, and the mask pattern layer 132 has a first pattern and a second pattern corresponding to the memory cell region R1 and the peripheral pickup region R2 of the substrate 100, respectively. Specifically, the first pattern includes a plurality of first bar patterns 132a1 and a plurality of second bar patterns 132a2 arranged in parallel. The line width of the first bar pattern 132A1 is greater than the line width of the second bar pattern 132A2, as shown in fig. 1 and 2A. The first stripe pattern 132a1 is used to define a select gate of the memory device, and the second stripe pattern 132a2 is used to define a word line of the memory device.

In addition, the second pattern includes a plurality of fork-shaped patterns 132b (as shown in fig. 1), wherein the fork-shaped patterns 132b are correspondingly connected to the second bar-shaped patterns 132a2. As shown in fig. 1, the fork-shaped pattern 132b further includes a connection pattern 132v, a third bar pattern 132x, and a fourth bar pattern 132y. The third bar pattern 132x and the fourth bar pattern 132y are used to define a pickup electrode bar of a portion of the memory device. As shown in fig. 1, the third and fourth stripe patterns 132x and 132y are parallel to the first direction, extend along a second direction different from the first direction, and are arranged on the substrate 100.

Next, referring to fig. 2B, fig. 3B, and fig. 4B, the first pattern and the second pattern of the mask pattern layer 132 are sequentially transferred into the underlying hard mask layer 130 and the sacrificial material layer 120 to expose the upper surface of the hard mask layer 110. The hard mask layer 130 has a first bar pattern 130a1 and a plurality of second bar patterns 130a2 corresponding to the first bar pattern 132a1 and the second bar pattern 132a2 on the substrate 100 of the memory cell region R1. The sacrificial material layer 120 also has a first bar pattern 120a1 and a second bar pattern 120a2 corresponding to the first bar pattern 132a1 and the second bar patterns 132a2 on the substrate 100 of the memory cell region R1, as shown in fig. 2B.

The hard mask layer 130 and the sacrificial material layer 120 respectively have a connection pattern 130v1 and a connection pattern 120v1 corresponding to the connection pattern 132v on the substrate 100 in the peripheral pick-up region R2, as shown in fig. 3B. The hard mask layer 130 and the sacrificial material layer 120 respectively have a third stripe pattern 130x1 and a third stripe pattern 120x1 corresponding to the third stripe pattern 132x, and a fourth stripe pattern 130y1 and a fourth stripe pattern 120y1 corresponding to the fourth stripe pattern 132y1, on the substrate 100 in the peripheral pickup region R2, as shown in fig. 4B. The patterned hard mask layer 130 and the patterned sacrificial material layer 120 may be formed by a suitable etching process.

Referring to fig. 2C, 3C and 4C, the mask pattern layer 132 having the first pattern and the second pattern is removed to expose sidewalls and upper surfaces of the first bar pattern 130a1, the second bar pattern 130a2, the connection pattern 130v1, the third bar pattern 130x1 and the fourth bar pattern 130y1 and an upper surface of the hard mask layer 110. In some embodiments, a selective trimming (trimming) process may be performed to reduce line widths of the first, second, third, and fourth bar patterns 130a1, 130v1, 120v1,130 x1,120x1, and 130y1, 120y1, the second, and third bar patterns 130a1, 120a2, the connection patterns 130v1, 120v1, and the fourth bar patterns 130y1, 120y 1. After the trimming process is performed, trimmed first bar patterns 130a3 and 120a3 and trimmed second bar patterns 130a4 and 120a4 are formed on the substrate 100 of the memory cell region R1 (as shown in fig. 2C). The trimmed connection patterns 130v2 and 120v2 (as shown in fig. 3C), the trimmed third bar patterns 130x2 and 120x2, and the trimmed fourth bar patterns 130y2 and 120y2 (as shown in fig. 4C) are formed on the substrate 100 in the peripheral pickup region R2. Thereafter, a spacer liner 140 is formed over the substrate 100 to conformably cover the resulting structure after the trimming process.

Next, referring to fig. 2D, 3D and 4D, a plurality of spacers 140a are formed on the hard mask layer 110 by etching the spacer material liner 140. For example, an anisotropic etching process is performed on the spacer liner 140, so that the patterned sacrificial material layer 120 has corresponding spacers 140a on two opposite sidewalls of the trimmed first bar patterns 120a3, the trimmed second bar patterns 120a4, the trimmed connection patterns 120v2, the trimmed third bar patterns 120x2, and the trimmed fourth bar patterns 120y2. The patterned hard mask layer 130 is then removed from over the patterned sacrificial material layer 120. That is, the trimmed first bar pattern 130a3, the trimmed second bar pattern 130a4, the trimmed connection pattern 130v2, the trimmed third bar pattern 130x2, and the trimmed fourth bar pattern 130y2 are removed to expose the trimmed first bar pattern 120a3, the trimmed second bar pattern 120a4, the trimmed connection pattern 120v2, the trimmed third bar pattern 120x2, and the fourth bar pattern 120y2. Since the post-trimming connection patterns 120v2 on the substrate 100 of the peripheral pickup region R2 are connected to the post-trimming third bar patterns 120x2 and the post-trimming fourth bar patterns 120y2, the two spacer layers 140a located between two adjacent post-trimming connection patterns 120v2 are connected to each other. Although not shown, the connected spacers 140a may be further patterned to ensure that the two spacers 140a between two adjacent trimmed connecting patterns 120v2 are spaced apart from each other.

Then, an etching process is performed on the hard mask layer 110 to expose a portion of the upper surface of the target layer 102 by using the patterned sacrificial material layer 120 and the spacer layer 140a as an etching mask. The etching process first defines the select gate pattern in the memory cell region R1. Specifically, the etching process forms a first stripe pattern 110a1 and a second stripe pattern 110a2 in the hard mask layer 110 on the substrate 100 of the memory cell region R1 (as shown in fig. 2D). A connection pattern 110v1 (as shown in fig. 3D), a third stripe pattern 120y2 and a fourth stripe pattern 110y1 (as shown in fig. 4D) are formed in the hard mask layer 110 on the substrate 100 in the peripheral pick-up region R2. The first stripe pattern 110a1 corresponding to the memory cell region R1 serves as a select gate pattern, and a line width W1 of the first stripe pattern 110a1 is substantially equal to a target line width of the select gate pattern.

Next, the patterned sacrificial material layer 120 having the trimmed first stripe patterns 120a3, the trimmed second stripe patterns 120a4, the trimmed connecting patterns 120v2, the trimmed third stripe patterns 120x2, and the trimmed fourth stripe patterns 120y2 in fig. 2D, 3D, and 4D is removed, and the spacer layer 140a on the patterned hard mask layer 110 is left, so that the structure is shown in fig. 2E, 3E, and 4E. The removal step may be performed by a suitable etching process.

Next, referring to fig. 2F, fig. 3F and fig. 4F, a mask structure 156 is formed on the substrate 100 and covers the spacer layer 140a and the patterned hard mask layer 110, wherein the mask structure 156 does not cover the connection pattern 110v1 of fig. 3F. After the mask structure 156 is patterned, it serves as an etch mask for the subsequent etching of the patterned hard mask layer 110. Mask structure 156 is a multi-layer resist structure. For example, the multi-layer resist structure is a three-layer resist structure and may include a bottom layer 150, an intermediate layer 152, and a top pattern layer 154.

The bottom layer 150 may serve as a planar layer to form a substantially planar upper surface over the structure shown in fig. 2F and 4F. The bottom layer 150 may be a Spin On Carbon (SOC) layer or may be made of other materials with anti-reflective properties. The intermediate layer 152 may provide a hard mask characteristic to the overlying top patterned layer 154, and the material of the intermediate layer 152 may include silicon oxide, silicon nitride, silicon oxycarbide, or other suitable mask material. In addition, the top pattern layer 154 has a seventh stripe pattern 154a similar to and corresponding to the first stripe pattern 110a1 as the select gate pattern, as shown in fig. 2F. The seventh stripe pattern 154a exposes a word line region (not shown) to be formed in the memory cell region R1 and serves as an etch stop region to prevent the select gate pattern thereunder from being etched during a subsequent etching process. As a result, the line width of the select gate pattern (i.e., the first stripe pattern 110a 1) can be maintained. The top pattern layer 154 corresponding to the peripheral pickup region R2 has a large non-pattern 154b (as shown in fig. 4F) to retain the patterns defined by the third and fourth stripe patterns 110x1 and 110y 1. The top patterning layer 154 may include a photoresist material and may be formed by a photolithography process.

Next, referring to fig. 2G, fig. 3G, and fig. 4G, the patterned hard mask layer 110 is etched to expose the upper surface of the underlying target layer 102 by using the remaining spacer layer 140a and the multi-layer resist structure 156 as an etching mask. The hard mask layer 110 is patterned again to form a third pattern therein. After etching, the remaining bottom layer 150, intermediate layer 152, and top pattern layer 154 are removed.

The third pattern includes a fifth stripe pattern 110a3 (i.e., a word line pattern) corresponding to the memory cell region R1 and a previously formed first stripe pattern 110a1 (i.e., a select gate pattern), as shown in fig. 2G. The line width of the fifth stripe pattern 110a3 is substantially determined by the width of the spacer layer 140a, and the width of the spacer layer 140a is controlled by the thickness of the spacer material layer 140. The third pattern also includes a sixth stripe pattern 110v2 (shown in fig. 3G), a third stripe pattern 110x1, and a fourth stripe pattern 110y1 (shown in fig. 4G) corresponding to the peripheral pickup region R2. The sixth bar pattern 110v2 is used to connect the third bar pattern 110x1 and the fourth bar pattern 110y1 to word lines of the memory device, wherein the third bar pattern 110x1 and the fourth bar pattern 110y1 together constitute a pickup electrode pattern.

As shown in fig. 2F and 2G, a select gate pattern is first defined in the hard mask layer 110. Therefore, after the hard mask layer 110 is etched by using the seventh stripe pattern 154a as an etching mask, the first line width W1 of the first stripe pattern 110a1 as a select gate pattern remains unchanged even if the seventh stripe pattern 154a and the underlying spacer layer 140a are misaligned. The selection gate pattern is defined in advance, so that the overlay tolerance can be effectively increased in the subsequent process.

As shown in fig. 3F and 3G, during the formation of the selection gate pattern (i.e., the first stripe pattern 110a 1) on the substrate 100 of the memory cell region R1 by the hard mask layer 110, a connection pattern 110v1 is simultaneously formed on the substrate 100 of the peripheral pickup region R2. Therefore, after the hard mask layer 110 is etched using the spacer layer 140a as an etching mask, the second line width W2 of the sixth stripe pattern 110v2 is substantially equal to the width of the spacer layer 140a.

As shown in fig. 4F and 4G, the third stripe pattern 110x1 and the fourth stripe pattern 110y1 in the hard mask layer 110 have been defined to have the pickup electrode pattern, so that the third line width W3 of the third stripe pattern 110x1 and the fourth stripe pattern 110y1 as the pickup electrode pattern remains unchanged even if the overlay shift occurs between the non-pattern 154b and the underlying spacer layer 140a after the hard mask layer 110 is etched using the large non-pattern 154b as an etching mask. The first definition of the pick-up electrode pattern can effectively increase the overlay tolerance in the subsequent process.

Referring to FIG. 5, a mask structure 156 for fabricating a memory device is shown in plan view. Mask structure 156 shown in fig. 5 corresponds to mask structure 156 shown in fig. 2F, 3F, and 4F. As shown in fig. 5, the mask structure 156 covers the third and fourth stripe patterns 110x1 and 110y1 and the first stripe pattern 110a1 having the third line width W3, and exposes the second stripe pattern 110a2 and the connection pattern 110v1.

Next, referring to fig. 2H, 3H, and 4H, the third pattern in the patterned hard mask layer 110 is transferred into the target layer 102. The target layer 102 is etched using the hard mask layer 110 having the third pattern as an etching mask to form a third pattern in the target layer 102.

After the above etching is performed, a select gate structure 102a1 having a target line width (i.e., a first line width W1) and a plurality of word line structures 102a2 having the target line width are formed on the substrate 100 of the memory cell region R1, as shown in fig. 2H. A pickup electrode structure including a plurality of pickup electrode bars is formed on the substrate 100 in the peripheral pickup region R2, and each pickup electrode bar includes an extension portion 102v2 (as shown in fig. 3H) and a main body portion 102z (as shown in fig. 4H), wherein the main body portion 102z is defined by a third bar pattern 110x1 and a fourth bar pattern 110y1 having a third line width W3.

Fig. 6 is a schematic plan view of a target layer 102 for manufacturing a memory device. The target layer 102 of fig. 6 is manufactured using the method shown in fig. 2A-2H, 3A-3H, and 4A-4H. As shown in fig. 6, the pickup electrode bars are parallel to a first direction (e.g., Y direction) and arranged on the substrate 100 in a second direction (e.g., X direction) different from the first direction. To simplify the drawing, fig. 6 only depicts two sets of pickup electrode structures that are symmetrical up and down, and each set of pickup electrode structures includes ten pickup electrode bars. However, it will be appreciated that the number of pick-up electrode strips depends on design requirements and is not limited to the embodiment shown in FIG. 6.

Each pickup electrode bar includes an extension portion 102v2 and a body portion 102z. The main body portion 102z is located in the peripheral pickup region R2, and the extension portion 102v2 extends from the main body portion 102z to the word line structure 102a2 of the memory cell region R1. The width of the extension portion 102v2 (which is substantially equal to the second line width W2 of the sixth stripe pattern 110v 2) is smaller than the width of the main body portion 102z (which is substantially equal to the third line width W3 of the third stripe pattern 110x1 and the fourth stripe pattern 110y 1), and the extension portion 102v2 has a sidewall surface 103 that is aligned with a sidewall surface 105 of the main body portion 102z.

In order to simplify the explanation of the configuration of the pick-up electrode structure, only the first pick-up electrode stripe 101a, the second pick-up electrode stripe 101b, the third pick-up electrode stripe 101c, and the fourth pick-up electrode stripe 101d, which are sequentially arranged in the second direction, are taken as an example here. In this example, the body portions 102z of the first and second pickup electrode strips 101a and 101b have the same first length L1, and the body portions 102z of the third and fourth pickup electrode strips 101c and 101d have the same second length L2, where the first length L1 is greater than (or equal to) the second length L2.

The first and second pickup electrode bars 101a and 101b are arranged symmetrically to each other, and the third and fourth pickup electrode bars 101c and 101d are arranged symmetrically to each other. In addition, the second and third pickup electrode bars 101b and 101c are substantially symmetrically arranged with respect to each other. Further, the first, second, third and fourth pickup electrode bars 101a, 101b, 101c and 101d all have a third width W3.

A first distance d1 separating the extension portion 102v2 of the first pickup electrode bar 101a from the extension portion 102v2 of the second pickup electrode bar 101b is larger than a second distance d2 separating the main body portion 102z of the first pickup electrode bar 101a from the main body portion 102z of the second pickup electrode bar 101 b. The third distance d3 separating the extension 102v2 of the third pick-up electrode strip 101c from the extension 102v2 of the fourth pick-up electrode strip 101d is greater than the fourth distance d4 separating the body portion 102z of the third pick-up electrode strip 101c from the body portion 102z of the fourth pick-up electrode strip 101 d.

The fifth distance d5 separating the extension 102v2 of the second pick-up electrode strip 101b from the extension 102v2 of the third pick-up electrode strip 101c is substantially equal to the sixth distance d6 separating the body portion 102z of the second pick-up electrode strip 101b from the body portion 102z of the third pick-up electrode strip 101c, wherein the second distance d2 is substantially equal to the fourth distance d4 and the sixth distance d6.

Since the select gate pattern and the fork-shaped pattern are defined in the memory cell region and the peripheral pick-up region respectively before removing the patterned sacrificial material layer, the overlay tolerance can be effectively increased. When the target line widths of the selected gate pattern and the fork-shaped pattern are reduced along with the reduction of the size of the storage device, the original photoetching process can be adopted without adopting a high-resolution photoetching process, and the increase of the manufacturing cost is further avoided.

Before etching, a plurality of fork-shaped patterns are formed in the peripheral pick-up area in advance by utilizing a photoetching process to serve as an etching barrier layer. Therefore, after the pick-up electrode pattern is defined by the third strip pattern and the fourth strip pattern of the fork-shaped pattern, the main body portion of the pick-up electrode pattern can maintain the target line width without being influenced by the overlapping offset of the multilayer resist structure and the pick-up electrode pattern. In this way, the line width of the main body portion of the pickup electrode bar is uniform and greater than the line width of the extension portion to have a paddle (paddle) shape, so that a contact can be easily formed above the main body portion of the pickup electrode bar. That is, the contact and the pick-up electrode bar can have a robust and reliable electrical connection, thereby increasing the yield and reliability of the memory device.

Although the present invention has been described with reference to exemplary embodiments, it should be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention is subject to the claims.

Claims (10)

1. A pickup structure for a storage device, comprising:

a substrate having a memory cell region and a peripheral pickup region adjacent thereto; and

a plurality of pickup electrode bars are parallel to a first direction, extend along a second direction different from the first direction, and are arranged on the substrate, wherein each pickup electrode bar comprises:

a main body portion located in the peripheral pick-up region, wherein the main body portion is defined by a plurality of fork-shaped patterns of a first mask layer; and

an extension portion extending from the main body portion to the memory cell region, wherein the extension portion has a width smaller than a width of the main body portion, and the extension portion has a sidewall surface aligned with a sidewall surface of the main body portion.

2. The pickup structure of claim 1, wherein each of the fork-shaped patterns comprises a first bar pattern, a second bar pattern, and a connection pattern, the first bar pattern and the second bar pattern extending parallel to the first direction and along the second direction, the connection pattern for connecting the first bar pattern and the second bar pattern, wherein the first bar pattern and the second bar pattern are for defining the body portion, wherein a multi-layer resist structure is overlaid on the first bar pattern and the second bar pattern for forming the extension portion connected to the body portion using the connection pattern, wherein the first bar pattern and the second bar pattern form the body portion.

3. The pickup structure of the storage device as claimed in claim 1, wherein the pickup electrode bars include at least a first pickup electrode bar, a second pickup electrode bar, a third pickup electrode bar and a fourth pickup electrode bar sequentially arranged along the second direction, and wherein the main body portions of the pickup electrode bars have the same width, wherein one of the fork-shaped patterns defines the first pickup electrode bar and the second pickup electrode bar, and the other of the fork-shaped patterns defines the third pickup electrode bar and the fourth pickup electrode bar, wherein the first pickup electrode bar and the second pickup electrode bar are symmetrically arranged with respect to each other, and the third pickup electrode bar and the fourth pickup electrode bar are symmetrically arranged with respect to each other, wherein the extension portion of the first pickup electrode bar is spaced apart from the extension portion of the second pickup electrode bar by a first distance, and the main body portion of the first pickup electrode bar is spaced apart from the main body portion of the second pickup electrode bar by a second distance, and wherein the first distance is greater than the second distance.

4. The pick-up structure of a memory device as claimed in claim 3, wherein the extension of the third pick-up electrode strip is separated from the extension of the fourth pick-up electrode strip by a third distance and the main body portion of the third pick-up electrode strip is separated from the main body portion of the fourth pick-up electrode strip by a fourth distance, and wherein the third distance is greater than the fourth distance and the second distance, wherein the extension of the second pick-up electrode strip is separated from the extension of the third pick-up electrode strip by a third distance and the main body portion of the second pick-up electrode strip is separated from the main body portion of the third pick-up electrode strip by a fourth distance, and wherein the third distance is equal to the fourth distance and the second distance.

5. The pickup structure of claim 1, wherein said pickup electrode strips comprise at least a first pickup electrode strip, a second pickup electrode strip, a third pickup electrode strip and a fourth pickup electrode strip arranged in sequence along said second direction, and wherein said main body portion of said first pickup electrode strip and said main body portion of said second pickup electrode strip have a first length, said main body portion of said third pickup electrode strip and said main body portion of said fourth pickup electrode strip have a second length, wherein said first length is greater than said second length.

6. A method of manufacturing a memory device, comprising:

providing a substrate;

sequentially forming a first mask layer, a sacrificial material layer and a second mask layer on the substrate, wherein the substrate is provided with a memory unit area and a peripheral pick-up area adjacent to the memory unit area;

forming a first pattern and a second pattern in the second mask layer, wherein the first pattern corresponds to the memory cell region and includes a plurality of first stripe patterns and a plurality of second stripe patterns arranged in parallel to each other, and the second pattern corresponds to the peripheral pickup region and includes a plurality of fork patterns connected to the plurality of second stripe patterns, wherein the fork patterns include a third stripe pattern, a fourth stripe pattern, and a connection pattern, the third stripe pattern and the fourth stripe pattern are parallel to a first direction, and the connection pattern is used to connect the third stripe pattern and the fourth stripe pattern;

transferring the first pattern and the second pattern of the second mask layer to the sacrificial material layer, so that the sacrificial material layer has the first bar pattern, the second bar pattern, and the fork pattern;

removing the second mask layer with the first pattern and the second pattern;

forming a plurality of spacing layers on the first mask layer, so that two opposite side walls of each first bar-shaped pattern and two opposite side walls of each second bar-shaped pattern of the sacrificial material layer are provided with a corresponding spacing layer;

performing first etching on the first mask layer by using the sacrificial material layer and the spacing layer as an etching mask;

after the first etching, removing the sacrificial material layer and leaving the spacing layer; and

and performing second etching on the first mask layer by using the spacing layer as an etching mask to enable the first mask layer to have a third pattern.

7. The method of manufacturing a memory device according to claim 6, further comprising:

before the second etching, forming a multilayer resist structure on the substrate and covering the spacer layer and the first mask layer, so that during the second etching, the spacer layer and the multilayer resist structure are used as an etching mask, wherein the multilayer resist structure also covers the spacer layer of the first bar-shaped pattern, the third bar-shaped pattern and the fourth bar-shaped pattern and the first mask layer, so that the connection pattern is removed during the second etching.

8. The method for manufacturing a memory device according to claim 7, further comprising:

forming a target layer on the substrate before sequentially forming the first mask layer, the sacrificial material layer and the second mask layer; and

after forming the third pattern, transferring the third pattern into the target layer.

9. The method of claim 8, wherein after transferring the third pattern into the target layer, the target layer corresponding to the peripheral pickup region forms a plurality of pickup electrode stripes parallel to a first direction, and the pickup electrode stripes are arranged on the substrate along a second direction different from the first direction, and wherein each pickup electrode stripe comprises:

a main body portion located in the peripheral pick-up region, wherein the main body portion is defined by the third bar pattern and the fourth bar pattern; and

an extension portion extending from the main body portion to the memory cell region, wherein the extension portion has a width smaller than a width of the main body portion, and the extension portion has a sidewall surface aligned with a sidewall surface of the main body portion, wherein the extension portion is formed by etching the connection pattern.

10. The method of claim 9, wherein the main body portions of the pick-up electrode strips have the same width, wherein the pick-up electrode strips include at least a first pick-up electrode strip, a second pick-up electrode strip, a third pick-up electrode strip and a fourth pick-up electrode strip arranged in sequence along the second direction, and the main body portions of the first and second pick-up electrode strips have a first length and the main body portions of the third and fourth pick-up electrode strips have a second length, wherein the first length is greater than the second length.

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