CN113611702B - Semiconductor memory device and method for forming semiconductor device - Google Patents
Semiconductor memory device and method for forming semiconductor device Download PDFInfo
- Publication number
- CN113611702B CN113611702B CN202110891793.0A CN202110891793A CN113611702B CN 113611702 B CN113611702 B CN 113611702B CN 202110891793 A CN202110891793 A CN 202110891793A CN 113611702 B CN113611702 B CN 113611702B
- Authority
- CN
- China
- Prior art keywords
- pattern
- widening
- patterns
- width
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
The invention discloses a semiconductor memory device and a method for forming the semiconductor memory device. The first pattern is arranged on the substrate and extends along a first direction, the first pattern comprises an extension part and two end points, the two end points respectively comprise a first end pattern and a second end pattern, the extension part is provided with a first width, the first end pattern comprises an outer widened part and an inner widened part, and the maximum widths of the outer widened part and the inner widened part are different from each other and are both larger than the first width of the extension part of the first pattern.
Description
Technical Field
The present invention relates to the field of semiconductor fabrication, and more particularly, to a semiconductor memory device formed by a multiple patterning (mult iple patterning) process and a method for forming the semiconductor memory device.
Background
In the semiconductor manufacturing process, it is necessary to form a fine pattern having a precise size in a proper substrate or material layer such as a semiconductor substrate/film layer, a dielectric material layer or a metal material layer by using a manufacturing process such as photolithography and etching. To achieve this, in the existing semiconductor technology, a mask layer is formed over a target material layer so that patterns are first formed in the mask layer to define these minute patterns, and then the patterns of the mask layer are transferred to the target material layer. In general, the mask layer is, for example, a patterned photoresist layer formed by a photolithography process, and/or a patterned mask layer formed using the patterned photoresist layer.
With the complexity of integrated circuits, the size of these micro patterns is continuously reduced, and the apparatus and patterning method for producing micro feature patterns must meet the strict requirements of manufacturing process resolution and overlay accuracy (overlay accuracy), while the single patterning (s ingle patterning) method cannot meet the requirements of manufacturing resolution or manufacturing process for manufacturing micro line width patterns. Therefore, how to improve the conventional process of these micro patterns is one of the important problems in the art.
Disclosure of Invention
The invention provides a semiconductor memory device and a method for forming the same, wherein a patterning process of a material layer is performed by a self-aligned multiple patterning (self-al igned multiple patterning, SAMP) process and different mask patterns to form material patterns which are mutually parallel and alternately arranged, two end points of each material pattern comprise asymmetric end patterns, one end pattern of each material pattern comprises at least two widened parts, and the reliability of interconnection between the end patterns of the material patterns and the extended parts can be improved by connecting at least two widened parts with the extended parts of the material patterns.
According to an embodiment of the present invention, a semiconductor memory device includes a substrate and a first pattern. The first pattern is arranged on the substrate and extends along a first direction, the first pattern comprises an extension part and two end points, the two end points respectively comprise a first end pattern and a second end pattern, the extension part has a first width, the first end pattern comprises an outer widening part and an inner widening part, and the maximum widths of the outer widening part and the inner widening part are different from each other and are both larger than the first width of the extension part of the first pattern.
According to an embodiment of the present invention, a method for forming a semiconductor device is provided, including providing a substrate; forming a material layer on the substrate, the material layer comprising opposite first and second sides, wherein the material layer comprises a plurality of protrusions on the first side; forming a plurality of strip masks on the material layer, wherein a partial area of one of the plurality of strip masks covers a partial area of one of the plurality of protruding parts; forming a mask layer on the plurality of strip-shaped masks, wherein the mask layer comprises an opening, the edge of the opening on the first side comprises a plurality of mask protruding parts, and each mask protruding part covers the partial area of the strip-shaped mask and the partial area of the protruding part; and etching the material layer by using the plurality of strip masks and the mask layer as etching masks.
The embodiment of the invention can form the characteristic patterns with relatively dense layout and relatively tiny size on the premise of simplifying the process, and can further improve the reliability of the electric connection between the formed characteristic patterns, such as the conducting wires and the contact pad patterns.
Drawings
Fig. 1 to 6 are schematic plan views illustrating stages of a method for forming a semiconductor device according to an embodiment of the invention.
Fig. 7 is a schematic plan view of a first pattern and a second pattern of a semiconductor memory device according to an embodiment of the present invention.
Fig. 8 is a partially enlarged plan view of a first pattern according to another embodiment of the present invention.
Fig. 9 is a partially enlarged plan view of a first pattern according to still another embodiment of the present invention.
Wherein reference numerals are as follows:
100. semiconductor device with a semiconductor device having a plurality of semiconductor chips
100A first zone
100B second region
101. Substrate and method for manufacturing the same
103. Material layer
103-1 main part
103-2 protrusion
103A first side
103B second side
105. First block pattern
107. Second block pattern
111. Strip-shaped mandrel
113. Strip mask
114. Annular mask
115. Mask layer
115P mask protrusion
116. An opening
116E edge
120. Pattern and method for producing the same
120A first side
120B second side
121. First pattern
121A extension
121B outside widening
121C inside widening
121C-1 partial region
121C-2 partial region
121D connecting part
121V end face
121P-1 first end pattern
121P-2 second end pattern
122. Second pattern
122A extension
122B outside widening part
122C inside widening portion
122P-1 third end pattern
122P-2 fourth end pattern
130. Conductive plug
W1 first width
W2 second width
W3 third width
W4 fourth width
W5 fifth width
Detailed Description
For a better understanding of the present invention, preferred embodiments will be described in detail hereinafter. The preferred embodiments of the present invention are illustrated in the accompanying drawings with elements labeled. Furthermore, technical features in different embodiments described below may be replaced, recombined or mixed with each other to constitute another embodiment without departing from the spirit of the invention.
Referring to fig. 1 to 6, schematic plan views of stages of a method for forming a semiconductor device according to an embodiment of the invention are shown. First, as shown in fig. 1, a substrate 101 is provided, and the substrate 101 is, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, or other semiconductor substrate. The substrate 101 may include a first region 100A, for example, an element region for setting a memory cell, and a second region 100B, for example, a peripheral region for setting a logic cell, but is not limited thereto. A material layer 103 is formed on the first region 100A of the substrate 101, the material layer 103 comprising a main portion 103-1 and a plurality of protrusions 103-2, wherein the main portion 103-1 comprises opposite first and second edges, the plurality of protrusions 103-2 are disposed on the first and second edges of the main portion 103-1, in other words, the material layer 103 comprises opposite first and second sides 103A, 103B, and the plurality of protrusions 103-2 comprised by the material layer 103 are located on the first and second sides 103A, 103B, wherein each of the plurality of protrusions 103-2 located on the first side 103A and each of the plurality of protrusions 103-2 located on the second side 103B do not coincide with each other in a first direction (e.g., x-direction as shown in fig. 1).
Further, a plurality of first block patterns 105 and second block patterns 107 are formed on the second region 100B of the substrate 101 in parallel with each other and extending along a first direction (for example, the x-direction shown in fig. 1), wherein the first block patterns 105 and the second block patterns 107 are alternately arranged with each other and are offset from each other in a second direction (for example, the y-direction shown in fig. 1), and the second direction is perpendicular to the first direction. In an embodiment, the material layer 103, the first block pattern 105 and the second block pattern 107 may be formed by the same photolithography process and include the same material, for example, but not limited to, a conductive material such as tungsten (W), aluminum (Al), or copper (Cu), or further include a dielectric material disposed under the conductive material, for example, silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN). In addition, in one embodiment, the material layer 103, the first block pattern 105 and the second block pattern 107 may be directly formed on the substrate 101, but the specific arrangement of the semiconductor device of the present invention is not limited thereto, and in another embodiment, other films or components, such as a dielectric layer (not shown), may be additionally disposed between the material layer 103 and the substrate 101 according to the actual device requirements. In addition, in order to protect the top surfaces of the material layer 103, the first block pattern 105, and the second block pattern 107, protective layers (not shown), such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), may be provided on the top surfaces, respectively, but not limited thereto. The protective layer may have the same profile as its corresponding underlying material layer 103, first block pattern 105 and second block pattern 107, and the protective layer may be removed at an appropriate point in time. The protective layer is not shown here in order to facilitate understanding of the present invention.
Next, referring to fig. 2, a plurality of bar-shaped mandrels (mandril) 111 are formed on the material layer 103, a partial area of one bar-shaped mandrel of the plurality of bar-shaped mandrels 111 covers a partial area of one protrusion of the plurality of protrusions 103-2, and the plurality of bar-shaped mandrels 111 also cover a main portion 103-1 of the material layer 103 located in the first region 100A. In addition, the plurality of strip-shaped mandrels 111 may also extend along a first direction (e.g., the x-direction shown in fig. 2) into the second zone 100B. In one embodiment, the plurality of bar-shaped mandrels 111 may be formed by photoresist, and the photoresist layer is coated on the material layer 103, and then the plurality of bar-shaped mandrels 111 are formed by photolithography. The stripe mandrels 111 may be formed by transferring a pattern in the photoresist layer to a layer under the photoresist layer.
Then, referring to fig. 3, spacers 113 are formed on the sidewalls of the respective bar mandrels 111, the material of the spacers 113 may be a mask material, such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), etc., by depositing a mask material layer on the material layer 103, covering the plurality of bar mandrels 111 and filling the gaps between the plurality of bar mandrels 111, and then removing the mask material covering the top surfaces of the plurality of bar mandrels 111 by an etching process, and removing a portion of the mask material between the plurality of bar mandrels 111, leaving the spacers 113 on the sidewalls of the respective bar mandrels 111, as shown in fig. 3, the spacers 113 surrounding the respective bar mandrels 111. According to the embodiment of the invention, the width of the spacers 113 is smaller than the width of the stripe mandrels 111, so that the dimension of the spacers 113 in one dimension may be the dimension of a sub-lithographic (sub-i-graphic).
Next, referring to fig. 4, the stripe mandrels 111 are removed, leaving spacers 113 on the material layer 103, and the spacers 113 may also be referred to as stripe masks 113 in the following description. In one embodiment, an etching process may be used to remove each of the strip mandrels 111. As shown in fig. 4, a partial area of one of the plurality of strip masks 113 covers a partial area of one of the plurality of protruding portions 103-2, and each protruding portion 103-2 is disposed corresponding to each strip mask 113, and two adjacent strip masks 113 constitute a part of the annular mask 114. In addition, a partial region of one of the two adjacent strip masks 113 of the annular mask 114 covers a partial region of one protrusion 103-2 located on the first side 103A, and a partial region of the other strip mask 113 of the annular mask 114 covers a partial region of the other protrusion 103-2 located on the second side 103B.
Then, referring to fig. 5, a mask layer 115 is formed on the plurality of stripe masks 113, and the mask layer 115 includes openings 116. As shown in fig. 5, the edge 116E of the opening 116 is spaced apart from the edge of the main portion 103-1 of the material layer 103, i.e., the edge of the main portion 103-1 is separated from the edge 116E of the opening 116. According to an embodiment of the present invention, the mask layer 115 further includes a plurality of mask protrusions 115P disposed on an edge 116E of the opening 116 on the first side 103A and an edge 116E of the opening on the second side 103B, and each mask protrusion 115P on the first side 103A and each mask protrusion 115P on the second side 103B do not overlap each other in the first direction (e.g., the x-direction shown in fig. 5). Further, each mask protrusion 115P covers a partial region of the stripe mask 113 and a partial region of the protrusion 103-2. According to an embodiment of the present invention, the top view area of each protrusion 103-2 is larger than the top view area of each mask protrusion 115P. In one embodiment, the mask layer 115 may be formed of photoresist, and the mask layer 115 is formed using a photolithography process, which includes an opening 116 and a plurality of mask protrusions 115P.
Thereafter, referring to fig. 5 and 6, the material layer 103 is etched using the plurality of stripe masks 113 and the mask layer 115 (including the openings 116 and the plurality of mask protrusions 115P) of fig. 5 as an etching mask, to form a plurality of patterns 120 of the semiconductor device 100 shown in fig. 6. In one embodiment, the semiconductor device 100 is a semiconductor memory device, as shown in fig. 6, the semiconductor memory device includes a substrate 101, a plurality of patterns 120 includes a plurality of first patterns 121 and a plurality of second patterns 122 disposed on the substrate 101, the plurality of first patterns 121 and the plurality of second patterns 122 each extend along a first direction (e.g., an x-direction shown in fig. 6), and the plurality of first patterns 121 and the plurality of second patterns 122 are alternately arranged along a second direction (e.g., a y-direction shown in fig. 6), the second direction being non-parallel to the first direction, for example, the second direction may be perpendicular to the first direction. Each of the first patterns 121 has a first end pattern 121P-1 at an end point located at the first side 120A of the pattern 120, each of the second patterns 122 has a fourth end pattern 122P-2 at an end point located at the second side 120B of the pattern 120, and the plurality of first end patterns 121P-1 and the plurality of fourth end patterns 122P-2 are arranged asymmetrically left and right, i.e., each of the first end patterns 121P-1 located at the first side 120A and each of the fourth end patterns 122P-2 located at the second side 120B do not coincide with each other in the first direction (e.g., x-direction shown in fig. 6). In the case where the top surfaces of the first pattern 121, the second pattern 122, the first block pattern 105, and the second block pattern 107 are provided with a protective layer (not shown), the protective layer may be further removed, and then a conductive plug (plug) 130 electrically connected to the first pattern 121, the second pattern 122, the first block pattern 105, and the second block pattern 107 may be formed.
In one embodiment, each of the first patterns 121 and each of the second patterns 122 of the semiconductor memory device are bit line patterns having conductive layers, and each of the conductive plugs 130 of the semiconductor memory device is disposed on each of the first end patterns 121P-1 and each of the fourth end patterns 122P-2. In addition, each conductive plug 130 is further disposed on each first block pattern 105 and each second block pattern 107 of the second region 100B.
Referring to fig. 7, a schematic plan view of a first pattern and a second pattern of a semiconductor memory device according to an embodiment of the invention is shown. As shown in fig. 7, the first pattern 121 includes an extension portion 121A and two end points including a first end pattern 121P-1 and a second end pattern 121P-2, respectively. The first end pattern 121P-1 includes an outer widened portion 121B and an inner widened portion 121C, and the first end pattern 121P-1 includes an end surface 121V perpendicular to a first direction (e.g., x-direction shown in fig. 7), the end surface 121V being located between the outer widened portion 121B and the inner widened portion 121C, and both the outer widened portion 121B and the inner widened portion 121C include curved surfaces. Further, according to the embodiment of the present invention, the top-view area of the outer widened portion 121B is larger than the top-view area of the inner widened portion 121C, and each conductive plug 130 overlaps the outer widened portion 121B. In one embodiment, the outside widening 121B directly contacts the inside widening 121C. In addition, the extension portion 121A has a maximum width, i.e., a first width W1. The outer widening 121B has a maximum width, i.e. the second width W2, and the inner widening 121C has a maximum width, i.e. the third width W3. According to an embodiment of the present invention, the second width W2 of the outer widening portion 121B and the third width W3 of the inner widening portion 121C are different from each other, and both the second width W2 and the third width W3 are larger than the first width W1 of the extension portion 121A. Further, the second width W2 of the outside widening portion 121B is larger than the third width W3 of the inside widening portion 121C.
Similarly, the second pattern 122 includes an extension 122A and two end points including a third end pattern 122P-1 on the first side 120A and a fourth end pattern 122P-2 on the second side 120B, respectively. As shown in fig. 7, the third end pattern 122P-1 of the second pattern 122 overlaps a partial region of the inner widened portion 121C of the first pattern 121 in a second direction (e.g., y-direction shown in fig. 7), which may also be referred to as an overlapping region, and the second direction is non-parallel to the first direction, e.g., the second direction may be perpendicular to the first direction. In addition, other partial regions of the inner widened portion 121C of the first pattern 121, that is, partial regions (which may also be referred to as non-overlapping regions) of the third end pattern 122P-1 that do not overlap the second pattern 122, may be disposed between the above-mentioned overlapping regions of the inner widened portion 121C and the outer widened portion 121B, and the other partial regions (non-overlapping regions) of the inner widened portion 121C may be separated from the third end pattern 122P-1 of the second pattern 122 in the first direction (e.g., x-direction shown in fig. 7).
As shown in fig. 7, in an embodiment, the fourth end pattern 122P-2 of the second pattern 122 on the second side 120B includes an outer widened portion 122B and an inner widened portion 122C, the top-view area of the outer widened portion 122B is larger than the top-view area of the inner widened portion 122C, and the maximum width of the outer widened portion 122B is larger than the maximum width of the inner widened portion 122C, and in an embodiment, the outer widened portion 122B directly contacts the inner widened portion 122C.
Referring to fig. 8, a partially enlarged plan view of a first pattern according to another embodiment of the invention is shown. The difference between the first pattern 121 of fig. 8 and the first pattern 121 of fig. 7 is that the partial region 121C-1 where the inner widening portion 121C directly contacts the outer widening portion 121B has a fixed width, i.e., the fourth width W4, and the partial region 121C-2 where the inner widening portion 121C directly contacts the extending portion 121A has a gradual width, and the width of the partial region 121C-2 gradually decreases from the fourth width W4 of the partial region 121C-1 to the first width W1 of the extending portion 121A in the direction from the outer widening portion 121B to the extending portion 121A.
Referring to fig. 9, a partially enlarged plan view of a first pattern according to still another embodiment of the invention is shown. The difference between the first pattern 121 of fig. 9 and the first pattern 121 of fig. 7 is that a connecting portion 121D is further disposed between the inner widened portion 121C and the outer widened portion 121B, the connecting portion 121D has a maximum width, i.e. a fifth width W5, and the fifth width W5 of the connecting portion 121D is greater than the first width W1 of the extending portion 121A. In an embodiment, the fifth width W5 of the connecting portion 121D may be smaller than the second width W2 of the outer widened portion 121B and also smaller than the third width W3 of the inner widened portion 121C. In another embodiment, the fifth width W5 of the connection portion 121D may be smaller than the second width W2 of the outer widened portion 121B and larger than the third width W3 of the inner widened portion 121C.
The structures illustrated in fig. 6 to 9 described above show only a part of the semiconductor device or the semiconductor memory device, and other components and structures may be included in the semiconductor device or the semiconductor memory device to realize the functions of the semiconductor device or the semiconductor memory device. For example, when the semiconductor device or the semiconductor memory device is a dynamic random access memory (dynamic random access memory, DRAM), the substrate 101 may further include a plurality of active regions (not shown) surrounded by an insulating structure (not shown), such as a shallow trench insulation (shallow trench isolation, STI), and disposed under the bit line patterns (composed of the first patterns 121 and the second patterns 122). Each active region may be electrically connected to a corresponding bit line pattern using a bit line plug (not shown). The substrate 101 may further include a plurality of word line patterns (not shown) therein, which may extend along the second direction y and pass through the corresponding active regions. The substrate 101 may also include a plurality of capacitive structures (not shown) above that may be electrically connected to one end of the active region in the substrate 101, respectively, to store charge from the bit line. It should be noted that the above dynamic random access memory is only one aspect of the present invention, and the semiconductor device or the semiconductor memory device may be any other semiconductor device or semiconductor memory device without departing from the concept of the present invention.
According to the embodiment of the invention, the patterning process of the material layer can be performed by using a self-aligned multiple patterning (SAMP) process and different mask patterns, so as to form a plurality of first patterns 121 and a plurality of second patterns 122 which are relatively dense in layout and relatively tiny in size, wherein the plurality of first patterns 121 and the plurality of second patterns 122 can be used as wires, such as bit lines of a semiconductor memory device, and asymmetric first end patterns 121P-1 and fourth end patterns 122P-2 are respectively formed at the first side 120A end point of each first pattern 121 and the second side 120B end point of each second pattern 122, each first end pattern 121P-1 and each fourth end pattern 122P-2 comprises an outer widening part and an inner widening part, and can be used as contact pads of the wires, wherein the outer widening part with larger top surface area and larger maximum width can be used for bearing the conductive plugs 130, thereby improving the reliability of the electrical connection between the conductive plugs and the contact pads, while the inner widening part can increase the reliability of the interconnection between the outer widening part and the extending part, and simultaneously the inner widening part can avoid the first end pattern 121P-1 and the second end pattern 122-1 to the contact pad. Therefore, the embodiment of the invention can form the wire and contact pad patterns with high reliability of electric connection, relatively dense layout and relatively tiny size on the premise of simplifying the process, thereby improving the yield of the semiconductor device.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (17)
1. A semiconductor memory device, comprising:
a substrate; and
a first pattern disposed over the substrate and extending along a first direction, the first pattern comprising an extension portion and two end points, the two end points comprising a first end pattern and a second end pattern, respectively, wherein the extension portion has a first width, the first end pattern comprises an outer widening portion and an inner widening portion, and a maximum width of the outer widening portion is greater than a maximum width of the inner widening portion; the outer widening part, the inner widening part and the extension part are sequentially arranged along the direction from the first end pattern to the second end pattern in the first direction, the outer widening part is in direct contact with the inner widening part or is connected with the inner widening part through a connecting part with the width smaller than the maximum width of the outer widening part, the width of the outer widening part gradually increases along the direction from the first end pattern to the second end pattern, and the width of the inner widening part close to the extension part gradually decreases to the width of the extension part along the direction from the first end pattern to the second end pattern; the first pattern is a conductive pattern.
2. The semiconductor memory device according to claim 1, wherein the first end pattern includes an end face perpendicular to the first direction.
3. The semiconductor memory device according to claim 1, further comprising a plurality of second patterns each extending along the first direction, wherein the plurality of second patterns and the plurality of first patterns are alternately arranged along a second direction, each of the second patterns includes an end located at a first side, the end of each of the second patterns overlaps a partial area of the inner widening portion in the second direction, and the second direction is non-parallel to the first direction.
4. The semiconductor memory device according to claim 3, wherein other partial regions of the inner widening section are provided between the partial regions of the inner widening section and the outer widening section, the other partial regions of the inner widening section being separated from the ends of the second pattern in the first direction.
5. The semiconductor memory device according to claim 3, wherein each of the second patterns includes another end disposed at the second side, the another end including an outer widened portion and an inner widened portion, a maximum width of the outer widened portion of the second pattern being larger than a maximum width of the inner widened portion of the second pattern.
6. The semiconductor memory device according to claim 1, wherein the outer widening portion and the inner widening portion comprise curved surfaces.
7. The semiconductor memory device according to claim 1, wherein a top-view area of the outer widened portion is larger than a top-view area of the inner widened portion.
8. The semiconductor memory device according to claim 3, wherein each of the first patterns and each of the second patterns is a bit line pattern having a conductive layer.
9. The semiconductor memory device according to claim 1, further comprising a plurality of conductive plugs, each of the conductive plugs overlapping the outer widening portion.
10. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a material layer on the substrate, the material layer comprising opposite first and second sides, wherein the material layer comprises a plurality of protrusions on the first side;
forming a plurality of strip masks on the material layer, wherein a partial area of one of the plurality of strip masks covers a partial area of one of the plurality of protruding parts;
forming a mask layer on the plurality of strip-shaped masks, wherein the mask layer comprises an opening, the edge of the opening on the first side comprises a plurality of mask protruding parts, and each mask protruding part covers the partial area of the strip-shaped mask and the partial area of the protruding part; and
etching the material layer by taking the plurality of strip masks and the mask layer as etching masks;
after etching the material layer, a plurality of patterns are formed in the material layer, the plurality of patterns including:
a plurality of first patterns each extending along a first direction, wherein each of the first patterns includes an extension portion and a tip end located at the first side, the tip end including an outer widening portion and an inner widening portion, the maximum widths of the outer widening portion and the inner widening portion being different from each other and each being greater than the width of the extension portion of the first pattern, the maximum width of the outer widening portion being greater than the maximum width of the inner widening portion;
the outer widening part, the inner widening part and the extension part are sequentially arranged along the first side to the second side in the first direction, the outer widening part is in direct contact with the inner widening part or is connected with the inner widening part through a connecting part with the width smaller than the maximum width of the outer widening part, the width of the outer widening part gradually increases along the first side to the second side, and the width of the inner widening part close to the extension part gradually decreases to the width of the extension part along the first side to the second side; the first pattern is a conductive pattern.
11. The method of claim 10, wherein each of the protruding portions is provided corresponding to each of the stripe masks.
12. The method of claim 10, wherein two adjacent strip masks form a portion of a ring mask.
13. The method of claim 10, wherein the material layer further comprises a main portion, the plurality of protruding portions are disposed at edges of the main portion, and the edges of the main portion are separated from the edges of the opening.
14. The method of claim 10, wherein a top-view area of each of the protruding portions is larger than a top-view area of each of the mask protruding portions.
15. The method according to claim 10, wherein before forming the plurality of stripe masks, the material layer further includes a plurality of protruding portions on the second side, and wherein each of the protruding portions on the second side and each of the plurality of protruding portions on the first side do not overlap with each other in the first direction.
16. The method according to claim 15, wherein an edge of the opening on the second side includes a plurality of mask protrusions before etching the material layer, and wherein each of the mask protrusions on the second side and each of the mask protrusions on the first side do not overlap with each other in the first direction.
17. The method of claim 10, wherein the plurality of patterns further comprises:
a plurality of second patterns each extending along a first direction, wherein the plurality of second patterns and the plurality of first patterns are alternately arranged along a second direction, each of the second patterns includes an end located at the first side, the ends of the second patterns overlap the inside widening in the second direction, and the second direction is non-parallel to the first direction.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110891793.0A CN113611702B (en) | 2021-08-04 | 2021-08-04 | Semiconductor memory device and method for forming semiconductor device |
| US17/513,907 US20230043973A1 (en) | 2021-08-04 | 2021-10-29 | Semiconductor memory device and method of forming semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110891793.0A CN113611702B (en) | 2021-08-04 | 2021-08-04 | Semiconductor memory device and method for forming semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113611702A CN113611702A (en) | 2021-11-05 |
| CN113611702B true CN113611702B (en) | 2023-07-18 |
Family
ID=78339472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110891793.0A Active CN113611702B (en) | 2021-08-04 | 2021-08-04 | Semiconductor memory device and method for forming semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113611702B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024779A (en) * | 2009-09-15 | 2011-04-20 | 三星电子株式会社 | Pattern structures in semiconductor devices and method for forming the same |
| CN107104043A (en) * | 2016-02-22 | 2017-08-29 | 爱思开海力士有限公司 | Pattern formation method and use its method, semi-conductor device manufacturing method |
| CN111640758A (en) * | 2020-06-11 | 2020-09-08 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
| CN215955280U (en) * | 2021-08-04 | 2022-03-04 | 福建省晋华集成电路有限公司 | Semiconductor memory device with a plurality of memory cells |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011061003A (en) * | 2009-09-10 | 2011-03-24 | Elpida Memory Inc | Method of forming wiring pattern, method of forming semiconductor device, semiconductor device, and data processing system |
| US9245844B2 (en) * | 2013-03-17 | 2016-01-26 | Nanya Technology Corporation | Pitch-halving integrated circuit process and integrated circuit structure made thereby |
| KR102257038B1 (en) * | 2014-06-23 | 2021-05-28 | 삼성전자주식회사 | Method for forming fine patterns of semiconductor devices, and method for forming semiconductor devices using the same, and semiconductor devices formed by using the same |
-
2021
- 2021-08-04 CN CN202110891793.0A patent/CN113611702B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024779A (en) * | 2009-09-15 | 2011-04-20 | 三星电子株式会社 | Pattern structures in semiconductor devices and method for forming the same |
| CN107104043A (en) * | 2016-02-22 | 2017-08-29 | 爱思开海力士有限公司 | Pattern formation method and use its method, semi-conductor device manufacturing method |
| CN111640758A (en) * | 2020-06-11 | 2020-09-08 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
| CN215955280U (en) * | 2021-08-04 | 2022-03-04 | 福建省晋华集成电路有限公司 | Semiconductor memory device with a plurality of memory cells |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113611702A (en) | 2021-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6486558B2 (en) | Semiconductor device having a dummy pattern | |
| CN108511440B (en) | Semiconductor structure with capacitance connecting pad and manufacturing method of capacitance connecting pad | |
| US8164119B2 (en) | Semiconductor device including conductive lines with fine line width and method of fabricating the same | |
| CN106941091B (en) | Interconnect structure, interconnect layout structure and method for fabricating the same | |
| US7767521B2 (en) | Cell region layout of semiconductor device and method of forming contact pad using the same | |
| US6228700B1 (en) | Method for manufacturing dynamic random access memory | |
| KR920005453B1 (en) | Making method of semiconductor contact holl | |
| CN215955280U (en) | Semiconductor memory device with a plurality of memory cells | |
| KR100439034B1 (en) | Bitline of semiconductor device with leakage current protection and method for forming the same | |
| US9165884B2 (en) | Method for fabricating a semiconductor device with formation of conductive lines | |
| CN113611702B (en) | Semiconductor memory device and method for forming semiconductor device | |
| US7429527B2 (en) | Method of manufacturing self-aligned contact openings | |
| KR102369509B1 (en) | Semiconductor device and method for fabricating the same | |
| US20230043973A1 (en) | Semiconductor memory device and method of forming semiconductor device | |
| KR100289661B1 (en) | Manufacturing method of semiconductor device | |
| US9349813B2 (en) | Method for fabricating semiconductor device | |
| CN109920761B (en) | Method for manufacturing semiconductor element | |
| US20220246625A1 (en) | Memory device and method for manufacturing the same | |
| US11289492B1 (en) | Semiconductor structure and method of manufacturing thereof | |
| CN112992790B (en) | Method for manufacturing semiconductor device structure | |
| CN117693195A (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| KR100267773B1 (en) | Method for fabricating semiconductor device | |
| KR100399934B1 (en) | Method for forming contact of semiconductor device | |
| KR101076813B1 (en) | Semiconductor Device and Method for Manufacturing the same | |
| KR100816245B1 (en) | Capacator and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |