CN115714552A - High-power frequency converter parallel control system and driving synchronization method - Google Patents
High-power frequency converter parallel control system and driving synchronization method Download PDFInfo
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- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
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- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
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- H02P29/02—Providing protection against overload without automatic interruption of supply
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- H02P29/028—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load the motor continuing operation despite the fault condition, e.g. eliminating, compensating for or remedying the fault
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- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
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- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
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- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/28—Arrangements for controlling current
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Abstract
The invention relates to a high-power frequency converter parallel control system and a driving synchronization method. Meanwhile, according to the structural characteristics of the parallel control system, the communication information establishing process, the communication fault tolerance and derating operation process and the driving signal synchronization process are realized. The system has the advantages of simple structure, convenient wiring, low overall cost, simple field debugging and capability of realizing communication establishment and automatic addressing. According to the invention, the state of the adjacent slave controllers is detected by the slave controllers, when the slave controllers have faults, the slave controllers are switched to the second transmission state, and the numerical value of the working counter is sent to the master controller, so that the positioning of communication fault equipment is realized, the automatic derating operation is realized, and the operation reliability of the system is improved.
Description
Technical Field
The invention belongs to the technical field of variable frequency speed regulation, and particularly relates to a high-power frequency converter parallel control system and a driving synchronization method.
Background
The frequency converter is an electric energy control device which converts a power frequency power supply into another frequency by utilizing the on and off of a power electronic device and mainly comprises a rectifying unit, a filtering unit, an inverting unit, a braking unit, a driving unit, a detecting unit, a micro-processing unit and the like. The frequency converter is widely applied to various fields of metallurgy, petroleum, chemical industry, textile, electric power, building materials, coal and the like.
In some application occasions, a high-power driving motor is required to be used and is matched with a frequency converter which needs high power to drive. The maximum capacity of the single frequency converter is limited by power electronic devices, heat dissipation technology and cost, so that the power cannot be too high. Therefore, a mode of realizing parallel connection of a plurality of frequency converters of the same type is often adopted, and the mode has the characteristics of high efficiency, flexible capacity configuration and convenient maintenance.
When the frequency converters work in parallel, the driving pulse signals in the power units of the frequency converters need to be triggered simultaneously, otherwise, circulation among devices is caused, power loss is caused if the frequency converters work in parallel, and equipment is damaged if the frequency converters work in parallel. As shown in fig. 1, a commonly used parallel control method for frequency converters is that a master device generates a given operation and distributes the given operation to parallel slave devices through a star topology communication method. The mode is convenient for positioning when communication faults occur, equipment without the communication faults can still operate in a derating mode, and the hardware design of the main equipment is complex and the wiring is complex along with the increase of the number of the parallel equipment. As shown in fig. 2, to solve the above problems, a ring communication mode may be adopted to send the operation given serial to the parallel converter devices, which is simpler in hardware design and more convenient in wiring compared to the parallel sending mode, but when the transmission signal line is damaged, the fault location cannot be performed, and the parallel converter devices need to be shut down as a whole. Meanwhile, serial transmission causes different signal transmission paths, increases signal transmission delay, causes inconsistency of trigger pulse signals among parallel devices, and cannot achieve a good circulating current suppression effect.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a high-power frequency converter parallel control system and a driving synchronization method, which can maintain the stable operation of a power grid, can quickly and accurately provide an optimal load transfer scheme, greatly improve the working efficiency of a dispatcher, and ensure the safe and stable operation of the power grid.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
a high-power frequency converter parallel control system comprises a main controller, a plurality of slave controllers and a plurality of power units, wherein the main controller is connected with the slave controllers through an optical fiber chain, each slave controller is connected with the corresponding power unit through a signal wire and used for controlling the corresponding power unit, and the power units are connected with a motor in parallel and used for driving the motor.
Furthermore, the master controller comprises a master controller first input interface and a master controller first output interface; the slave controller comprises a first input interface of the slave controller, a second input interface of the slave controller, a first output interface of the slave controller and a second output interface of the slave controller;
the first output interface of the master controller is connected with the first input interface of the first slave controller, the first input interface of the master controller is connected with the first output interface of the first slave controller, the first input interface of the front slave controller is connected with the first output interface of the rear slave controller, and the first output interface of the front slave controller is connected with the first input interface of the rear slave controller.
Moreover, the main controller adopts DSP and FPGA, the main controller is used for start-stop logic, process control and vector control,
the start-stop logic is used for switching and controlling the initialization state, the normal running state and the shutdown state of the parallel system;
the process control carries out fans, pumps, curling and lifting;
the vector control is used for rotating speed regulation, flux linkage and torque control, current regulation, flux linkage and torque observation and rotating coordinate transformation.
And the slave controller adopts an FPGA (field programmable gate array) and is used for collecting three-phase output current and bus voltage of the power unit, receiving given operation of the master controller and generating a PWM (pulse-width modulation) signal to drive the power unit.
And the slave controller comprises a communication processing unit and a transmission routing unit, the input end of the communication processing unit is connected with the first input interface of the slave controller and used for receiving communication data and outputting the communication data after processing, the output end of the communication processing unit is connected with the input end of the transmission routing unit, the output end of the transmission routing unit is respectively connected with the first output interface of the slave controller and the second output interface of the slave controller, and the input end of the transmission routing unit is connected with the second input interface of the slave controller and the output end of the communication processing unit.
A driving synchronization method of a high-power frequency converter parallel control system comprises a communication information establishing process, a communication fault tolerance and derating operation process and a driving signal synchronization process.
Moreover, the communication information establishing process includes the following steps:
step 1.1, the initial state of the slave controller transmission routing unit is kept in a first transmission state, the master controller sends information containing the number of slave controllers and a work counter, the number of the slave controllers is used for recording the total number of the slave controllers set by the master controller, the work counter is used for recording the number of the slave controllers which currently process the information, and the master controller initially sends out the work counter to be 0;
step 1.2, after receiving the information from the slave controller, the communication processing unit adds 1 to the working counter value and outputs the working counter value, stores the working counter value added with 1 as the address number of the slave controller, compares the total station number with the address number of the slave controller, and if the address number of the slave controller is less than the total station number, the transmission routing unit is kept in a first transmission state;
step 1.3, when the address number of the slave controllers is equal to the total station number, the slave controllers recognize that the slave controllers are tail-end slave controllers, the transmission routing unit is switched to a second transmission state, data are transmitted back to the front slave controllers, the data are not processed, and finally the data are transmitted back to the master station, at this moment, a communication link is established, and each slave controller completes automatic addressing;
and step 1.4, the master controller receives the returned information, the working counter is equal to the total number of the slave controllers, and the communication establishment is finished.
When the communication processing unit is in the first transmission state, the communication processing unit is connected with the first output interface of the slave controller and the first input interface of the slave controller, the second input interface of the slave controller is connected with the second output interface of the slave controller, when the communication processing unit is in the second transmission state, the communication processing unit is connected with the first input interface of the slave controller, the communication processing unit is connected with the second output interface of the slave controller, and the second input interface of the slave controller is connected with the first output interface of the slave controller.
Moreover, the communication fault tolerance and derating operation process comprises the following steps:
step 2.1, the master controller sends periodic communication information at regular time, the periodic communication information comprises a working counter, after the slave controller receives the periodic communication information, the communication processing unit adds 1 to the value of the working counter and outputs the result, and the address of the slave controller is not changed;
step 2.2, if a slave controller detects that the next slave controller adjacent to the slave controller has communication fault, the transmission routing unit is switched to a second transmission state, and the slave controller before the communication fault point still keeps communication;
2.3, the master controller receives the returned periodic communication information, reads the working counter, and learns the number of the slave controllers with normal communication and the communication fault occurrence point;
and 2.4, recalculating the operation set by the master controller according to the number of the slave controllers with normal communication, and performing integral derating operation on the parallel equipment.
Also, the driving signal synchronization process includes the steps of:
3.1, the main controller sends a timer value T1 in the main controller at the moment in a timing mode;
step 3.2, recording the local timer value T2 at the moment after receiving the local timer value from the controller, sending back an application command, and simultaneously recording the local timer value T3 at the moment;
and 3.3, after the main controller receives the response command, recording a timer value T4 of the main controller at the moment, transmitting the value back to the slave controller again, and removing redundant return time RTime from T4 to obtain correction time T4F:
T4F＝T4-RTime
and 3.4, calculating the clock deviation by the slave controller according to the received four numerical values:
deviation = [ (T4F-T3) - (T2-T1) ]/2
And the slave controller subtracts the clock deviation from the local timer value to realize the synchronization of the timers and further complete the synchronization of the driving signals.
The invention has the advantages and positive effects that:
1. according to the parallel control system, the master controller controls the plurality of slave controllers in parallel, each slave controller is connected with the corresponding driving unit, and the driving units are respectively connected with the motors, so that the parallel control system is formed. Meanwhile, according to the structural characteristics of the parallel control system, the communication information establishing process, the communication fault tolerance and derating operation process and the driving signal synchronization process are realized. The system has the advantages of simple structure, convenient wiring, low overall cost, capability of realizing communication establishment and automatic addressing, and simple field debugging.
2. According to the invention, the state of the adjacent slave controllers is detected by the slave controllers, when the slave controllers have faults, the slave controllers are switched to the second transmission state, and the numerical value of the working counter is sent to the master controller, so that the positioning of communication fault equipment is realized, the automatic derating operation is realized, and the operation reliability of the system is improved.
3. The invention synchronizes the timers of the master controller and the slave controller, so that the parallel driving signals can achieve very high synchronization effect, the synchronization error is less than 100ns, the circulation of the system is reduced, and the performance of the system is improved. This synchronization method is not affected by the device location and the length of the wiring.
Description of reference numerals:
11-a main controller, 111-a first output interface of the main controller, 112-a first input interface of the main controller, 12-a slave controller, 121-a first input interface of the slave controller, 122-a first output interface of the slave controller, 123 a second input interface of the slave controller, 124 a second output interface of the slave controller, 13-a power unit, 125 a communication processing unit and 126 a transmission routing unit.
Drawings
FIG. 1 is a schematic diagram of a star communication topology parallel control system;
FIG. 2 is a schematic diagram of a ring communication topology parallel control system;
FIG. 3 is a schematic diagram of a chain communication topology parallel control system constructed according to the present invention;
FIG. 4 is a view of the internal structure of the slave controller of the present invention;
FIG. 5 is a diagram illustrating a communication establishment procedure according to the present invention;
FIG. 6 is a schematic diagram of a communication fault tolerance and location process according to the present invention;
FIG. 7 is a flowchart of a clock synchronization method according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
A high-power frequency converter parallel control system is shown in fig. 3 and comprises a main controller 11, a plurality of sub-controllers 12 and a plurality of power units 13, wherein the main controller is connected with the plurality of sub-controllers through an optical fiber chain, each sub-controller is connected with the corresponding power unit through a signal wire, and the plurality of power units are connected with a motor in parallel. The main controller is responsible for motor control operation and control of the whole operation state of the system, the slave controllers are responsible for collecting voltage and current signals and generating PWM signals to drive the power unit, the main controller receives bus voltage, output three-phase current, working state and other data returned by the slave controllers through communication, and the data are processed through operation and logic to generate control set values and control commands and are sent to the slave controllers through communication.
The working process of the parallel system is as follows: the main controller receives three-phase output current sent by each slave controller, the main controller returns the current after averaging the current as vector control current, voltage setting is calculated through a vector control algorithm and sent to the slave controllers, and the slave controllers adopt a Sinusoidal Pulse Width Modulation (SPWM) method to compare the voltage setting with internal carrier waves and then generate PWM wave signals.
The master controller and the slave controllers respectively comprise a timer, the slave controllers use the timer to generate PWM carrier signals, the slave controllers are connected with the control set values generated by the master controller, IGBT driving signals are generated after the comparison between the set values and the PWM carrier signals, and the IGBT driving signals are sent to the corresponding power units.
The master controller comprises a master controller first input interface 112 and a master controller first output interface 111; the slave controller comprises a slave controller first input interface 121, a slave controller second input interface 123, a slave controller first output interface 122 and a slave controller second output interface 124; the first output interface of the main controller is connected with the first input interface of the first slave controller, the first input interface of the main controller is connected with the first output interface of the first slave controller, the first input interface of the front slave controller is connected with the first output interface of the rear slave controller, the first output interface of the front slave controller is connected with the first input interface of the rear slave controller, and the rest is done in sequence. The slave controller at the tail part only uses one pair of transceiving interfaces, wherein the first output interface and the second input interface have no external connection.
The main controller can be realized by using a Digital Signal Processor (DSP) and a programmable gate array (FPGA), and is used for starting and stopping logic, process control and vector control, wherein the starting and stopping logic is used for switching and controlling an initialization state, a normal operation state and a shutdown state of a parallel system; the process control carries out different process control requirements such as fans, pumps, curling, lifting and the like; the vector control is used for rotating speed regulation, flux linkage and torque control, current regulation, flux linkage and torque observation and rotating coordinate transformation.
The slave controller can be realized by using a programmable gate array (FPGA), is used for collecting three-phase output current and bus voltage of the power unit, and simultaneously receives given operation of the master controller to generate a PWM signal to drive the power unit.
As shown in fig. 4, the slave controller includes a communication processing unit 125 and a transmission routing unit 126, an input end of the communication processing unit is connected to the first input interface of the slave controller, the received communication data is processed and then output, and the communication data can be received and processed while being output for reducing communication delay.
The master controller and the slave controller are sequentially connected in series through a communication line, asynchronous serial communication is adopted for realizing, and the communication is divided into a physical layer and a protocol layer. The physical layer implements data recovery and serial-to-parallel conversion. The physical layer can be realized by using a special chip such as a PHY chip, and can also be realized by using FPGA development, the physical layer transmitter comprises a 4B/5B coding module, a scrambling module and a parallel-serial conversion module, and the physical layer receiver comprises a data recovery module, a serial-parallel conversion module, a descrambling module and a 4B/5B decoding module. The protocol layer is used for realizing the analysis of the communication protocol, the protocol layer can be realized by using the FPGA, the protocol layer of the main controller protects the communication processing unit and the synchronization unit, and the protocol layer of the slave controller comprises the communication processing unit, the automatic routing unit and the synchronization unit.
A driving synchronization method of a high-power frequency converter parallel control system comprises a communication information establishing process, a communication fault tolerance and derating operation process and a driving signal synchronization process.
The communication information establishing process comprises the following steps:
step 1.1, the initial state of the slave controller transmission routing unit is kept in the first transmission state, the master controller sends information containing the number of slave controllers and a work counter, the number of the slave controllers is used for recording the total number of the slave controllers set by the master controller, the work counter is used for recording the number of the slave controllers which process the information currently, and the master controller initially sends out the work counter to be 0.
And step 1.2, after receiving the information from the slave controller, the communication processing unit adds 1 to the working counter value and outputs the working counter value, stores the working counter value added with 1 as the address number of the slave controller, compares the total station number with the address number of the slave controller, and if the address number of the slave controller is less than the total station number, the transmission routing unit keeps in a first transmission state.
And 1.3, when the address number of the slave controllers is equal to the total station number, the slave controllers recognize that the slave controllers are tail-end slave controllers, the transmission routing unit is switched to a second transmission state, data are transmitted back to the front slave controllers, the data are not processed and are finally transmitted back to the master station, at the moment, a communication link is established, and each slave controller completes automatic addressing.
And step 1.4, the master controller receives the returned information, the working counter is equal to the total number of the slave controllers, and the communication establishment is finished.
As shown in fig. 5, the specific implementation method for establishing the communication information is as follows: in the communication initialization stage, the initial state of the slave controller transmission routing unit is kept in a first transmission state, the master controller sends a communication establishment frame, the communication establishment frame is shown in table 1 and comprises a frame header, a communication state, slave controller number segments, a working counter segment and a check code, wherein the frame header is used for identifying the communication frame, the communication state represents the current communication state of the master controller, the slave controller number is the total number of the parallel slave controllers set by the master controller, the working counter is used for recording the number of the slave controllers with current processed information, and the working counter is 0 when the master controller sends the communication establishment frame. The check code is used for checking the data frame, and a CRC (cyclic redundancy check) checking mode can be adopted.
Table 1 communication establishment frame
| Frame header | Communication status | Number of slave controllers | Work counter | Check code |
And after receiving the communication establishment frame from the slave controller, the communication processing unit adds 1 to the working counter value and outputs the working counter value, stores the working counter value added with 1 as the address number of the slave controller, compares the total station number with the address number of the slave controller, and if the address number of the slave controller is less than the total station number, the transmission routing unit keeps in a first transmission state. When the communication establishment frame is transmitted to the tail-end slave controllers, the address numbers of the slave controllers are equal to the total station number, the transmission routing unit is switched to a second transmission state, at the moment, the communication link is established, each slave controller finishes automatic addressing, the master controller receives the returned communication establishment frame, the working counter is equal to the total slave controller number, and the communication initialization stage is finished.
The communication fault tolerance and derating operation process comprises the following steps:
and 2.1, the master controller sends periodic communication information at regular time, the periodic communication information comprises a working counter, and after the slave controller receives the periodic communication information, the communication processing unit adds 1 to the value of the working counter and outputs the result, without changing the address of the slave controller.
And 2.2, if a certain slave controller detects that the next slave controller adjacent to the certain slave controller has communication fault, the transmission routing unit is switched to a second transmission state, and the slave controller before the communication fault point still keeps communication.
And 2.3, the master controller receives the returned periodic communication information, reads the working counter, and learns the number of the slave controllers with normal communication and the communication fault occurrence point.
And 2.4, recalculating the operation setting by the master controller according to the number of the slave controllers with normal communication, so that the parallel equipment is operated in a derating mode integrally.
The specific implementation method of communication fault tolerance and derating operation comprises the following steps: after the communication initialization stage is finished, the master controller sends periodic communication frames in a fixed period, the periodic communication frames are shown in table 2 and comprise working counter sections, and after the slave controller receives periodic communication information, the communication processing unit adds 1 to the working counter value and outputs the working counter value, so that the address of the slave controller is not changed. And each slave controller establishes a timer, and the timer is cleared when a periodic communication frame is received. As shown in fig. 6, when the timer exceeds the communication cycle time, the communication before the slave controller is proved to be faulty, the slave controller drive output is blocked, and the second output interface of the slave controller is closed. When the former slave controller detects that the second input interface has no data reception, the transmission routing unit is switched to the second transmission state, and the slave controller before the communication fault point can still keep communication.
TABLE 2 periodic communication frame
| Frame header | Voltage setting | Control command | Work counter | Check code |
The master controller receives the returned periodic communication frame, reads the working counter, and can know the number of the slave controllers with normal communication and the occurrence point of communication faults. The main controller can recalculate the operation setting according to the number of the sub-controllers with normal communication, so that the parallel equipment is wholly derated to operate, and the specific derated operation mode needs to be specifically defined according to the application scene.
When the communication processing unit is in a first transmission state, the communication processing unit is connected with the first output interface of the slave controller and the first input interface of the slave controller, and the second input interface of the slave controller is connected with the second output interface of the slave controller. This state serves as the slave controller state in the middle of the communication link.
When the communication processing unit is in the second transmission state, the communication processing unit is connected with the first input interface of the slave controller, the communication processing unit is connected with the second output interface of the slave controller, and the second input interface of the slave controller is connected with the first output interface of the slave controller. And the internal connection is not carried out, and the state is used as the state of the slave controller at the tail end of the communication link.
The driving signal synchronization process includes the steps of:
and 3.1, the main controller sends a timer value T1 in the main controller at the moment in a timing mode.
And 3.2, recording the local timer value T2 at the moment after receiving the command from the controller, sending the command back to the controller, and simultaneously recording the local timer value T3 at the moment.
And 3.3, after the main controller receives the response command, recording a timer value T4 of the main controller at the moment, transmitting the value back to the slave controller again, and removing redundant return time RTime from T4 to obtain correction time T4F:
T4F＝T4-RTime。
and 3.4, calculating the clock deviation by the slave controller according to the received four numerical values:
deviation = [ (T4F-T3) - (T2-T1) ]/2
And the slave controller subtracts the clock deviation from the local timer value to realize the synchronization of the timers and further complete the synchronization of the driving signals.
As shown in fig. 7, a specific implementation method of the driving signal synchronization process is as follows: the slave controller comprises a timer and is used for generating PWM carrier signals, the slave controller generates IGBT driving signals after being compared with the PWM carrier signals sent by the master controller, and the IGBT driving signals are sent to the corresponding power units. If the slave controllers' timers are synchronized and given the same, synchronization of the drive signals can be guaranteed.
The master controller includes a timer that synchronizes the slave controller timers with the master controller timer through a synchronization process. The synchronization process is specifically as follows: the main controller sends a synchronous command at fixed time, and sends the time value (marked as T1) of the periodic timer of the main controller together with the synchronous command; after receiving the synchronous command, the power unit saves the value T1 and saves the value (marked as T2) of the period timer of the power unit at the moment; the power unit returns a delay request command and sends the time value (marked as T3) of the power unit period timer along with the delay request command; after receiving the delay request command, the main controller records the time value (marked as T4) of the periodic timer of the main controller, sends a delay feedback command and sends the T4 value along with the command; the slave controller needs to record the time RTime of returning data from the output interface 1 to the input interface 2; and after receiving the delay feedback command from the controller, calculating the deviation between the power unit cycle clock and the master controller cycle timer by using calculation formulas (1) and (2), and subtracting the deviation from the power unit cycle timer to finish synchronization.
T4F＝T4-RTime (1)
Deviation = [ (T4F-T3) - (T2-T1) ]/2 (2)
By adopting the synchronization method, the influence of communication delay difference caused by different communication wiring lengths between the master controller and the slave controllers can be eliminated, and the flexibility of field equipment arrangement is improved. The parallel driving signals can achieve a very high synchronization effect, and experiments prove that the synchronization error is less than 100ns, the system circulation is reduced, and the parallel system performance is improved.
It should be emphasized that the embodiments described herein are illustrative rather than restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but also includes other embodiments that can be derived from the technical solutions of the present invention by those skilled in the art.
Claims (10)
1. The utility model provides a high-power converter parallel control system, connects in parallel on the converter which characterized in that: the power unit comprises a main controller, a plurality of slave controllers and a plurality of power units, wherein the main controller is connected with the plurality of slave controllers through an optical fiber chain, each slave controller is connected with the corresponding power unit through a signal wire and used for controlling the corresponding power unit, and the plurality of power units are connected with a motor in parallel and used for driving the motor.
2. The parallel control system of high-power frequency converters according to claim 1, characterized in that: the main controller comprises a main controller first input interface and a main controller first output interface; the slave controller comprises a first input interface of the slave controller, a second input interface of the slave controller, a first output interface of the slave controller and a second output interface of the slave controller;
the first output interface of the main controller is connected with the first input interface of the first slave controller, the first input interface of the main controller is connected with the first output interface of the first slave controller, the first input interface of the front slave controller is connected with the first output interface of the rear slave controller, and the first output interface of the front slave controller is connected with the first input interface of the rear slave controller.
3. The parallel control system of high-power frequency converters according to claim 1, characterized in that: the main controller adopts DSP and FPGA, the main controller is used for start-stop logic, process control and vector control,
the start-stop logic is used for switching and controlling the initialization state, the normal running state and the shutdown state of the parallel system;
the process control carries out fans, pumps, curling and lifting;
the vector control is used for rotating speed regulation, flux linkage and torque control, current regulation, flux linkage and torque observation and rotating coordinate transformation.
4. The parallel control system of high-power frequency converters according to claim 1, characterized in that: the slave controller adopts an FPGA (field programmable gate array) and is used for collecting three-phase output current and bus voltage of the power unit, receiving given operation of the master controller and generating a PWM (pulse-width modulation) signal to drive the power unit.
5. The parallel control system of high-power frequency converters according to claim 2, characterized in that: the slave controller comprises a communication processing unit and a transmission routing unit, the input end of the communication processing unit is connected with a first input interface of the slave controller and used for receiving communication data and outputting the communication data after processing, the output end of the communication processing unit is connected with the input end of the transmission routing unit, the output end of the transmission routing unit is respectively connected with a first output interface of the slave controller and a second output interface of the slave controller, and the input end of the transmission routing unit is connected with the second input interface of the slave controller and the output end of the communication processing unit.
6. A driving synchronization method of a high power frequency converter parallel control system according to any one of claims 1 to 5, characterized in that: the method comprises a communication information establishing process, a communication fault tolerance and derating operation process and a driving signal synchronization process.
7. The driving synchronization method of the parallel control system of the high-power frequency converter according to claim 6, characterized in that: the communication information establishing process comprises the following steps:
step 1.1, the initial state of the slave controller transmission routing unit is kept in a first transmission state, the master controller sends information containing the number of slave controllers and a work counter, the number of the slave controllers is used for recording the total number of the slave controllers set by the master controller, the work counter is used for recording the number of the slave controllers which currently process the information, and the master controller initially sends out the work counter to be 0;
step 1.2, after receiving the information from the controller, the communication processing unit adds 1 to the working counter value and outputs the working counter value, stores the working counter added with 1 as the address number of the controller, compares the total station number with the address number of the controller, and if the address number of the controller is less than the total station number, the transmission routing unit keeps in a first transmission state;
step 1.3, when the address number of the slave controllers is equal to the total station number, the slave controllers recognize that the slave controllers are tail-end slave controllers, the transmission routing unit is switched to a second transmission state, data are transmitted back to the front slave controllers, the data are not processed, and finally the data are transmitted back to the master station, at this moment, a communication link is established, and each slave controller completes automatic addressing;
and step 1.4, the master controller receives the returned information, the working counter is equal to the total number of the slave controllers, and the communication establishment is finished.
8. The driving synchronization method of the parallel control system of the high-power frequency converter according to claim 7, characterized in that: when the communication processing unit is in a first transmission state, the communication processing unit is connected with a first output interface of the slave controller and a first input interface of the slave controller, a second input interface of the slave controller is connected with a second output interface of the slave controller, when the communication processing unit is in a second transmission state, the communication processing unit is connected with the first input interface of the slave controller, the communication processing unit is connected with the second output interface of the slave controller, and the second input interface of the slave controller is connected with the first output interface of the slave controller.
9. The driving synchronization method of the parallel control system of the high-power frequency converter according to claim 6, characterized in that: the communication fault tolerance and derating operation process comprises the following steps:
step 2.1, the master controller sends periodic communication information at regular time, the periodic communication information comprises a working counter, after the slave controller receives the periodic communication information, the communication processing unit adds 1 to the value of the working counter and outputs the result, and the address of the slave controller is not changed;
step 2.2, if a slave controller detects that the next slave controller adjacent to the slave controller has communication fault, the transmission routing unit is switched to a second transmission state, and the slave controller before the communication fault point still keeps communication;
2.3, the master controller receives the returned periodic communication information, reads the working counter, and learns the number of the slave controllers with normal communication and the communication fault occurrence point;
and 2.4, recalculating the operation setting by the master controller according to the number of the slave controllers with normal communication, so that the parallel equipment is operated in a derating mode integrally.
10. The driving synchronization method of the parallel control system of the high-power frequency converter according to claim 6, characterized in that: the driving signal synchronization process includes the steps of:
3.1, the main controller sends a timer value T1 in the main controller at the moment in a timing mode;
3.2, recording the local timer value T2 after receiving the command from the controller, sending the command back, and recording the local timer value T3 at the moment;
and 3.3, after the main controller receives the response command, recording a timer value T4 of the main controller at the moment, transmitting the value back to the slave controller again, and removing redundant return time RTime from T4 to obtain correction time T4F:
T4F＝T4-RTime
and 3.4, calculating the clock deviation by the slave controller according to the received four numerical values:
deviation = [ (T4F-T3) - (T2-T1) ]/2
And the slave controller subtracts the clock deviation from the local timer value to realize the synchronization of the timers and further complete the synchronization of the driving signals.
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| CN202211457840.1A CN115714552A (en) | 2022-11-21 | 2022-11-21 | High-power frequency converter parallel control system and driving synchronization method |
| PCT/CN2022/141794 WO2024108720A1 (en) | 2022-11-21 | 2022-12-26 | Parallel control system for high-power frequency converters, and driving synchronization method |
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| CN202211457840.1A CN115714552A (en) | 2022-11-21 | 2022-11-21 | High-power frequency converter parallel control system and driving synchronization method |
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| US4449247A (en) * | 1980-07-30 | 1984-05-15 | Harris Corporation | Local orderwire facility for fiber optic communication system |
| CN203398982U (en) * | 2013-04-26 | 2014-01-15 | 武汉港迪电气有限公司 | A combining device for low-voltage large-power frequency converters |
| CN104977859B (en) * | 2014-04-04 | 2018-10-26 | 伊顿公司 | A kind of frequency converter parallel control system and its fault tolerant control method |
| CN106209541B (en) * | 2016-07-04 | 2019-09-20 | 南京埃斯顿自动化股份有限公司 | A kind of means of communication of parallel drive system |
| CN106100507A (en) * | 2016-07-04 | 2016-11-09 | 南京埃斯顿自动控制技术有限公司 | A kind of modular parallel drive system and control method thereof |
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