CN111817592B - High-power inverter parallel system based on SPI communication, synchronization method and online switching method - Google Patents
High-power inverter parallel system based on SPI communication, synchronization method and online switching method Download PDFInfo
- Publication number
- CN111817592B CN111817592B CN202010496448.2A CN202010496448A CN111817592B CN 111817592 B CN111817592 B CN 111817592B CN 202010496448 A CN202010496448 A CN 202010496448A CN 111817592 B CN111817592 B CN 111817592B
- Authority
- CN
- China
- Prior art keywords
- control unit
- inverter
- pwm pulse
- signal
- pwm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/325—Means for protecting converters other than automatic disconnection with means for allowing continuous operation despite a fault, i.e. fault tolerant converters
Abstract
The invention discloses a high-power inverter parallel system based on SPI communication, which comprises an upper computer and N parallel inverters, wherein each inverter comprises a control unit and a main circuit unit; the upper computer is connected with the control unit of each inverter through a standard RS422 communication line, a PWM pulse signal input interface of the main circuit unit is connected with a PWM pulse signal output interface of the control unit, the control units of the parallel inverters are connected in pairs through SPI communication, and each group of logic signal interfaces of the control unit of the parallel inverter is connected with a logic signal interface of the other inverter control unit. The PWM pulse information and the pulse switching of the parallel inverter are controlled by a host, the host can realize the high-precision synchronization of the parallel inverter only through proper time delay compensation, and the synchronization precision can reach ns level; the synchronization method is easy to realize, and the reliability of the system is greatly improved.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a high-power inverter parallel system based on SPI communication, a synchronization method and an online switching method.
Background
The high-power inverter parallel system has wide application in the fields of high-speed trains, automobile acceleration crash tests and the like, a plurality of inverters are generally required to be connected in parallel for improving the redundancy and the output power of the system, and when one inverter breaks down, other inverters can normally run to continuously provide electric energy for the system. The key of the parallel connection of the inverters is that all the inverters must run synchronously, otherwise, large circulation currents are generated among the inverters, the output power of a system is reduced, the loss of the system is increased, and the circulation currents can also enable part of the inverters to bear overlarge current stress, so that equipment is damaged in severe cases.
With the development of power electronic technology, many documents have researched the synchronization scheme of the parallel inverter, and in terms of hardware, the circulating current of the inverter can be suppressed by connecting an inductor in series with an output interface of the inverter, but the inductor has a large volume and high cost, and the loss and voltage drop of a system line can be increased. The droop algorithm based on the voltage frequency external characteristic can also realize the synchronous control of the inverter, and is characterized by simple installation and maintenance and convenient expansion, but for high-power application occasions, the inverter frequency and power change rapidly, and generally no steady-state working point exists, so that the active power and the reactive power cannot be separated to introduce the droop algorithm. There is also a document to reduce the circulating current of the parallel inverter by a carrier synchronization method, but under some limit conditions of the high-power parallel inverter, the instantaneous current may exceed the limit range of the device, which requires the synchronization precision of the inverter to be controlled within us level, and the existing carrier synchronization method is difficult to meet the high-precision synchronization requirement. On the other hand, in consideration of the redundancy of the system, when a single inverter fails, the system should continue to operate, and the existing synchronization method is difficult to realize smooth switching of the parallel inverter master and slave machines.
Disclosure of Invention
The invention aims to solve the problems of synchronous control and system redundancy operation of a high-power parallel inverter, and provides a high-power inverter parallel system, a synchronization method and an online switching method based on SPI communication, so that high-precision synchronization of parallel inverters is realized, and the system can run uninterruptedly when a single inverter fails.
In order to achieve the purpose, the high-power inverter parallel system based on SPI communication comprises an upper computer and N parallel inverters, wherein the N inverters comprise a host and N-1 slave machines, each inverter has a unique and fixed serial number, and each inverter comprises a control unit and a main circuit unit; the upper computer is connected with the control unit of each inverter through a standard RS422 communication line, a PWM pulse signal input interface of a main circuit unit of each inverter is connected with a PWM pulse signal output interface of the control unit, the control units of the parallel inverters are connected in pairs through SPI communication, and each group of logic signal interfaces of the parallel inverter control units are connected with a logic signal interface of another inverter control unit.
Further, each group of the logic signal interfaces includes six binary logic signal interfaces, wherein three of the binary logic signal interfaces are output interfaces and are used for outputting three logic signals: a PWM enabling output signal PwmEnOut _ x, a PWM pulse loading output signal PwmStrobeOut _ x, and an inverter fault output signal FaultOut _ x; the other three paths are input interfaces and are used for receiving three logic signals: the PWM control circuit comprises a PWM enabling input signal PwmEnIn _ x, a PWM pulse loading input signal PwmStrobeIn _ x and an inverter fault input signal FaultIn _ x, wherein x is a serial number of a logic signal and ranges from 1 to N-1.
The high-power inverter parallel system synchronization method based on SPI communication is also provided as follows:
step 1: in each modulation wave period, the upper computer sends a data frame to all the inverter control units through the RS422 communication line, and the data frame comprises a voltage instruction and a PWM pulse enabling instruction; the inverter control unit sends the state data of the inverter control unit to the upper computer every time the upper computer sends a data frame;
step 2: after all the inverter control units receive the data frame of the upper computer, caching the PWM pulse enabling instruction and the voltage instruction; the control units of all the inverters execute a modulation algorithm according to the voltage command, generate PWM (pulse-width modulation) waves and PWM pulse signals and cache the PWM waves and the PWM pulse signals; the master control unit sends the generated PWM pulse signal to the slave control unit through SPI communication, the slave control unit sends a response message to the master control unit each time the slave control unit receives the PWM pulse message sent by the master control unit, the slave control unit caches the PWM pulse signal after receiving the PWM pulse signal, and the PWM pulse signal generated by the slave control unit is covered at the moment;
the master control unit detects a PWM pulse enabling instruction, if the PWM pulse enabling instruction is 0, the system is in standby, at the moment, the master control unit sets all PwmEnOut _ x signals to be 0 and sends the PwmEnOut _ x signals to the slave control unit, and if the PWM pulse enabling instruction is 1, the inverter starts to work, the master control unit sets the PwmEnOut _ x signals to be 1 and sends the PwmEnOut _ x signals to the slave control unit;
and step 3: the host control unit compares the PWM modulation wave with the PWM carrier in real time, and when the size relation between the PWM modulation wave and the PWM carrier changes, the host control unit immediately inverts a logic signal PwmStrobeOut _ x;
meanwhile, if the PWM pulse enable instruction is 1, the host control unit loads the cached PWM pulse signal after time delay and sends the PWM pulse signal to the main circuit unit; if the PWM pulse enable instruction is 0, the system keeps a standby state;
and 4, step 4: the slave control unit detects a PwmEnIn _ x signal interface and a PwmStrobeIn _ x signal interface which are connected with the master control unit in real time;
when the PwmEnIn _ x signal sent by the master control unit is 0, the slave keeps a standby state; when the PwmEnIn _ x signal sent by the host control unit is 1, the inverter starts to work; when the PwmStrobeIn _ x signal transmitted by the host changes, the slave control unit immediately loads the buffered PWM pulse signal and sends the PWM pulse signal to the master circuit unit.
Further, in step 1, the state data includes a serial number of the inverter, a current working state, detailed fault information, and an identity of the master/slave device.
The online switching method of the high-power inverter parallel system based on the SPI communication is also provided as follows:
step 1: after the master control unit sends the PWM pulse signal, the response information of the slave control unit is detected; if no response information is detected, the master control unit sends the PWM pulse signal to the slave control unit again for K times, and if the slave control unit does not respond, the slave control unit is offline;
the method comprises the following steps that a host control unit sets a PwmEnOut _ x signal and a PwmStobeOut _ x signal sent to an offline slave to be 0, so that the offline slave exits a parallel system, meanwhile, the host control unit sends a queue updating instruction to all slave control units, and the slave control unit sets a fault flag bit of the offline slave in a queue to be 1 after receiving the queue updating instruction;
step 2: if a faultIn _ x signal received by the host control unit is 1, indicating that a corresponding slave machine has a fault, setting a PwmEnOut _ x signal and a PwmStrobeOut _ x signal which are sent to the fault slave machine to be 0 by the host control unit, and enabling the fault slave machine to exit the parallel system; meanwhile, the master control unit sends a queue updating instruction to all the slave control units, and after receiving the queue updating instruction, the slave control units set the fault flag bit of the fault slave in the queue to be 1;
and step 3: if the master machine has a fault but is not offline, the master machine control unit selects the slave machine which is closest to the head of the queue and has a fault zone bit of 0 from the queue as a new master machine, and then sends a master machine updating instruction to all the slave machine control units; the selected slave control unit automatically becomes a master after receiving the master updating instruction and starts to send PWM pulse information to the rest slaves, and the rest slave control units start to receive the PWM pulse information of a new master after receiving the master updating instruction and send response information; meanwhile, all inverter control units update the fault flag bit of the original fault host to 1, and the new host sets the PwmEnOut _ x signal and the PemStrobeOut _ x which are sent to the original fault host to 0, so that the fault inverter exits from the parallel system, and a new master-slave relationship is established;
and 4, step 4: all slave control units detect PWM pulse information sent by the host, if the PWM pulse information is detected, the host works normally, otherwise, the host is offline, and the slave sends host offline information to all inverters;
and 5: after the inverter control units receive the host offline information, all the inverter control units without faults send self health information to other inverter control units, and the fault inverters do not send self health information; after all the inverter control units receive the health information, an inverter information queue is established again according to the ascending sequence of the inverter serial numbers, all the inverters in the queue are fault-free and online inverters, and the health information received by the inverter control units is the same, so the reestablished queue is also the same;
after the queue is established, the inverter at the head of the queue automatically becomes a new host, the new host control unit firstly sends a host updating instruction to the slave control units in all the queues, all the slave control units start to receive PWM pulse information of the host and reply response information after receiving the host updating instruction, the new master-slave relationship is established, and the host control unit sets signals PwmEnOut _ x and PwmStrobe _ x which are sent to the inverters which are not in the queues to be 0 so that the inverters exit a parallel system.
Further, in step 5, the health information includes an inverter serial number and a fault flag.
Compared with the prior art, the invention has the following advantages:
1. according to the high-power inverter parallel system and the synchronization method based on SPI communication, PWM pulse information and pulse switching of the parallel inverter are controlled by the host, the host can realize high-precision synchronization of the parallel inverter only through proper time delay compensation, and the synchronization precision can reach ns level; the synchronization method is easy to realize, and the reliability of the system is greatly improved;
2. the invention also provides an online switching method of the master and the slave machines, when part of inverters have faults, the smooth switching between the master machine and the slave machines can be realized, the continuous operation of the system is ensured, and the reliability of the system is further improved; the switching of the fault is only completed by the control unit of the inverter, and the upper computer does not refer to the reconstruction of the master and the slave, so the method is easier to realize in terms of procedure and has good adaptability.
Drawings
FIG. 1 is a block diagram of a high-power inverter parallel system based on SPI communication according to the present invention;
FIG. 2 is a diagram of a topology of the main circuit unit of FIG. 1;
FIG. 3 is a flow chart of the synchronization method of FIG. 1;
fig. 4 is a flow chart of online switching between master and slave devices in fig. 1.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments.
As shown in fig. 1, the SPI communication-based high-power inverter parallel system includes an upper computer and N inverters connected in parallel, where the N inverters include a host and N-1 slaves, and each inverter has a unique and fixed serial number. Each inverter comprises a control unit and a main circuit unit, wherein the topological structure of the main circuit unit of the inverter is not limited herein, for example, the commonly used topological structure comprises a two-level topological structure, a clamp diode three-level topological structure or a polar H-bridge topological structure; as shown in fig. 2, the clamp diode three-level topology, the main circuit unit includes two supporting capacitors C1 and C2, four clamp diodes AD1, AD2, BD1, BD2, eight power devices AT1, AT2, AT3, AT4, BT1, BT2, BT3, BT 4; one end of a supporting capacitor C1 is a direct current input port anode, the other end of the supporting capacitor C1 is connected with a supporting capacitor C2, one end of a supporting capacitor C2 is connected with the supporting capacitor C1, the other end of the supporting capacitor C2 is a cathode of the direct current input port, power devices AT1, AT2, AT3 and AT4 are sequentially connected in series in an emitter-collector connection mode, a collector of the power device AT1 is connected with the direct current input port anode, an emitter of the power device AT4 is connected with the direct current input port cathode, and a cathode of a diode clamp AD1 is connected with a connection point of the power devices AT1 and AT 2; an anode of the clamp diode AD1 is connected with a cathode of the clamp diode AD2, an anode of the clamp diode AD2 is connected with a connection point of power devices AT3 and AT4, a connection point of the clamp diodes AD1 and AD2 is connected with a connection point of support capacitors C1 and C2, the power devices BT1, BT2, BT3 and BT4 are connected in series in an emitter-collector connection manner, a collector of the power device BT4 is connected with a positive electrode of a direct current input port, an emitter of the power device BT4 is connected with a negative electrode of the direct current input port, a cathode of the clamp diode BD 4 is connected with a connection point of the power devices BT4 and BT4, an anode of the clamp diode BD 4 is connected with a cathode of the clamp diode BD 4, an anode of the clamp diode BD 4 is connected with a connection point of the power devices BT4 and BT4, a connection point of the clamp diodes BD 4 and BD 4 is connected with a connection point of the support capacitors C4 and the ac output port, and a connection point of the power device AT4 is an ac output port. The connection point of the power devices BT2 and BT3 is the negative electrode of an alternating current output port.
As shown in fig. 1 again, the upper computer includes N sets of standard RS422 communication interfaces; the main circuit unit of the inverter comprises a PWM pulse signal input interface; the control unit of the inverter comprises a PWM pulse signal output interface, a group of standard RS422 communication interfaces, an N-1 group of standard SPI communication interfaces and an N-1 group of logic signal interfaces, wherein each group of logic signal interfaces comprises six binary logic signal interfaces, three of the six binary logic signal interfaces are output interfaces, and the function of the three binary logic signal interfaces is to output three logic signals: a PWM enabling output signal PwmEnOut _ x, a PWM pulse loading output signal PwmStrobeOut _ x, and an inverter fault output signal FaultOut _ x; the other three paths are input interfaces and are used for receiving three logic signals: the PWM control circuit comprises a PWM enabling input signal PwmEnIn _ x, a PWM pulse loading input signal PwmStrobeIn _ x and an inverter fault input signal FaultIn _ x, wherein x is a serial number of a logic signal and ranges from 1 to N-1.
The upper computer is connected with the control unit of each inverter through a standard RS422 communication line, a PWM pulse signal input interface of a main circuit unit of each inverter is connected with a PWM pulse signal output interface of the control unit, the control units of the parallel inverters are connected in pairs through SPI communication, and each group of logic signal interfaces of the control units of the parallel inverters are connected with a logic signal interface of another inverter control unit. For example, the pwmenouti _1 signal interface, PwmStrobeOut _1 signal interface, and FaultOut _1 signal interface of the first inverter are connected to the PwmEnIn _1 signal interface, pwmstrobeiin _1 signal interface, and FaultIn _1 signal interface of the second inverter, respectively, and correspondingly, the PwmEnIn _1 signal interface, pwmstrobeiin _1 signal interface, and FaultIn _1 signal interface of the first inverter are connected to the pwmenouti _1 signal interface, pwmstrobeiut _1 signal interface, and FaultOut _1 signal interface, respectively, of the second inverter.
The working principle of the high-power inverter parallel system based on SPI communication is as follows:
and the upper computer is used for controlling the whole parallel system, and RS422 communication between the upper computer and the control units of all the inverters is started when the parallel system is powered on and started. The upper computer gives an instruction, one of the N inverters is set as a host, and the rest N-1 inverters are set as slaves.
The logic signal functions of the control unit of the inverter are respectively as follows:
the PwmEnOut _ x is a PWM pulse enabling output signal which is sent to all the slave machines by the host machine, the slave machines passively receive the signal through a PwmEnIn _ x signal interface, and the PwmEnOut _ x signal interface of the slave machines always outputs 0; when the parallel inverter is in standby, the host PwmEnOut _ x is 0, and when the parallel inverter works, the host PwmEnOut _ x is 1;
PwmStrobeOut _ x is a PWM pulse loading signal, the signal is sent to all the slaves by the master, the slaves passively receive the signal through a PwmStrobeIn _ x signal interface, and PwmStrobeOut _ x of the slaves always outputs 0;
the FaultOut _ x is an inverter fault output signal, when the inverter is normal and has no fault, the FaultOut _ x is 0, otherwise, the FaultOut _ x is 1; each inverter control unit sends the self FaultOut _ x signal to all other inverters through a logic signal output interface, and meanwhile, each inverter control unit receives the FaultOut _ x signals of other inverters through a FaultIn _ x signal interface. Therefore, when any one inverter fails, the FaultIn _ x signal interfaces of the remaining N-1 inverter control units connected to the failed inverter control unit will receive a 1.
The high-power inverter parallel system synchronization method based on SPI communication as shown in FIG. 3 is as follows:
step 1: in each modulation wave period, the upper computer sends a data frame to all the inverter control units through RS422 communication, and the data frame comprises a voltage instruction and a PWM pulse enabling instruction; the inverter control unit sends self state data to the upper computer every time the upper computer sends a data frame, wherein the state data comprises the serial number of the inverter, the current working state, detailed fault information and the identity of a master machine and a slave machine;
step 2: after all the inverter control units receive the data frame of the upper computer, caching the PWM pulse enabling instruction and the voltage instruction; the control units of all the inverters execute a modulation algorithm according to the voltage command, generate PWM (pulse-width modulation) waves and PWM pulse signals and cache the PWM waves and the PWM pulse signals; the master control unit sends the generated PWM pulse signal to the slave control unit through SPI communication, the slave control unit sends a response message to the master control unit each time the slave control unit receives the PWM pulse message sent by the master control unit, the slave control unit caches the PWM pulse signal after receiving the PWM pulse signal, and the PWM pulse signal generated by the slave control unit is covered at the moment;
the master control unit detects a PWM pulse enabling instruction, if the PWM pulse enabling instruction is 0, the system is in standby, at the moment, the master control unit sets all PwmEnOut _ x signals to be 0 and sends the PwmEnOut _ x signals to the slave control unit, and if the PWM pulse enabling instruction is 1, the inverter starts to work, the master control unit sets the PwmEnOut _ x signals to be 1 and sends the PwmEnOut _ x signals to the slave control unit;
and step 3: the host control unit compares the PWM modulation wave with the PWM carrier in real time, and when the size relation between the PWM modulation wave and the PWM carrier changes, the host control unit immediately inverts a logic signal PwmStrobeOut _ x;
meanwhile, if the PWM pulse enable command is 1, the host control unit loads the buffered PWM pulse signal after a delay, and sends the PWM pulse signal to the main circuit unit, where the delay is to compensate the transmission delay of the logic signal PwmStrobeOut _ x, so as to improve the synchronization accuracy (the length of the delay is related to hardware, usually ns level, and is not limited herein); if the PWM pulse enable instruction is 0, the system keeps a standby state;
and 4, step 4: the slave control unit detects a PwmEnIn _ x signal interface and a PwmStrobeIn _ x signal interface which are connected with the master control unit in real time;
when the PwmEnIn _ x signal sent by the master control unit is 0, the slave keeps a standby state; when the PwmEnIn _ x signal sent by the host control unit is 1, the inverter starts to work; when the PwmStrobeIn _ x signal transmitted by the host changes, the slave control unit immediately loads the buffered PWM pulse signal and sends the PWM pulse signal to the master circuit unit.
In this embodiment, the SPI communication rate is 7Mbps, and the carrier cycle is 500 us. In each carrier cycle, the upper computer sends a voltage command and a PWM pulse enabling command once, and meanwhile, the master control unit sends PWM pulse information once to the slave control unit. The pulse synchronization precision can be controlled within 500 ns.
When the parallel inverter system fails, the smooth switching of the master and the slave is required to be realized. The faults include online faults and offline faults. An online fault means that the inverter is communicating normally but cannot continue to operate due to software or hardware faults. The offline fault refers to the condition that the communication between the inverter and the system is interrupted and the inverter cannot be synchronized with other inverters.
When the inverter fails, all inverter control units are arranged in an ascending order according to the inverter serial numbers to establish an inverter information queue for realizing system reconstruction, wherein the inverter serial numbers are unique and fixed. The inverter information queue includes the serial number of each inverter and the corresponding fault flag bit. And if the FaultIn _ x signal of the corresponding inverter is 0 and the inverter is on line, setting the fault flag bit of the corresponding inverter in the queue to be 0. And if the FaultIn _ x signal of the corresponding inverter is 1 or the inverter is offline, setting the fault flag bit of the corresponding inverter in the queue to be 1.
When the inverter fails, the method for switching the parallel system of the high-power inverter based on the SPI communication on line, as shown in fig. 4, comprises the following steps:
step 1: after the master control unit sends the PWM pulse signal, the response information of the slave control unit is detected; if no response information is detected, the master control unit sends the PWM pulse signal to the slave control unit again for K times, and if the slave control unit does not respond, the slave control unit is offline;
the method comprises the following steps that a host control unit sets a PwmEnOut _ x signal and a PwmStobeOut _ x signal sent to an offline slave to be 0, so that the offline slave exits a parallel system, meanwhile, the host control unit sends a queue updating instruction to all slave control units, and the slave control unit sets a fault flag bit of the offline slave in a queue to be 1 after receiving the queue updating instruction;
step 2: if a faultIn _ x signal received by the host control unit is 1, indicating that a corresponding slave machine has a fault, setting a PwmEnOut _ x signal and a PwmStrobeOut _ x signal which are sent to the fault slave machine to be 0 by the host control unit, and enabling the fault slave machine to exit the parallel system; meanwhile, the master control unit sends a queue updating instruction to all the slave control units, and after receiving the queue updating instruction, the slave control units set the fault flag bit of the fault slave in the queue to be 1;
and step 3: if the master machine has a fault but is not offline, the master machine control unit selects the slave machine which is closest to the head of the queue and has a fault zone bit of 0 from the queue as a new master machine, and then sends a master machine updating instruction to all the slave machine control units; the selected slave control unit automatically becomes a master after receiving the master updating instruction and starts to send PWM pulse information to the rest slaves, and the rest slave control units start to receive the PWM pulse information of a new master after receiving the master updating instruction and send response information; meanwhile, all inverter control units update the fault flag bit of the original fault host to 1, and the new host sets the PwmEnOut _ x signal and the PemStrobeOut _ x which are sent to the original fault host to 0, so that the fault inverter exits from the parallel system, and a new master-slave relationship is established;
and 4, step 4: all slave control units detect PWM pulse information sent by the host, if the PWM pulse information is detected, the host works normally, otherwise, the host is offline, and the slave sends host offline information to all inverters;
and 5: after the inverter control units receive host offline information, all the inverter control units without faults send self health information to other inverter control units, wherein the health information comprises an inverter serial number and a fault flag bit, and the fault inverters do not send self health information; after all the inverter control units receive the health information, an inverter information queue is established again according to the ascending sequence of the inverter serial numbers, all the inverters in the queue are fault-free and online inverters, and the health information received by the inverter control units is the same, so the reestablished queue is also the same;
after the queues are established, the inverter at the head of the queues automatically becomes a new host, the new host control unit firstly sends a host updating instruction to the slave control units in all the queues, all the slave control units start to receive the PWM pulse information of the host and reply response information after receiving the host updating instruction, and the establishment of the new master-slave relationship is completed. The master control unit sets the pwmenoutx and PwmStrobe _ x signals sent to inverters not in the queue to 0, causing these inverters to exit the parallel system.
The invention has been described in detail for the purpose of illustration only and is not to be construed as limited thereby, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. Those not described in detail in this specification are within the skill of the art.
Claims (2)
1. The utility model provides a high-power inverter parallel system based on SPI communication which characterized in that: the system comprises an upper computer and N inverters connected in parallel, wherein the N inverters comprise a host and N-1 slave machines, each inverter has a unique and fixed serial number, and each inverter comprises a control unit and a main circuit unit; the upper computer is connected with the control unit of each inverter through a standard RS422 communication line, a PWM pulse signal input interface of a main circuit unit of each inverter is connected with a PWM pulse signal output interface of the control unit, the control units of the parallel inverters are connected in pairs through SPI communication, and each group of logic signal interfaces of the parallel inverter control units are connected with a logic signal interface of the other inverter control unit;
each group of logic signal interfaces comprises six binary logic signal interfaces, wherein three paths are output interfaces and are used for outputting three logic signals: a PWM enabling output signal PwmEnOut _ x, a PWM pulse loading output signal PwmStrobeOut _ x, and an inverter fault output signal FaultOut _ x; the other three paths are input interfaces and are used for receiving three logic signals: a PWM enabling input signal PwmEnIn _ x, a PWM pulse loading input signal PwmStrobeIn _ x and an inverter fault input signal FaultIn _ x, wherein x is a serial number of a logic signal and ranges from 1 to N-1;
the high-power inverter parallel system synchronization method based on SPI communication comprises the following steps:
step 1: in each modulation wave period, the upper computer sends a data frame to all the inverter control units through the RS422 communication line, and the data frame comprises a voltage instruction and a PWM pulse enabling instruction; the inverter control unit sends the state data of the inverter control unit to the upper computer every time the upper computer sends a data frame;
step 2: after all the inverter control units receive the data frame of the upper computer, caching the PWM pulse enabling instruction and the voltage instruction; the control units of all the inverters execute a modulation algorithm according to the voltage command, generate PWM (pulse-width modulation) waves and PWM pulse signals and cache the PWM waves and the PWM pulse signals; the master control unit sends the generated PWM pulse signal to the slave control unit through SPI communication, the slave control unit sends a response message to the master control unit each time the slave control unit receives the PWM pulse signal sent by the master control unit, the slave control unit caches the PWM pulse signal after receiving the PWM pulse signal, and the PWM pulse signal generated by the slave control unit is covered at the moment;
the master control unit detects a PWM pulse enabling instruction, if the PWM pulse enabling instruction is 0, the system is in standby, at the moment, the master control unit sets all PwmEnOut _ x signals to be 0 and sends the PwmEnOut _ x signals to the slave control unit, and if the PWM pulse enabling instruction is 1, the inverter starts to work, the master control unit sets the PwmEnOut _ x signals to be 1 and sends the PwmEnOut _ x signals to the slave control unit;
and step 3: the host control unit compares the PWM modulation wave with the PWM carrier in real time, and when the size relation between the PWM modulation wave and the PWM carrier changes, the host control unit immediately inverts a logic signal PwmStrobeOut _ x;
meanwhile, if the PWM pulse enable instruction is 1, the host control unit loads the cached PWM pulse signal after time delay and sends the PWM pulse signal to the main circuit unit; if the PWM pulse enable instruction is 0, the system keeps a standby state;
and 4, step 4: the slave control unit detects a PwmEnIn _ x signal interface and a PwmStrobeIn _ x signal interface which are connected with the master control unit in real time;
when the PwmEnIn _ x signal sent by the master control unit is 0, the slave keeps a standby state; when the PwmEnIn _ x signal sent by the host control unit is 1, the inverter starts to work; when the PwmStrobeIn _ x signal transmitted by the host changes, the slave control unit immediately loads the buffered PWM pulse signal and sends the PWM pulse signal to the master circuit unit.
2. The high-power inverter parallel system based on SPI communication according to claim 1, characterized in that: in the step 1, the state data includes the serial number of the inverter, the current working state, the detailed fault information and the identity of the master and the slave.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010496448.2A CN111817592B (en) | 2020-06-03 | 2020-06-03 | High-power inverter parallel system based on SPI communication, synchronization method and online switching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010496448.2A CN111817592B (en) | 2020-06-03 | 2020-06-03 | High-power inverter parallel system based on SPI communication, synchronization method and online switching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111817592A CN111817592A (en) | 2020-10-23 |
| CN111817592B true CN111817592B (en) | 2021-11-02 |
Family
ID=72847923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010496448.2A Active CN111817592B (en) | 2020-06-03 | 2020-06-03 | High-power inverter parallel system based on SPI communication, synchronization method and online switching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111817592B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104002B (en) * | 2020-11-04 | 2021-03-02 | 武汉精能电子技术有限公司 | Alternating current power supply parallel operation method and device |
| CN113676069B (en) * | 2021-09-08 | 2023-06-16 | 新风光电子科技股份有限公司 | Parallel circulation suppression method for cascaded high-voltage frequency converter |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7277304B2 (en) * | 2005-09-23 | 2007-10-02 | Gm Global Technology Operations, Inc. | Multiple inverter system with single controller and related operating method |
| CN103280999B (en) * | 2013-04-24 | 2015-06-10 | 浙江大学 | Multi-module inverter wired parallel digital control method |
| CN104486059B (en) * | 2015-01-04 | 2018-07-03 | 阳光电源股份有限公司 | A kind of photovoltaic DC-to-AC converter parallel system carrier synchronization method and device |
| CN104950765B (en) * | 2015-06-23 | 2017-09-22 | 合肥工业大学 | A kind of inverter parallel system and its carrier synchronization method based on CAN |
| CN105391089B (en) * | 2015-12-21 | 2018-06-26 | 中国西电电气股份有限公司 | The control method for parallel and circuit of a kind of inverter |
| CN110392009A (en) * | 2019-06-26 | 2019-10-29 | 天津电气科学研究院有限公司 | Multi-inverter parallel carrier synchronization device and its synchronous method with redundancy feature |
| CN110932645A (en) * | 2019-12-30 | 2020-03-27 | 卧龙电气集团辽宁荣信电气传动有限公司 | High-voltage frequency converter dual-control machine redundancy topology structure and control method |
-
2020
- 2020-06-03 CN CN202010496448.2A patent/CN111817592B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111817592A (en) | 2020-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2408102B1 (en) | Power layer generation of inverter gate drive signals | |
| CN111817592B (en) | High-power inverter parallel system based on SPI communication, synchronization method and online switching method | |
| CN105680567A (en) | Fault processing method, device and system of converter system | |
| CN102820802B (en) | Inverter system and signal transfer method thereof | |
| KR100738571B1 (en) | Cascaded H-bridge Inverter System Using CAN Communication Interrupt | |
| CN101478282A (en) | Method for realizing high voltage frequency transformer main control system by built-in dual-port RAM of FPGA | |
| CN110768291B (en) | Redundancy control method for wind power converter and wind power converter using same | |
| KR101141038B1 (en) | Parallel DC/DC converter control system using CAN communication | |
| CN111884493A (en) | Multi-power-supply master-slave multi-machine communication method and multi-power-supply system | |
| CN111490591B (en) | Upper layer controller, upper layer control system and upper layer control method of modularized wind power converter | |
| CN111181169A (en) | Control method and device for SVG parallel operation system and storage medium | |
| CN216390529U (en) | Inverter parallel system and grid-connected power generation system | |
| CN116388396A (en) | High-speed parallel operation method and device based on analog-digital mixing | |
| CN113341807B (en) | Ship direct-current power distribution system power station control system and method and application | |
| CN113541187B (en) | Intermediate frequency sine wave alternating current power supply parallel operation system and control system thereof | |
| CN213937776U (en) | Motor master-slave control device and distributed control device | |
| CN103904658A (en) | Modularized multi-level converter with bridge arm redundancy function and control method thereof | |
| KR20240038038A (en) | Solar system and control method | |
| CN107888057A (en) | The master ＆ slave control system and its control method of a kind of subway energy back feed device | |
| CN209858959U (en) | Communication control device for pure electric ship | |
| CN108255106B (en) | High-speed communication centralized control unit and method for secondary equipment of high-voltage direct-current circuit breaker | |
| KR100786696B1 (en) | H-bridge inverter system using serial communication | |
| CN112994492B (en) | Inverter apparatus and output synchronization method thereof | |
| CN109361309B (en) | Parallel inverter system and wave-by-wave current limiting control method | |
| CN213990156U (en) | Power grid power adjusting equipment and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |