CN104977859B - A kind of frequency converter parallel control system and its fault tolerant control method - Google Patents
A kind of frequency converter parallel control system and its fault tolerant control method Download PDFInfo
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Abstract
The present invention provides a kind of frequency converter parallel control system, including multiple controllers, wherein each controller is used to control a corresponding frequency converter in frequency converter parallel-connection structure；Each controller includes：First input interface, the first output interface, the second input interface, the second output interface and a circuit switching unit, the circuit switching unit is used to control first output interface and second output interface switches between following three connection status：The state for connecting local first input interface connects the state of local second input interface, and the state disconnected with local the first input interface and the second input interface；First output interface of each controller connects to form inner ring with the first input interface step by step, and the second output interface of each controller connects to form outer shroud step by step with the second input interface.The present invention has very strong fault-tolerant ability, while also having high synchronization accuracy.
Description
Technical field
The present invention relates to motor and technical field of electric control, specifically, the present invention relates to a kind of frequency converter and joint controls
System processed and its fault tolerant control method.
Background technology
Frequency converter (Variable-frequency Drive, VFD) is to apply converter technique and microelectric technique, by changing
Become motor working power Frequency Patterns to control the power driven equipment of ac motor, it is widely used in metallurgy, oil, change
The every field such as work, weaving, electric power, building materials, coal.
With the development of industry, more and more prominent the problem of single inverter underpower, if simultaneously by more frequency converters
Connection, then can effectively improve motor driving capability.And to make more frequency converter synchronous operations in parallel, need unified control
System processed.
Fig. 1 shows that a kind of schematic diagram with frequency converter parallel-connection structure driving motor in the prior art, frequency converter are in parallel
In structure, each frequency converter 2 connects a corresponding resistance R and forms a branch, then again by each branch circuit parallel connection, with driving
Motor M work, this parallel-connection structure can realize powerful motor driving.Wherein, each frequency converter 2 is all connected with a controller
1.These controllers 1 need to be interconnected to constitute frequency converter parallel control system with the communications cable (such as cable or optical fiber).
Fig. 2 shows a kind of structures of typical frequency converter parallel control system in the prior art.Each box indicates a control in figure
Device processed, for ease of description, representing the series of controller with the number in box.Select wherein the 1st grade of controller as main control
Device, remaining 2~n grades of controller are used as from controller.Master controller and all have a signal output from controller
With a signal input, with the input of triangle representation signal, delivery outlet in figure.The signal output of master controller passes through communication
Cable is connect with one from the signal input of controller, should from the signal output of controller again by the communications cable with it is next
Grade is connected from the signal input of controller, repeatedly, until being connected to afterbody from controller, i.e. n-th grade of controller,
Afterbody connects the signal input of master controller from the signal output of controller by the communications cable again.Thus formed
One bars transmits circuit, and the signal sent out by master controller can transmit circuit by the signal and pass to every level-one from control
Device processed, and the signal input of the master controller is returned, to realize being uniformly controlled to all frequency converters in parallel-connection structure.
This equipment room connection scheme does not need master controller and is each separately connected the communications cable from controller, on the one hand makes main control
Device need not also design excessive input, output interface, on the other hand, can reduce the number of the communications cable, shorten communication line
The length of cable convenient for wiring and saves cable cost.
However, the control system fault-tolerant ability of Fig. 2 is relatively low, and any frequency converter or controller failure, Huo Zheren
What one section of communications cable open circuit can all cause entire control system to fail.Further, frequency converter parallel-connection structure often requires that
High synchronization accuracy, therefore, should have redundancy fault-tolerant ability, ensure again high synchronization accuracy be current frequency converter simultaneously
Join a great problem of control technology.
Invention content
The object of the present invention is to provide a kind of solutions that can overcome above-mentioned technical problem.
The present invention provides a kind of frequency converter parallel control system, including at least three controllers, at least three control
Each controller in device processed is used to control a corresponding frequency converter in frequency converter parallel-connection structure；Each controller
Include：One first input interface, one first output interface, one second input interface, one second output interface and a circuit
Switch unit, the circuit switching unit switch between three connection status for controlling first output interface, and described the
Three connection status of one output interface are：The state for connecting local first input interface connects local described the
The state of two input interfaces, and the state that is disconnected with local the first input interface and the second input interface, the circuit
Switch unit is additionally operable to control second output interface to be switched between three connection status, three of second output interface
Connection status is：The state for connecting local first input interface, connects the state of local second input interface,
And the state disconnected with local the first input interface and the second input interface；
At least three controller connects in the following manner：At least three controller is denoted as the 1st grade of control successively
Device processed, the 2nd grade of controller ... ..., n-th grade of controller, n is at least 3 integer, wherein the first output of i-stage controller
Interface connects the first input interface of i+1 grade controller, the second output interface connection i-stage control of i+1 grade controller
Second input interface of device, i are integer and 1≤i≤n-1, and the first output interface of n-th grade of controller connects the 1st grade of controller
The first input interface, the second output interface of the 1st grade of controller connects the second input interface of n-th grade of controller.
Wherein, each controller further comprises：One timer, for providing clock information to be local；At least
In first input interface and second input interface of one capture unit, at least one capture unit and local
At least one connection, for capture the high and low level change moment from the data of external input local and record last time
Change the clock readings at moment；An and clock calibration unit；The 1st grade of controller after often sending out one group of status data,
Then the clock readings that the capture unit of the 1st grade of controller is currently recorded is sent out, in the 2nd to n grade of controller
Each controller, it is poor according to local and the series of the 1st grade of controller that the clock calibration unit is used for, and is currently remembered to local
The clock readings of record carries out compensation of delay, and by after compensation of delay local clock readings and the 1st grade of control receiving
The clock readings of device processed is compared, then tunes up or slow down local timer based on comparative result.
The present invention also provides the fault tolerant control methods based on above-mentioned frequency converter parallel control system, include the following steps：
1) using the 1st grade of controller as master controller, the first output interface of the master controller is placed in and this
The state that first input interface and the second input interface on ground disconnect, by remaining controller in addition to the 1st grade of controller
As from controller, by each shape for being placed in local first input interface of connection from the first output interface of controller
State；The master controller sends out status data by its first output interface, and master controller and each logical from controller
It crosses respective first input interface and receives the status data, and corresponding drive waveforms are exported to corresponding frequency converter；
If 2) the first input interface of the master controller can not receive the data sent out from the master controller,
Second output interface of the master controller is placed in the shape disconnected with the first local input interface and the second input interface
State, by each state for being placed in local second input interface of connection from the second output interface of controller；The master control
Device processed sends out status data by its second output interface, and master controller and each passes through respective second from controller
Input interface receives the data, and exports corresponding drive waveforms to corresponding frequency converter.
Wherein, in the step 2), if the second input interface of the master controller can not be received from the master control
3) data that second output interface of device processed is sent out, then follow the steps；
3) abort situation is detected, it is for before abort situation and the controller nearest from abort situation, it is second defeated
Outgoing interface is placed in the state of local first input interface of connection, for being located at after abort situation and nearest from abort situation
Controller, its first output interface is placed in the state of local second input interface of connection, also, for main control
Its second output interface is placed in the state of local second input interface of connection by device；The master controller by its
One output interface sends out status data, and master controller and each passes through respective first input interface from controller and receive
The status data, and export corresponding drive waveforms to corresponding frequency converter.
Wherein, in the frequency converter parallel control system, each controller further comprises：One timer is used
In providing clock information to be local；And at least one capture unit, at least one capture unit and local described the
At least one of one input interface and second input interface connect, for capturing from the data of external input local
The high and low level change moment simultaneously records the clock readings that last time changes the moment；
In the fault tolerant control method, the step 1), 2), 3) in, the master controller is often sending out one group of status number
According to rear, the clock readings that the capture unit of master controller is currently recorded then is sent out, it is described each from the equal root of controller
According to local and master controller series, compensation of delay is carried out to local current the recorded clock readings, and will prolong
When compensation after local clock readings be compared with the clock readings of the master controller received, then adjust based on comparative result
It is fast or slow down local timer.
Wherein, in the step 1), for kth grade controller, compensation of delay is when will be local current recorded described
Clock reading adds n+1-k times of basic compensation of delay amount, wherein 2≤k≤n, the basic compensation of delay amount is that signal passes through
Mean transit delay amount when one controller one time.
Wherein, in the step 2), for kth grade controller, compensation of delay is when will be local current recorded described
Clock reading adds k-1 times of basic compensation of delay amount, wherein 2≤k≤n, the basic compensation of delay amount are signals by one
Mean transit delay amount when controller one time.
Wherein, in the step 3), the detection abort situation includes：
31) it utilizes the first output interface of master controller to send test data, and is connect using the second input of master controller
Mouth intercepts the test data that first output interface is sent, positive detection master controller step by step to the rings at different levels from controller
Road, until finding failure；
32) it utilizes the second output interface of master controller to send test data, and is connect using the first input of master controller
Mouth intercepts the test data that second output interface is sent, and reversely detects master controller step by step to the rings at different levels from controller
Road, until finding failure；
33) if the first input interface of master controller does not receive test number when step-by-step measurement is to m grades of controllers
According to the second input interface does not receive test data when step-by-step measurement is to m-1 grades of controllers, then judging m-1 grades of controls
Fiber failure between device processed and m grades of controllers；If the first input interface of master controller is controlled in step-by-step measurement to m grades
Device processed does not receive test data, and the second input interface does not receive test data in step-by-step measurement to m grades of controllers yet, that
Judge m grades of controller failures, 2≤m≤n.
Wherein, in the step 3), it is assumed that the fiber failure between m-1 grades of controllers and m grades of controllers, then right
In kth grade controller, if 2≤k≤m-1, compensation of delay is that local current the recorded clock readings is added 2n-
K-1 times of basic compensation of delay amount, if m≤k≤n, compensation of delay is by local current the recorded clock readings
In addition n-k+1 times of basic compensation of delay amount；
Assuming that m grades of controller failures, then for kth grade controller, if 2≤k≤m-1, compensation of delay be by
Local current the recorded clock readings adds 2n-k-3 times of basic compensation of delay amount, if m+1≤k≤n, is delayed
Compensation is the basic compensation of delay amount that local current the recorded clock readings is added to n-k+1 times.
Compared with prior art, the present invention has following technique effect：
1, control system of the invention significantly improves fault-tolerant ability compared with the scheme of Fig. 1.
2, control system of the invention can diagnose fault automatically, and automatic Reconstruction signal transmits circuit after breaking down.
3, control system of the invention has high synchronization accuracy (can reach 10~20 nanosecond rank), and is occurring
After failure, control system of the invention can not only automatic Reconstruction signal transmit circuit, moreover it is possible to keep original synchronization accuracy.
4, control system of the invention can be automatically closed failure frequency converter, and then save the energy.
Description of the drawings
A kind of schematic diagrames with frequency converter parallel-connection structure driving motor of Fig. 1；
Fig. 2 shows a kind of structure charts of typical frequency converter parallel control system in the prior art；
Fig. 3 shows the structure chart of the frequency converter parallel control system of one embodiment of the invention；
Fig. 4~6 show the structure of controller 1 used by Fig. 3 embodiments and three kinds of internal connection states；
Fig. 7 shows the signal of the frequency converter parallel control system under normal operating conditions in one embodiment of the invention
Figure；
Fig. 8 shows the schematic diagram of the frequency converter parallel control system under malfunction 1 in one embodiment of the invention；
Fig. 9 shows the schematic diagram of the frequency converter parallel control system under malfunction 2 in one embodiment of the invention；
Figure 10 shows the schematic diagram of the frequency converter parallel control system under malfunction 3 in one embodiment of the invention；
And
Figure 11 shows the electrical block diagram of the controller in one embodiment of the invention.
Specific implementation mode
The present invention is further described through in the following with reference to the drawings and specific embodiments.
Fig. 3 shows the frequency converter parallel control system provided according to one embodiment of present invention, including at least three
A controller, wherein each controller is for controlling a corresponding frequency converter.Each frequency converter parallel drive motor operating, this
In embodiment, the mode with frequency converter parallel-connection structure driving motor is consistent with Fig. 1, and details are not described herein again.The knot of each controller
Structure is consistent, and Fig. 4~6 show the structure of controller 1 used by Fig. 3 embodiments and three kinds of internal connection states.
As shown in figure 4, controller 1 includes：One first input interface 11, one first output interface 12, one second input connect
Mouth 13, one second output interface 14, a first line switch unit 15 and one second circuit switching unit 16.Wherein, first
Circuit switching unit 15 is for controlling switching of first output interface 12 between three connection status, the first output interface 12
Three connection status be respectively：The state (as shown in Figure 4) for connecting the first local input interface 11, connects local second
The state (as shown in Figure 5) of input interface 13, and disconnected with local the first input interface 11 and the second input interface 13
State (as shown in Figure 6).Second circuit switching unit 16 is for controlling second output interface 14 in three connection status
Between switching, three connection status of the second output interface 14 are respectively：Connect the state of the first local input interface 11 (such as
Shown in Fig. 5), connect the state (as shown in Figure 4) of the second local input interface 13, and the first input interface with local
11 and second state (as shown in Figure 6) that disconnects of input interface 13.First line switch unit 15 and the second circuit switching list
Member 16 can collectively form a total line switch unit, this total line switch unit can control local signal flow direction.Always
In circuit switching unit, first line switch unit 15 and the second circuit switching unit 16 can respective independent works.
Referring still to Fig. 3, also shown is the connection relation of each controller in frequency converter parallel control system, in figure
Each box represents a controller, and the junction curve between box represents communication line (such as optical fiber), triangle is used in figure
Shape represents input interface and output interface.For ease of description, each controller is denoted as the 1st grade of controller successively, the 2nd grade
Controller ... ..., n-th grade of controller, n are at least 3 integers, wherein the first output interface of i-stage controller connection the
First input interface of i+1 grades of controllers, the second of the second output interface connection i-stage controller of i+1 grade controller are defeated
Incoming interface, i is integer and 1≤i≤n-1, also, the first output interface of n-th grade of controller connects the first of the 1st grade of controller
Input interface, the second output interface of the 1st grade of controller connect the second input interface of n-th grade of controller.It especially emphasizes, Fig. 3
In the input of shown each controller, output interface, it is the first input or output interface to be connected in inner ring 3, even
It is second signal input or output interface to be connected on outer shroud 4.
The working method of the frequency converter parallel control system of Fig. 3 is described with reference to Fig. 7~10.
Fig. 7 shows the schematic diagram of the frequency converter parallel control system under normal operating conditions.In normal operation,
Using the 1st grade of controller as master controller, by the first output interface of master controller be placed in the first local input interface and
Remaining controller in addition to the 1st grade of controller is used as from controller by the state that the second input interface disconnects, will
The state of local first input interface of connection is each placed in from the first output interface of controller, as shown in Figure 7.Just
Under normal working condition, the master controller sends out master controller status data, and master controller by its first output interface
The master controller status data is received by respective first input interface from controller with each.Master controller status number
According to some key times of mainly Frequency Converter Control algorithm, being each based on these input variables from controller can calculate
The current drive waveforms for needing to export to local frequency converter.Frequency Converter Control algorithm has been mature technology, and with lead herein
Purport is unrelated, so not repeating herein.Master controller and each after controller receives master controller status data, respectively
It obtains corresponding drive waveforms and exports the drive waveforms obtained and give (the change of i.e. each controller local of corresponding frequency converter
Frequency device).
Fig. 8 shows the schematic diagram of the frequency converter parallel control system under malfunction 1.If the of the master controller
One input interface can not receive the data sent out from the master controller, indicate that the inner ring of frequency converter parallel control system exists
Failure, at this point, the second output interface of the master controller is placed in and local the first input interface and the second input interface
The state disconnected, by each shape for being placed in local second input interface of connection from the second output interface of controller
State, as shown in Figure 8.Under malfunction 1, master controller sends out master controller status data by its second output interface, and
Master controller and the master controller status data is each received by respective second input interface from controller, and to institute
Corresponding frequency converter exports corresponding drive waveforms.
If frequency converter parallel control system, after establishing connection shown in Fig. 8, the second input of the master controller connects
Mouth still can not receive the data sent out from the second output interface of the master controller, then illustrate that inner ring and outer rings occur
Failure needs to check abort situation at this time.Can be seen that checked abort situation from Fig. 9, Figure 10, there may be two kinds
Situation is referred to as malfunction 2 and malfunction 3 in text, if the abort situation checked is at m-1 to m grades
At optical fiber between controller, then judge that at this time as malfunction 2, Fig. 9 shows the frequency converter Parallel Control under malfunction 2
The schematic diagram of system.If the abort situation checked at m grades of controllers, i.e. m grades of controller itself failures are then sentenced
Disconnected is malfunction 3 at this time, and Figure 10 shows the schematic diagram of the frequency converter parallel control system under malfunction 3.
It with reference to figure 9, nonserviceables under 2, for before abort situation and the controller nearest from abort situation, i.e.,
Its second output interface is placed in the state of local first input interface of connection, for being located at failure by m-1 grades of controllers
Behind position and the controller nearest from abort situation, i.e. m grades of controllers, its first output interface is placed in the local institute of connection
The state of the second input interface is stated, also, for master controller, its second output interface is placed in the second local input of connection
The state of interface.Master controller sends out master controller status data by its first output interface, and master controller and each
The master controller status data is received by respective first input interface from controller, and defeated to corresponding frequency converter
Go out corresponding drive waveforms.
It with reference to figure 10, nonserviceables under 3, for before abort situation and the controller nearest from abort situation, i.e.,
Its second output interface is placed in the state of local first input interface of connection by m-1 grades of controllers, for being located at event
Hinder position after and the controller nearest from abort situation, i.e. m+1 grade controllers, by its first output interface be placed in connection local
Second input interface state, also, for master controller, its second output interface is placed in local second of connection
The state of input interface.Master controller sends out master controller status data by its first output interface, and master controller and
The master controller status data is each received by respective first input interface from controller, and to corresponding frequency conversion
Device exports corresponding drive waveforms.
In one embodiment, frequency converter parallel control system checks abort situation by investigating step by step, including following
Step.
Step 1：First output interface of master controller (i.e. the 1st grade of controller) is placed in first input with local
Its second output interface is also placed in first input interface with local by the state that interface and the second input interface disconnect
The state disconnected with the second input interface.
Step 2：Using the 2nd grade of controller as tested from controller, it is placed in tested from the second output interface of controller
Connect the state of the first local input interface.First output interface of master controller sends out test data, if master controller
The first input interface the test data is received in preset time, then the circuit of master controller to the 2nd grade of controller is normal,
For convenience of description, current being tested from the series of controller is denoted as i, enters step 3, if the first input of master controller
Interface does not receive the test data in preset time, then enters step 6.
Step 3：First output interface of i-stage controller is placed in the state of the first local input interface of connection, the
Two output interfaces are placed in the state of the second local input interface of connection；Second output interface of i+1 grade controller is placed in
Connect the state of the first local input interface.First output interface of master controller sends out test data, if master controller
The first input interface the test data is received in preset time, then the circuit of master controller to i+1 grade controller is being just
Often, so that variable i is increased by 1, even i=i+1, then repeat step 3, until the first input interface of master controller cannot
The test data is received in preset time, enters step 6 at this time.
Step 4：First output interface of n-th grade of controller is placed in the shape of the second local input interface of connection
Second output interface of state, master controller sends out test data, if the second input interface of master controller is in preset time
Receiving the test data, then the circuit of master controller to n-th grade of controller is normal, enters step 5, for ease of being described below,
Current being tested from the series of controller is denoted as n-i+2, this is opposite with being tested from the series of controller in step 3
It answers, if the second input interface of master controller does not receive the test data in preset time, enters step 6.
Step 5：First output interface of the n-th-i+2 grades of controller is placed in the shape of the first local input interface of connection
State, the second output interface are placed in the state of the second local input interface of connection；By the first output of the n-th-i+1 grades of controller
Interface is placed in the state of the second local input interface of connection.Second output interface of master controller sends out test data, if
Second input interface of master controller receives the test data in preset time, then master controller to the n-th-i+1 grades of control
The circuit of device is normal, so that variable i is increased by 1, even i=i+1, then repeats step 5, until the second input of master controller
Interface cannot receive the test data in preset time, enter step 6 at this time.
Above-mentioned steps 2,3 are positive detections step by step, and step 3,4 are reversed detections step by step, positive to save the time
Detection synchronous can be carried out with reversed detection step by step step by step.
Step 6：If the first input interface of master controller does not receive test when step-by-step measurement is to m grades of controllers
Data, the second input interface does not receive test data when step-by-step measurement is to m-1 grades of controllers, then judging m-1 grades
Fiber failure between controller and m grades of controllers, current state belong to malfunction 2.If the first of master controller is defeated
Incoming interface does not receive test data in step-by-step measurement to m grades of controllers, and the second input interface is also in step-by-step measurement to m
Grade controller does not receive test data, then judging m grades of controller failures, current state belongs to malfunction 3.If main
First input interface of controller does not receive test data when step-by-step measurement is to m grades of controllers, and the second input interface exists
Step-by-step measurement then exceeds the appearance of the control system of the present embodiment to m+1 or not receive test data when higher controller
Wrong range, control system report failure are simultaneously stopped.
Further, if the synchronization accuracy of frequency converter parallel-connection structure is insufficient, current spike between frequency converter may be caused
And circulation, serious current spike can directly damage power device, circulation then makes transducer power distribution in parallel uneven, leads
Parallel drive ability is caused to be restricted the aging of simultaneously accelerating part frequency converter.Therefore, frequency converter parallel-connection structure often requires that high
Synchronization accuracy.
According to one embodiment of present invention, a kind of frequency converter Parallel Control system with high synchronization accuracy is provided
System, it increases some new portions on the basis of the frequency converter parallel control system of previous embodiment on each controller
Part.Specifically, in the present embodiment, each controller further comprises：One timer, for providing clock information to be local；
One capture unit, it connect at least one of with local first input interface and second input interface, is used for
It captures the high and low level change moment from the data of external input local and records the clock readings that last time changes the moment；
An and clock calibration unit.In normal operation, level change can promote the frequency converter parallel control system each time
Capture unit is set to record a present clock reading, then after master controller distributes one group of data, all controllers can all be remembered
Record the clock readings at last time level change moment.In this way, after master controller sends out one group of master controller status data, then connect
It and sends out the clock readings that the capture unit of master controller is currently recorded, for each in the 2nd to n grade of controller
Controller, clock calibration unit is poor according to local and the series of the 1st grade of controller, reads local current the recorded clock
Number carries out compensation of delay, and by the clock readings of the local clock readings and the 1st grade of controller received after compensation of delay
It is compared, then tunes up or slow down local timer based on comparative result.
Further, according to one embodiment of present invention, in frequency converter parallel control system, each controller into
One step includes a control unit, built-in timer and buffer unit in control unit.As shown in figure 11, control unit includes following
Interface：It connects the first signal receiving interface RX1 of the first input interface 11 and the first input signal captures interface Cap1, connection the
First signal transmission interface TX1 of one output interface 12 connects the second signal receiving interface RX2 and the of the second input interface 13
Two input signals capture interface Cap2, connect the second signal transmission interface TX2 of the second output interface 14.Wherein, the first signal
Receiving interface RX1, second signal receiving interface RX2 are used to receive the master controller status data that previous stage controller transmits, the
One input signal captures interface Cap1, the second input signal captures the height that interface Cap2 is used to capture previous stage equipment derived signals
At the time of low level variation (can be captured according to signal rising edge or failing edge), signal capture interface and buffer unit are combined,
The function of capture unit described above can be realized.In the present embodiment there is the first input signal to capture interface Cap1 and the
Two input signals capture interface two signal capture interfaces of Cap2, they are combined with buffer unit respectively, you can before constituting two
Capture unit described herein.
Further, the first, second input interface is optical signal input port, and the first, second output interface is light letter
Number delivery outlet.The optical signal received can be converted to electric signal by built-in optical receiver in optical signal input port.Optical signal is defeated
Built-in optical transmitting set in outlet, can convert electrical signals into optical signal.Optical receiver and optical transmitting set constitute a pair of of optocoupler.
Inside controller, optical receiver is connected with optical transmitting set by circuit, forms signal line.
Referring still to Figure 11, controller 1 still further comprises three triple gates 15a, 15b, 15c, these three triple gates
15a, 15b, 15c form previously described first line switch unit 15.Wherein, triple gate 15a connects for controlling the first output
The break-make of signal line between mouth 12 and the first input interface 11, triple gate 15b is for controlling the first output interface 12 and first
The break-make of signal line between signal transmission interface TX1, triple gate 15c connect for controlling the first output interface 12 with the second input
The break-make of signal line between mouth 13.The enabled stitch I/O1 controls by control unit of two triple gates 15a, 15b, and
In the two triple gates 15a, 15b, one enabled for high level, another is enabled for low level, is conducive to save control in this way
The I/O stitch numbers of unit.The enabled stitch I/O3 controls by control unit of third triple gate.Can thus it make, the
One output interface 12 can only be connected to the first input interface 11, the second input interface 13 and the transmission of the first signal in synchronization and connect
One in mouth TX1, to realize three kinds of connection status shown in Fig. 4~6.
Similarly, controller 1 still further comprises three triple gates 16a, 16b, 16c, these three triple gates 16a, 16b,
16c forms previously described second circuit switching unit 16.Wherein, triple gate 16a is for controlling the second output interface 14 and the
The break-make of signal line between two input interfaces 13, triple gate 16b are sent for controlling the second output interface 14 with second signal
The break-make of signal line between interface TX2, triple gate 16c is for controlling between the second output interface 14 and the first input interface 11
The break-make of signal line.The enabled stitch I/O2 controls by control unit of two triple gates 16a, 16b, and the two
In triple gate 16a, 16b, one enabled for high level, another is enabled for low level, is conducive to save control unit in this way
I/O stitch numbers.The enabled stitch I/O4 controls by control unit of third triple gate 16c.Can thus it make, second
Output interface 14 can only be connected to the first input interface 11, the second input interface 13 and second signal transmission interface in synchronization
One in TX2, to realize three kinds of connection status shown in Fig. 4~6.
The control system of above-described embodiment realizes that the signal between equipment transmits based on serial structure, and this structure connection is each
Optical fiber (or other cables) number needed for equipment is less, and length is shorter, and the I/O interfaces needed for master controller are also relatively fewer,
Therefore with material is saved, the advantage of equipment I/O Interface is saved.At the same time, above-mentioned control system has excellent fault-tolerant energy
Power, inner ring, outer shroud can respective independent operating, when inner ring, outer shroud simultaneous faults, can also under the control of master controller into
Row self-test simultaneously re-establishes signal loop.
As it was noted above, after master controller distributes one group of data, all controllers can all record the change of last time level
Change the clock readings at moment.In this way, after master controller sends out one group of master controller status data, followed by sending out master controller
The clock readings that capture unit is currently recorded, for each controller in the 2nd to n grade of controller, clock alignment
Unit is poor according to local and the series of the 1st grade of controller, and compensation of delay is carried out to local current the recorded clock readings,
And be compared the local clock readings after compensation of delay with the clock readings of the 1st grade of controller received, then be based on
Comparison result tunes up or slow down local timer.For kth grade controller, if the local clock readings after compensation of delay
It is completely the same with the clock readings of the 1st grade of controller received, then it is considered as the kth grade controller and master controller is completely same
Step, if not quite identical, needs correspondingly to tune up or slow down local timer.
In one embodiment, frequency converter parallel control system in normal operation, for kth grade controller,
Compensation of delay is the basic compensation of delay amount that local current the recorded clock readings is added to n+1-k times, wherein 2≤k
Mean transit delay amount when≤n, the basic compensation of delay amount are signals by controller one time, it is signal transmission
Hardware delay in the process.
When tuning up or slow down local timer, the software delays of several processor clock cycles are usually also had,
In one preferred embodiment, when replacing the old count value of timer with new count value, need to take into account software delays.Example
When should tune up t such as counter, then new count value is t0+ t+c, wherein t0For the old count value of timer, c calibrates for timer
Software delays.Software delays are executed from code, its size depends on compensation complexity, operation chip (such as
DSP dominant frequency) and instruction execution cycle, compensation (such as t0+ t+c) and operation chip determine after, timer calibration software
Delay c is also determined that.
In one embodiment, frequency converter parallel control system is nonserviceabled under 1, and for kth grade controller, delay is mended
It is the basic compensation of delay amount that local current the recorded clock readings is added to k-1 times to repay, wherein 2≤k≤n, it is described
Mean transit delay amount when basic compensation of delay amount is signal by controller one time.In a preferred embodiment,
Under malfunction 1, when replacing the old count value of timer with new count value, the software delays for calibrating timer are also needed
C takes into account, and details are not described herein again.
In one embodiment, frequency converter parallel control system is nonserviceabled under 2, it is assumed that m-1 grades of controllers and
Fiber failure between m grades of controllers, then for kth grade controller, if 2≤k≤m-1, compensation of delay is by local
The clock readings currently recorded adds 2n-k-1 times of basic compensation of delay amount, if m≤k≤n, compensation of delay
It is the basic compensation of delay amount that local current the recorded clock readings is added to n-k+1 times.Wherein, 2≤k≤n, it is described
Mean transit delay amount when basic compensation of delay amount is signal by controller one time.In a preferred embodiment,
Under malfunction 2, when replacing the old count value of timer with new count value, the software delays for calibrating timer are also needed
C takes into account, and details are not described herein again.
In one embodiment, frequency converter parallel control system is nonserviceabled under 3, it is assumed that m grades of controller failures, that
For kth grade controller, if 2≤k≤m-1, compensation of delay is to add local current the recorded clock readings
Upper 2n-k-3 times of basic compensation of delay amount, if m+1≤k≤n, compensation of delay be by it is local it is current it is recorded described in
Clock readings adds n-k+1 times of basic compensation of delay amount.Wherein, 2≤k≤n, the basic compensation of delay amount are that signal is logical
Cross mean transit delay amount when controller one time.In a preferred embodiment, under malfunction 3, with New count
When value replaces the old count value of timer, also need to take into account the software delays c that timer is calibrated, it is no longer superfluous herein
It states.
Above-described embodiment not only has redundancy fault-tolerant ability, moreover it is possible to ensure high to synchronize essence again under various malfunctions
Degree.In actual use, synchronization accuracy can reach for 10~20 nanoseconds to above-mentioned frequency converter parallel control system, help to support bigger
The frequency converter of quantity realizes parallel connection, to significantly improve its motor driving capability.
Number " one " set forth herein is not intended to be defined quantity, with the teachings of the present invention without prejudice to
In the case of can also refer to it is multiple.
The foregoing is merely the schematical specific implementation modes of the present invention, are not limited to the scope of the present invention.It is any
Those skilled in the art, do not depart from the design of the present invention and under the premise of principle made by equivalent variations, modification and combination,
The scope of protection of the invention should all be belonged to.
Claims (9)
1. a kind of frequency converter parallel control system, including at least three controllers, each control at least three controller
Device processed is all used to control a corresponding frequency converter in frequency converter parallel-connection structure；
It is characterized in that, each controller includes：One first input interface, one first output interface, one second input
Interface, one second output interface and a circuit switching unit, the circuit switching unit connect for controlling first output
Mouth switches between three connection status, and three connection status of first output interface are：Described the first of connection local is defeated
The state of incoming interface connects the state of local second input interface, and the first input interface and second with local
The state that input interface disconnects, the circuit switching unit are additionally operable to control second output interface in three connection status
Between switch, three connection status of second output interface are：Connect the state of local first input interface, connection
The state of local second input interface, and the shape that is disconnected with local the first input interface and the second input interface
State；
At least three controller connects in the following manner：At least three controller is denoted as the 1st grade of controller successively,
2nd grade of controller ... ..., n-th grade of controller, n are at least 3 integers, wherein the first output interface of i-stage controller
The first input interface of i+1 grade controller is connected, the second output interface connection i-stage controller of i+1 grade controller
Second input interface, i are integer and 1≤i≤n-1, and the first output interface of n-th grade of controller connects the of the 1st grade of controller
One input interface, the second output interface of the 1st grade of controller connect the second input interface of n-th grade of controller.
2. frequency converter parallel control system according to claim 1, which is characterized in that each controller is further
Including：One timer, for providing clock information to be local；
At least one capture unit, at least one capture unit and local first input interface and described second defeated
At least one of incoming interface connects, for capturing the high and low level change moment from the data of external input local and recording
Last time changes the clock readings at moment；And
One clock calibration unit；
The 1st grade of controller then sends out the current institute of capture unit of the 1st grade of controller after often sending out one group of status data
The clock readings of record, for each controller in the 2nd to n grade of controller, the clock calibration unit is used for root
It is poor according to local and the series of the 1st grade of controller, compensation of delay is carried out to local current the recorded clock readings, and will prolong
When compensation after local clock readings be compared with the clock readings of the 1st grade of controller received, then be based on comparing knot
Fruit tunes up or slow down local timer.
3. a kind of fault tolerant control method based on frequency converter parallel control system described in claim 1, which is characterized in that including
The following steps：
1) using the 1st grade of controller as master controller, the first output interface of the master controller is placed in and local
The state that first input interface and the second input interface disconnect, using remaining controller in addition to the 1st grade of controller as
From controller, by each state for being placed in local first input interface of connection from the first output interface of controller；Institute
It states master controller and status data is sent out by its first output interface, and master controller and each from controller by respective
The first input interface receive the status data, and export corresponding drive waveforms to corresponding frequency converter；
If 2) the first input interface of the master controller can not receive the data sent out from the master controller, by institute
The second output interface for stating master controller is placed in the state disconnected with the first local input interface and the second input interface, will
The state of local second input interface of connection is each placed in from the second output interface of controller；The master controller is logical
It crosses its second output interface and sends out status data, and master controller and each connect from controller by respective second input
Mouth receives the data, and exports corresponding drive waveforms to corresponding frequency converter.
4. fault tolerant control method according to claim 3, which is characterized in that in the step 2), if the main control
Second input interface of device can not receive the data sent out from the second output interface of the master controller, then follow the steps
3)；
3) abort situation is detected, for before abort situation and the controller nearest from abort situation, its second output is connect
Mouth is placed in the state of local first input interface of connection, for after abort situation and the control nearest from abort situation
Its first output interface, is placed in the state of local second input interface of connection by device processed, also, for master controller,
Its second output interface is placed in the state of local second input interface of connection；The master controller is first defeated by it
Outgoing interface sends out status data, and master controller and described in each being received by respective first input interface from controller
Status data, and export corresponding drive waveforms to corresponding frequency converter.
5. fault tolerant control method according to claim 4, which is characterized in that in the frequency converter parallel control system, institute
Each controller is stated to further comprise：One timer, for providing clock information to be local；And at least one capture is single
Member, at least one of at least one capture unit and local first input interface and second input interface
Connection, for capturing the high and low level change moment from the data of external input local and recording the last time variation moment
Clock readings；
In the fault tolerant control method, the step 1), 2), 3) in, the master controller after often sending out one group of status data,
Then the clock readings that the capture unit of master controller is currently recorded is sent out, it is described each from controller all in accordance with local
With the series of the master controller, compensation of delay carried out to local current the recorded clock readings, and by compensation of delay
Local clock readings afterwards is compared with the clock readings of the master controller received, then is tuned up or adjusted based on comparative result
Slow local timer.
6. fault tolerant control method according to claim 5, which is characterized in that in the step 1), kth grade is controlled
Device, compensation of delay are the basic compensation of delay amounts that local current the recorded clock readings is added to n+1-k times, wherein 2
Mean transit delay amount when≤k≤n, the basic compensation of delay amount are signals by controller one time.
7. fault tolerant control method according to claim 5, which is characterized in that in the step 2), kth grade is controlled
Device, compensation of delay are the basic compensation of delay amounts that local current the recorded clock readings is added to k-1 times, wherein 2≤
Mean transit delay amount when k≤n, the basic compensation of delay amount are signals by controller one time.
8. fault tolerant control method according to claim 5, which is characterized in that in the step 3), the detection fault bit
Set including：
31) it utilizes the first output interface of master controller to send test data, and is detectd using the second input interface of master controller
The test data for listening first output interface to send, the positive master controller of detection step by step is to the loops at different levels from controller, directly
To discovery failure；
32) it utilizes the second output interface of master controller to send test data, and is detectd using the first input interface of master controller
The test data for listening second output interface to send, reversely detection master controller is to the loops at different levels from controller step by step, directly
To discovery failure；
If 33) the first input interface of master controller does not receive test data when step-by-step measurement is to m grades of controllers, the
Two input interfaces do not receive test data when step-by-step measurement is to m-1 grades of controllers, then judge m-1 grades of controllers with
Fiber failure between m grades of controllers；If the first input interface of master controller connects in step-by-step measurement to m grades of controllers
Test data is can not receive, the second input interface does not receive test data in step-by-step measurement to m grades of controllers yet, then judging
M grades of controller failures, 2≤m≤n.
9. fault tolerant control method according to claim 8, which is characterized in that in the step 3), it is assumed that m-1 grades of controls
Fiber failure between device and m grades of controllers, then for kth grade controller, if 2≤k≤m-1, compensation of delay are
The basic compensation of delay amount that local current the recorded clock readings is added to 2n-k-1 times, if m≤k≤n, is delayed
Compensation is the basic compensation of delay amount that local current the recorded clock readings is added to n-k+1 times；
Assuming that m grades of controller failures, then for kth grade controller, if 2≤k≤m-1, compensation of delay is by local
The clock readings currently recorded adds 2n-k-3 times of basic compensation of delay amount, if m+1≤k≤n, compensation of delay
It is the basic compensation of delay amount that local current the recorded clock readings is added to n-k+1 times.
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| JP3857696B2 (en) * | 2004-03-10 | 2006-12-13 | 株式会社東芝 | Semiconductor integrated circuit and inspection method thereof |
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|---|---|---|---|---|
| CN1719687A (en) * | 2005-07-08 | 2006-01-11 | 浙江大学 | Automatic master-slave parallel apparatus for inverter |
| CN101902281A (en) * | 2010-07-07 | 2010-12-01 | 奥维通信股份有限公司 | Digital optical fiber repeater system with self-healing annular networking function and data communication method thereof |
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Effective date of registration: 20190425 Address after: Dublin, Ireland Patentee after: Eaton Intelligent Power Co.,Ltd. Address before: Ohio Patentee before: Eaton Corp. |