CN104977859A - Variable-frequency drive parallel control system and fault-tolerant control method thereof - Google Patents
Variable-frequency drive parallel control system and fault-tolerant control method thereof Download PDFInfo
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Abstract
A variable-frequency drive parallel control system provided by the present invention comprises a plurality of controllers, wherein each controller is used to control a corresponding variable-frequency drive in a variable-frequency drive parallel structure, and comprises a first input interface, a first output interface, a second input interface, a second output interface and a line switching unit. The line switching unit is used to control the first output interface and the second output interface to switch among the following three connection states of a state of connecting the local first input interface, a state of connecting the local second input interface, and a state of both disconnecting with the local first and second input interfaces. The first output interfaces and the first input interfaces of the controllers are connected in series step-by-step to form an inner ring, and the second output interfaces and the second input interfaces of the controllers are connected in series step-by-step to form an outer ring. The variable-frequency drive parallel control system of the present invention has a very strong fault tolerance capability, and also has a very high synchronization precision.
Description
Technical field
The present invention relates to motor and technical field of electric control, specifically, the present invention relates to a kind of frequency converter parallel control system and fault tolerant control method thereof.
Background technology
Frequency converter (Variable-frequency Drive, VFD) be application converter technique and microelectric technique, control the power driven equipment of AC motor by changing machine operation supply frequency mode, it is widely used in the every field such as metallurgy, oil, chemical industry, weaving, electric power, building materials, coal.
Along with industrial expansion, the under powered problem of single inverter is more and more outstanding, if multiple stage frequency converter is in parallel, then can effectively improve motor driving force.And the frequency converter synchronous operation of multiple stage parallel connection will be made, need unified control system.
Fig. 1 shows the schematic diagram of a kind of frequency converter parallel-connection structure drive motor of the prior art, in frequency converter parallel-connection structure, each frequency converter 2 connects a corresponding resistance R and forms a branch road, and then by each branch circuit parallel connection, work with drive motor M, this parallel-connection structure can realize powerful motor and drive.Wherein, each frequency converter 2 all connects a controller 1.These controllers 1 need to be connected to each other to form frequency converter parallel control system with the communications cable (such as cable or optical fiber).Fig. 2 shows the structure of a kind of typical frequency converter parallel control system in prior art.Each box indicating controller in figure, for ease of describing, with the progression of the digitized representation controller in square frame.Select wherein that the 1st grade of controller is as master controller, remaining 2nd ~ n level controller is all as from controller.Master controller and all have a signal output and a signal input from controller, with the input of triangle representation signal, delivery outlet in figure.The signal output of master controller is connected with a signal input from controller by the communications cable, should be connected with the signal input of next stage from controller by the communications cable again from the signal output of controller, so repeatedly, until be connected to afterbody from controller, i.e. n-th grade of controller, afterbody connects the signal input of master controller again from the signal output of controller by the communications cable.Material is thus formed a bars and transmit loop, the signal sent by master controller can give every one-level from controller by this signal transmission circuit transmission, and return the signal input of this master controller, thus realize controlling the unified of all frequency converters in parallel-connection structure.This equipment room connection scheme does not need master controller to be connected the communications cable with each respectively from controller, master controller is made also not need to design too much input, output interface on the one hand, on the other hand, the number of the communications cable can be reduced, shorten the length of the communications cable, be convenient to wiring and save cable cost.
But the control system fault-tolerant ability of Fig. 2 is relatively low, any frequency converter or controller failure, or any one section of communications cable open circuit, all can cause whole control system to lose efficacy.Further, frequency converter parallel-connection structure often requires high synchronization accuracy, therefore, should have redundancy fault-tolerant ability, ensures that high synchronization accuracy is a great problem of current frequency converter parallel control technology again.
Summary of the invention
The object of this invention is to provide a kind of solution that can overcome above-mentioned technical matters.
The invention provides a kind of frequency converter parallel control system, comprise at least three controllers, each controller in described at least three controllers is for controlling frequency converter corresponding in frequency converter parallel-connection structure one, described each controller includes: one first input interface, one first output interface, one second input interface, one second output interface, and a circuit switching unit, described circuit switching unit switches between three connection status for controlling described first output interface, three connection status of described first output interface are: the state connecting local described first input interface, connect the state of local described second input interface, and the state all to disconnect with the first input interface and second input interface of this locality, described circuit switching unit also switches between three connection status for controlling described second output interface, three connection status of described second output interface are: the state connecting local described first input interface, connect the state of local described second input interface, and the state all to disconnect with the first input interface and second input interface of this locality,
Described at least three controllers connect in the following manner: described at least three controllers are designated as successively the 1st grade of controller, 2nd grade of controller, n-th grade of controller, n be at least 3 integer, wherein, first output interface of i-th grade of controller connects the first input interface of the i-th+1 grade controller, second output interface of the i-th+1 grade controller connects the second input interface of i-th grade of controller, i is integer and 1≤i≤n-1, first output interface of n-th grade of controller connects the first input interface of the 1st grade of controller, second output interface of the 1st grade of controller connects the second input interface of n-th grade of controller.
Wherein, described each controller comprises all further: a timer, for providing clock information for this locality; At least one capture unit, at least one capture unit described is connected with at least one in local described first input interface and described second input interface, changes the moment and the clock readings in record last change moment for catching from the high and low level of the local data of outside input; And a clock alignment unit; Described 1st grade of controller is after often sending one group of status data, then the described clock readings that the capture unit of the 1st grade of controller is current recorded is sent, for each controller in 2 to n level controller, described clock alignment unit is used for according to local poor with the progression of the 1st grade of controller, the described clock readings current recorded to this locality carries out compensation of delay, and the reading of the clock of this locality after compensation of delay is read with the clock of the 1st grade of controller received compare, result tunes up or slow down local timer based on the comparison again, wherein, 2≤k≤n.
Present invention also offers the fault tolerant control method based on above-mentioned frequency converter parallel control system, comprise the following steps:
1) using described 1st grade of controller as master controller, first output interface of described master controller is placed in the state all disconnected with first input interface of this locality and the second input interface, using all the other controllers except described 1st grade of controller as from controller, each the first output interface from controller is placed in the state connecting local described first input interface; Described master controller sends status data by its first output interface, and master controller and eachly all receive described status data by the first respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter;
2) if the first input interface of described master controller cannot receive the data sent from described master controller, then the second output interface of described master controller is placed in the state all disconnected with first input interface of this locality and the second input interface, each the second output interface from controller is placed in the state connecting local described second input interface; Described master controller sends status data by its second output interface, and master controller and eachly all receive described data by the second respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
Wherein, described step 2) in, if the second input interface of described master controller cannot receive the data sent from the second output interface of described master controller, then perform step 3);
3) detection failure position, for before being positioned at abort situation and from the nearest controller of abort situation, its second output interface is placed in the state connecting local described first input interface, for after being positioned at abort situation and from the nearest controller of abort situation, its first output interface is placed in the state connecting local described second input interface, further, for master controller, its second output interface is placed in the state connecting local described second input interface; Described master controller sends status data by its first output interface, and master controller and eachly all receive described status data by the first respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
Wherein, in described frequency converter parallel control system, described each controller comprises all further: a timer, for providing clock information for this locality; And at least one capture unit, at least one capture unit described is connected with at least one in local described first input interface and described second input interface, changes the moment and the clock readings in record last change moment for catching from the high and low level of the local data of outside input;
In described fault tolerant control method, described step 1), 2), 3) in, described master controller is after often sending one group of status data, then the described clock readings that the capture unit of master controller is current recorded is sent, described each from controller all according to the local progression with described master controller, the described clock readings current recorded to this locality carries out compensation of delay, and the reading of the clock of this locality after compensation of delay read with the clock of master controller received and compare, then result tunes up or slow down the timer of this locality based on the comparison.
Wherein, in described step 1), for kth level controller, compensation of delay described clock readings current recorded for this locality is added (n+1-k) basic compensation of delay amount doubly, wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.
Wherein, described step 2) in, for kth level controller, compensation of delay described clock readings current recorded for this locality is added (k-1) basic compensation of delay amount doubly, wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.
Wherein, in described step 3), described detection failure position comprises:
31) the first output interface of master controller is utilized to send test data, and utilize the second input interface of master controller to intercept the test data of described first output interface transmission, forward detects master controller step by step to the loop from controller at different levels, until find fault;
32) the second output interface of master controller is utilized to send test data, and utilize the first input interface of master controller to intercept the test data of described second output interface transmission, oppositely detect master controller step by step to the loop from controller at different levels, until find fault;
33) if the first input interface of master controller does not receive test data in step-by-step measurement to during m level controller, second input interface does not receive test data in step-by-step measurement to during (m-1) level controller, so judges the fiber failure between (m-1) level controller and m level controller; If the first input interface of master controller does not receive test data in step-by-step measurement to m level controller, the second input interface does not receive test data in step-by-step measurement to m level controller yet, so judges m level controller failure, 2≤m≤n.
Wherein, in described step 3), suppose the fiber failure between (m-1) level controller and m level controller, so for kth level controller, if 2≤k≤m-1, then compensation of delay described clock readings current recorded for this locality is added (2n-k-1) basic compensation of delay amount doubly, if m≤k≤n, then compensation of delay described clock readings current recorded for this locality is added (n-k+1) basic compensation of delay amount doubly;
Suppose m level controller failure, so for kth level controller, if 2≤k≤m-1, then compensation of delay described clock readings current recorded for this locality is added (2n-k-3) basic compensation of delay amount doubly, if m+1≤k≤n, then compensation of delay described clock readings current recorded for this locality is added (n-k+1) basic compensation of delay amount doubly.
Compared with prior art, the present invention has following technique effect:
1, control system of the present invention is compared with the scheme of Fig. 1, significantly improves fault-tolerant ability.
2, control system of the present invention can automatic diagnosis fault, automatic Reconstruction signal transmission loop after breaking down.
3, control system of the present invention has high synchronization accuracy (can reach 10 ~ 20 nanosecond rank), and after breaking down, and control system of the present invention can not only automatic Reconstruction signal transmission loop, can also keep original synchronization accuracy.
4, control system of the present invention can close inefficacy frequency converter automatically, and then saves the energy.
Accompanying drawing explanation
The schematic diagram of a kind of frequency converter parallel-connection structure of Fig. 1 drive motor;
Fig. 2 shows the structural drawing of a kind of typical frequency converter parallel control system in prior art;
Fig. 3 shows the structural drawing of the frequency converter parallel control system of one embodiment of the invention;
Fig. 4 ~ 6 show structure and three kinds of internal connection state of the controller 1 that Fig. 3 embodiment adopts;
Fig. 7 shows the schematic diagram of the frequency converter parallel control system in one embodiment of the invention under normal operating conditions;
Fig. 8 shows the schematic diagram of the frequency converter parallel control system in one embodiment of the invention under malfunction 1;
Fig. 9 shows the schematic diagram of the frequency converter parallel control system in one embodiment of the invention under malfunction 2;
Figure 10 shows the schematic diagram of the frequency converter parallel control system in one embodiment of the invention under malfunction 3; And
Figure 11 shows the electrical block diagram of the controller in one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention done and describe further.
Fig. 3 shows frequency converter parallel control system provided according to one embodiment of present invention, comprises at least three controllers, and wherein each controller is for controlling a corresponding frequency converter.Each frequency converter parallel drive motor rotation, in the present embodiment, consistent with Fig. 1 by the mode of frequency converter parallel-connection structure drive motor, repeat no more herein.The structure of each controller is all consistent, and Fig. 4 ~ 6 show structure and three kinds of internal connection state of the controller 1 that Fig. 3 embodiment adopts.
As shown in Figure 4, controller 1 comprises: one first input interface 11, one first output interface 12, one second input interface 13, one second output interface 14, first line switch unit 15, and a first line switch unit 16.Wherein, first line switch unit 15 is for controlling described first switching of output interface 12 between three connection status, three connection status of the first output interface 12 are respectively: the state (as shown in Figure 4) connecting the first local input interface 11, connect the state (as shown in Figure 5) of the second local input interface 13, and the state (as shown in Figure 6) all disconnected with the first input interface 11 and second input interface 13 of this locality.Second circuit switching unit 16 is for controlling described second switching of output interface 14 between three connection status, three connection status of the second output interface 14 are respectively: the state (as shown in Figure 5) connecting the first local input interface 11, connect the state (as shown in Figure 4) of the second local input interface 13, and the state (as shown in Figure 6) all disconnected with the first input interface 11 and second input interface 13 of this locality.First line switch unit 15 and first line switch unit 16 can form a total line switch unit jointly, and this total line switch unit can control local signal and flow to.In total line switch unit, first line switch unit 15 and first line switch unit 16 can independent work separately.
Still with reference to figure 3, also shown is the annexation of each controller in frequency converter parallel control system, in figure, each square frame represents a controller, and the junction curve between square frame represents communication line (such as optical fiber), represents input interface and output interface in figure with triangle.For ease of describing, each controller described is designated as successively the 1st grade of controller, 2nd grade of controller, n-th grade of controller, n be at least 3 integer, wherein, first output interface of i-th grade of controller connects the first input interface of the i-th+1 grade controller, second output interface of the i-th+1 grade controller connects the second input interface of i-th grade of controller, i is integer and 1≤i≤n-1, and, first output interface of n-th grade of controller connects the first input interface of the 1st grade of controller, second output interface of the 1st grade of controller connects the second input interface of n-th grade of controller.Lay special stress on, in the input of each controller illustrated in fig. 3, output interface, is connected to and inner ring 3 is the first input or output interface, is connected to outer shroud 4 is secondary signal input or output interface.
The method of work of the frequency converter parallel control system of Fig. 3 is described below in conjunction with Fig. 7 ~ 10.
Fig. 7 shows the schematic diagram of the frequency converter parallel control system under normal operating conditions.In normal operation, using the 1st grade of controller as master controller, first output interface of master controller is placed in the state all disconnected with first input interface of this locality and the second input interface, using all the other controllers except described 1st grade of controller all as from controller, each the first output interface from controller is placed in the state connecting local described first input interface, as shown in Figure 7.In normal operation, described master controller sends master controller status data by its first output interface, and master controller and eachly all receive described master controller status data by the first respective input interface from controller.Some key time of master controller status data mainly Frequency Converter Control algorithm, eachly can calculate based on these input variables the drive waveforms that current needs export to the frequency converter of this locality from controller.Frequency Converter Control algorithm has been mature technology, and has nothing to do, so do not repeat herein with intention.Master controller and each receive master controller status data from controller after, draw corresponding drive waveforms separately and drawn drive waveforms exported to corresponding frequency converter (i.e. the frequency converter of each controller this locality).
Fig. 8 shows the schematic diagram of the frequency converter parallel control system under malfunction 1.If the first input interface of described master controller cannot receive the data sent from described master controller, represent that the inner ring of frequency converter parallel control system exists fault, now, second output interface of described master controller is placed in the state all disconnected with first input interface of this locality and the second input interface, each the second output interface from controller is placed in the state connecting local described second input interface, as shown in Figure 8.Malfunction 1 time, master controller sends master controller status data by its second output interface, and master controller and eachly all receive described master controller status data by the second respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
If frequency converter parallel control system is after setting up the connection shown in Fig. 8, second input interface of described master controller still cannot receive the data sent from the second output interface of described master controller, then illustrate that inner ring and outer shroud all break down, now need to check abort situation.As can be seen from Fig. 9, Figure 10, the abort situation that checks out may there are two kinds of situations, malfunction 2 and malfunction 3 is called in text, if the optical fiber place of abort situation between (m-1) to m level controller that check out, then judge now as malfunction 2, Fig. 9 shows the schematic diagram of the frequency converter parallel control system under malfunction 2.If the abort situation that checks out at m level controller place, i.e. the own fault of m level controller, then judge now as malfunction 3, Figure 10 shows the schematic diagram of the frequency converter parallel control system under malfunction 3.
With reference to figure 9, nonserviceable 2 times, for before being positioned at abort situation and from the nearest controller of abort situation, i.e. (m-1) level controller, its second output interface is placed in the state connecting local described first input interface, for after being positioned at abort situation and from the nearest controller of abort situation, i.e. m level controller, its first output interface is placed in the state connecting local described second input interface, and, for master controller, its second output interface is placed in the state connecting the second local input interface.Master controller sends master controller status data by its first output interface, and master controller and eachly all receive described master controller status data by the first respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
With reference to Figure 10, nonserviceable 3 times, for before being positioned at abort situation and from the nearest controller of abort situation, i.e. (m-1) level controller, its second output interface is placed in the state connecting local described first input interface, for after being positioned at abort situation and from the nearest controller of abort situation, i.e. (m+1) level controller, its first output interface is placed in the state connecting local described second input interface, and, for master controller, its second output interface is placed in the state connecting the second local input interface.Master controller sends master controller status data by its first output interface, and master controller and eachly all receive described master controller status data by the first respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
In one embodiment, frequency converter parallel control system checks abort situation by investigating step by step, comprises the following steps.
Step 1: the first output interface of master controller (i.e. the 1st grade of controller) is placed in the described state all disconnected with the first local input interface and the second input interface, is also placed in the described state all disconnected with the first local input interface and the second input interface by its second output interface.
Step 2: using the 2nd grade of controller as tested from controller, is placed in the state connecting the first local input interface by tested the second output interface from controller.First output interface of master controller sends test data, if the first input interface of master controller receives this test data in Preset Time, then master controller is normal to the circuit of the 2nd grade of controller, for convenience of describing, the current tested progression from controller is designated as i, enter step 3, if the first input interface of master controller does not receive this test data in Preset Time, then enter step 6.
Step 3: the first output interface of i-th grade of controller is placed in the state connecting the first local input interface, the second output interface is placed in the state connecting the second local input interface; Second output interface of (i+1) level controller is placed in the state connecting the first local input interface.First output interface of master controller sends test data, if the first input interface of master controller receives this test data in Preset Time, then master controller is normal to the circuit of (i+1) level controller, variable i is made to increase by 1, even i=i+1, then repeated execution of steps 3, until the first input interface of master controller can not receive this test data in Preset Time, now enters step 6.
Step 4: the first output interface of n-th grade of controller is placed in the described state connecting the second local input interface, second output interface of master controller sends test data, if the second input interface of master controller receives this test data in Preset Time, then the circuit of master controller to the n-th grade controller is normal, enter step 5, for ease of hereafter describing, the current tested progression from controller is designated as (n-i+2), this is corresponding with the tested progression from controller in step 3, if the second input interface of master controller does not receive this test data in Preset Time, then enter step 6.
Step 5: the first output interface of (n-i+2) level controller is placed in the state connecting the first local input interface, the second output interface is placed in the state connecting the second local input interface; First output interface of (n-i+1) level controller is placed in the state connecting the second local input interface.Second output interface of master controller sends test data, if the second input interface of master controller receives this test data in Preset Time, then master controller is normal to the circuit of (n-i+1) level controller, variable i is made to increase by 1, even i=i+1, then repeated execution of steps 5, until the second input interface of master controller can not receive this test data in Preset Time, now enters step 6.
Above-mentioned steps 2,3 is detections step by step of forward, and step 3,4 is reverse detections step by step, and for saving time, detection and the reverse detection step by step step by step of forward can synchronously be carried out.
Step 6: if the first input interface of master controller does not receive test data in step-by-step measurement to during m level controller, second input interface does not receive test data in step-by-step measurement to during (m-1) level controller, so judge the fiber failure between (m-1) level controller and m level controller, current state belongs to malfunction 2.If the first input interface of master controller does not receive test data in step-by-step measurement to m level controller, second input interface does not receive test data in step-by-step measurement to m level controller yet, so judge m level controller failure, current state belongs to malfunction 3.If the first input interface of master controller does not receive test data in step-by-step measurement to during m level controller, second input interface does not receive test data in step-by-step measurement to during (m+1) or more level controller, then exceed the error tolerance of the control system of the present embodiment, control system report fault also quits work.
Further, if the synchronization accuracy of frequency converter parallel-connection structure is not enough, current spike and circulation between frequency converter may be caused, serious current spike directly can damage power device, it is uneven that circulation then makes transducer power in parallel distribute, and causes parallel drive ability to be restricted and accelerating part frequency converter aging.Therefore, frequency converter parallel-connection structure often requires high synchronization accuracy.
According to one embodiment of present invention, provide a kind of frequency converter parallel control system with high synchronization accuracy, it, on the basis of the frequency converter parallel control system of previous embodiment, each controller adds the parts that some are new.Particularly, in the present embodiment, each controller comprises all further: a timer, for providing clock information for this locality; One capture unit, it is connected with at least one in local described first input interface and described second input interface, changes the moment and the clock readings in record last change moment for catching from the high and low level of the local data of outside input; And a clock alignment unit.This frequency converter parallel control system in normal operation, level change each time all can impel capture unit record present clock reading, so after master controller distributes one group of data, all controllers all can record the clock readings in last level change moment.Like this, after master controller sends one group of master controller status data, then the described clock readings that the capture unit of master controller is current recorded is sent again, for each controller in 2 to n level controller, clock alignment unit is according to local poor with the progression of the 1st grade of controller, the described clock readings current recorded to this locality carries out compensation of delay, and compared by the clock readings of the clock readings of this locality after compensation of delay with the 1st grade of controller received, then result tunes up or slow down local timer based on the comparison.
Further, according to one embodiment of present invention, in frequency converter parallel control system, each controller comprises a control module all further, built-in timer and buffer unit in control module.As shown in figure 11, control module comprises following interface: the first Signal reception interface RX1 and the first input signal that connect the first input interface 11 catch interface Cap1, connect the first signal transmission interface TX1 of the first output interface 12, the secondary signal receiving interface RX2 and the second input signal that connect the second input interface 13 catch interface Cap2, connect the secondary signal transmission interface TX2 of the second output interface 14.Wherein, the master controller status data that first Signal reception interface RX1, secondary signal receiving interface RX2 transmit for receiving previous stage controller, first input signal catches interface Cap1, the second input signal catches interface Cap2 for catching the moment of the low and high level change (can catch according to signal rising edge or negative edge) of previous stage equipment derived signals, signal capture interface and buffer unit combine, the function of the capture unit described in can realizing above.Have the first input signal in the present embodiment to catch interface Cap1 and the second input signal and catch interface Cap2 two signal capture interfaces, they are combined with buffer unit respectively, can form two above described in capture unit.
Further, first, second input interface is light signal input port, and first, second output interface is light signal delivery outlet.Built in light receiver in light signal input port, can be converted to electric signal received light signal.Built in light transmitter in light signal delivery outlet, can be converted to light signal electric signal.Optical receiver and optical transmitting set form a pair optocoupler.Inner from controller, optical receiver is connected by circuit with optical transmitting set, forms signal line.
Still with reference to Figure 11, controller 1 also comprises three triple gate 15a further, 15b, 15c, and these three triple gate 15a, 15b, 15c form previously described first line switch unit 15.Wherein, triple gate 15a is for controlling the break-make of signal line between the first output interface 12 and the first input interface 11, triple gate 15b is for controlling the break-make of signal line between the first output interface 12 and the first signal transmission interface TX1, and triple gate 15c is for controlling the break-make of signal line between the first output interface 12 and the second input interface 13.The enable stitch I/O1 by control module of two triple gates 15a, 15b controls, and in these two triple gates 15a, 15b, one is that high level is enable, and another is that low level is enable, is conducive to the I/O stitch number saving control module like this.3rd the enable stitch I/O3 by control module of triple gate controls.So just can make, the first output interface 12 can only be communicated with in the first input interface 11, second input interface 13 and the first signal transmission interface TX1 at synchronization, thus realizes kind of the connection status of three shown in Fig. 4 ~ 6.
Similarly, controller 1 also comprises three triple gate 16a further, 16b, 16c, these three triple gate 16a, and 16b, 16c form previously described second circuit switching unit 16.Wherein, triple gate 16a is for controlling the break-make of signal line between the second output interface 14 and the second input interface 13, triple gate 16b is for controlling the break-make of signal line between the second output interface 14 and secondary signal transmission interface TX2, and triple gate 16c is for controlling the break-make of signal line between the second output interface 14 and the first input interface 11.The enable stitch I/O2 by control module of two triple gates 16a, 16b controls, and in these two triple gates 16a, 16b, one is that high level is enable, and another is that low level is enable, is conducive to the I/O stitch number saving control module like this.3rd the enable stitch I/O4 by control module of triple gate 16c controls.So just can make, the second output interface 14 can only be communicated with in the first input interface 11, second input interface 13 and secondary signal transmission interface TX2 at synchronization, thus realizes kind of the connection status of three shown in Fig. 4 ~ 6.
The control system of above-described embodiment realizes the signal transmission between equipment based on serial structure, optical fiber (or other cable) number needed for each equipment of this anatomical connectivity is less, length is shorter, I/O interface needed for master controller is also relatively less, therefore there is saving material, save the advantage of equipment I/O interface.Meanwhile, above-mentioned control system has excellent fault-tolerant ability, and its inner ring, outer shroud can independent operatings separately, when inner ring, outer shroud simultaneous faults, can also under the control of master controller, carry out self-inspection and re-establish signal loop.
As mentioned before, after master controller distributes one group of data, all controllers all can record the clock readings in last level change moment.Like this, after master controller sends one group of master controller status data, then the described clock readings that the capture unit of master controller is current recorded is sent again, for each controller in 2 to n level controller, clock alignment unit is according to local poor with the progression of the 1st grade of controller, the described clock readings current recorded to this locality carries out compensation of delay, and compared by the clock readings of the clock readings of this locality after compensation of delay with the 1st grade of controller received, then result tunes up or slow down local timer based on the comparison.For kth level controller, if the clock readings of this locality after compensation of delay is completely the same with the clock readings of the 1st grade of controller received, then be considered as this kth level controller and master controller Complete Synchronization, if not quite identical, then need correspondingly to tune up or slow down local timer.
In one embodiment, frequency converter parallel control system in normal operation, for kth level controller, its compensation of delay described clock readings current recorded for this locality is added (n+1-k) basic compensation of delay amount doubly, wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time, and it is the hardware time delay in signals transmission.
When tuning up or slow down local timer, usually also having the software delays of several processor clock cycle, in a preferred embodiment, when replacing the old count value of timer with new count value, needing software delays to take into account.Such as, when counter should tune up t, then new count value is t
0+ t+c, wherein, t
0for the old count value of timer, c is the software delays of timer calibration.Software delays performs from code, and its size depends on dominant frequency and the instruction execution cycle of compensation complexity, compute chip (as DSP), compensation (such as t
0+ t+c) and after compute chip determines, the software delays c of timer calibration also just determines.
In one embodiment, frequency converter parallel control system is nonserviceabled 1 time, for kth level controller, compensation of delay described clock readings current recorded for this locality is added (k-1) basic compensation of delay amount doubly, wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.In a preferred embodiment, malfunction 1 time, when replacing the old count value of timer with new count value, needing the software delays c by timer is calibrated to take into account equally, repeating no more herein.
In one embodiment, frequency converter parallel control system is nonserviceabled 2 times, suppose the fiber failure between (m-1) level controller and m level controller, so for kth level controller, if 2≤k≤m-1, then compensation of delay described clock readings current recorded for this locality is added (2n-k-1) basic compensation of delay amount doubly, if m≤k≤n, then compensation of delay described clock readings current recorded for this locality is added (n-k+1) basic compensation of delay amount doubly.Wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.In a preferred embodiment, malfunction 2 times, when replacing the old count value of timer with new count value, needing the software delays c by timer is calibrated to take into account equally, repeating no more herein.
In one embodiment, frequency converter parallel control system is nonserviceabled 3 times, suppose m level controller failure, so for kth level controller, if 2≤k≤m-1, then compensation of delay described clock readings current recorded for this locality is added (2n-k-3) basic compensation of delay amount doubly, if m+1≤k≤n, then compensation of delay described clock readings current recorded for this locality is added (n-k+1) basic compensation of delay amount doubly.Wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.In a preferred embodiment, malfunction 3 times, when replacing the old count value of timer with new count value, needing the software delays c by timer is calibrated to take into account equally, repeating no more herein.
Above-described embodiment not only has redundancy fault-tolerant ability, can also all ensure high synchronization accuracy under various malfunction again.During the actual use of above-mentioned frequency converter parallel control system, synchronization accuracy can reach for 10 ~ 20 nanoseconds, contributed to supporting that the frequency converter of larger quantity realizes in parallel, thus significantly improved its motor driving force.
Number " one " stated herein is also not intended to logarithm amount and limits, when with instruction of the present invention without prejudice to also can refer to multiple.
The foregoing is only the schematic embodiment of the present invention, and be not used to limit scope of the present invention.Any those skilled in the art, the equivalent variations done under the prerequisite not departing from design of the present invention and principle, amendment and combination, all should belong to the scope of protection of the invention.
Claims (9)
1. a frequency converter parallel control system, comprises at least three controllers, and each controller in described at least three controllers is for controlling frequency converter corresponding in frequency converter parallel-connection structure one;
It is characterized in that, described each controller includes: one first input interface, one first output interface, one second input interface, one second output interface, and a circuit switching unit, described circuit switching unit switches between three connection status for controlling described first output interface, three connection status of described first output interface are: the state connecting local described first input interface, connect the state of local described second input interface, and the state all to disconnect with the first input interface and second input interface of this locality, described circuit switching unit also switches between three connection status for controlling described second output interface, three connection status of described second output interface are: the state connecting local described first input interface, connect the state of local described second input interface, and the state all to disconnect with the first input interface and second input interface of this locality,
Described at least three controllers connect in the following manner: described at least three controllers are designated as successively the 1st grade of controller, 2nd grade of controller, n-th grade of controller, n be at least 3 integer, wherein, first output interface of i-th grade of controller connects the first input interface of the i-th+1 grade controller, second output interface of the i-th+1 grade controller connects the second input interface of i-th grade of controller, i is integer and 1≤i≤n-1, first output interface of n-th grade of controller connects the first input interface of the 1st grade of controller, second output interface of the 1st grade of controller connects the second input interface of n-th grade of controller.
2. frequency converter parallel control system according to claim 1, is characterized in that, described each controller comprises all further: a timer, for providing clock information for this locality;
At least one capture unit, at least one capture unit described is connected with at least one in local described first input interface and described second input interface, changes the moment and the clock readings in record last change moment for catching from the high and low level of the local data of outside input; And
One clock alignment unit;
Described 1st grade of controller is after often sending one group of status data, then the described clock readings that the capture unit of the 1st grade of controller is current recorded is sent, for each controller in 2 to n level controller, described clock alignment unit is used for according to local poor with the progression of the 1st grade of controller, the described clock readings current recorded to this locality carries out compensation of delay, and the reading of the clock of this locality after compensation of delay is read with the clock of the 1st grade of controller received compare, result tunes up or slow down local timer based on the comparison again, wherein, 2≤k≤n.
3., based on a fault tolerant control method for frequency converter parallel control system according to claim 1, it is characterized in that, comprise the following steps:
1) using described 1st grade of controller as master controller, first output interface of described master controller is placed in the state all disconnected with first input interface of this locality and the second input interface, using all the other controllers except described 1st grade of controller as from controller, each the first output interface from controller is placed in the state connecting local described first input interface; Described master controller sends status data by its first output interface, and master controller and eachly all receive described status data by the first respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter;
2) if the first input interface of described master controller cannot receive the data sent from described master controller, then the second output interface of described master controller is placed in the state all disconnected with first input interface of this locality and the second input interface, each the second output interface from controller is placed in the state connecting local described second input interface; Described master controller sends status data by its second output interface, and master controller and eachly all receive described data by the second respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
4. fault tolerant control method according to claim 3, is characterized in that, described step 2) in, if the second input interface of described master controller cannot receive the data sent from the second output interface of described master controller, then perform step 3);
3) detection failure position, for before being positioned at abort situation and from the nearest controller of abort situation, its second output interface is placed in the state connecting local described first input interface, for after being positioned at abort situation and from the nearest controller of abort situation, its first output interface is placed in the state connecting local described second input interface, further, for master controller, its second output interface is placed in the state connecting local described second input interface; Described master controller sends status data by its first output interface, and master controller and eachly all receive described status data by the first respective input interface from controller, and export corresponding drive waveforms to corresponding frequency converter.
5. fault tolerant control method according to claim 4, is characterized in that, in described frequency converter parallel control system, described each controller comprises all further: a timer, for providing clock information for this locality; And at least one capture unit, at least one capture unit described is connected with at least one in local described first input interface and described second input interface, changes the moment and the clock readings in record last change moment for catching from the high and low level of the local data of outside input;
In described fault tolerant control method, described step 1), 2), 3) in, described master controller is after often sending one group of status data, then the described clock readings that the capture unit of master controller is current recorded is sent, described each from controller all according to the local progression with described master controller, the described clock readings current recorded to this locality carries out compensation of delay, and the reading of the clock of this locality after compensation of delay read with the clock of master controller received and compare, then result tunes up or slow down the timer of this locality based on the comparison.
6. fault tolerant control method according to claim 5, it is characterized in that, in described step 1), for kth level controller, compensation of delay described clock readings current recorded for this locality is added (n+1-k) basic compensation of delay amount doubly, wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.
7. fault tolerant control method according to claim 5, it is characterized in that, described step 2) in, for kth level controller, compensation of delay described clock readings current recorded for this locality is added (k-1) basic compensation of delay amount doubly, wherein, 2≤k≤n, described basic compensation of delay amount is signal by a mean transit delay amount during controller one time.
8. fault tolerant control method according to claim 5, is characterized in that, in described step 3), described detection failure position comprises:
31) the first output interface of master controller is utilized to send test data, and utilize the second input interface of master controller to intercept the test data of described first output interface transmission, forward detects master controller step by step to the loop from controller at different levels, until find fault;
32) the second output interface of master controller is utilized to send test data, and utilize the first input interface of master controller to intercept the test data of described second output interface transmission, oppositely detect master controller step by step to the loop from controller at different levels, until find fault;
33) if the first input interface of master controller does not receive test data in step-by-step measurement to during m level controller, second input interface does not receive test data in step-by-step measurement to during (m-1) level controller, so judges the fiber failure between (m-1) level controller and m level controller; If the first input interface of master controller does not receive test data in step-by-step measurement to m level controller, the second input interface does not receive test data in step-by-step measurement to m level controller yet, so judges m level controller failure, 2≤m≤n.
9. fault tolerant control method according to claim 8, it is characterized in that, in described step 3), suppose the fiber failure between (m-1) level controller and m level controller, so for kth level controller, if 2≤k≤m-1, then compensation of delay described clock readings current recorded for this locality is added (2n-k-1) basic compensation of delay amount doubly, if m≤k≤n, then compensation of delay described clock readings current recorded for this locality is added (n-k+1) basic compensation of delay amount doubly;
Suppose m level controller failure, so for kth level controller, if 2≤k≤m-1, then compensation of delay described clock readings current recorded for this locality is added (2n-k-3) basic compensation of delay amount doubly, if m+1≤k≤n, then compensation of delay described clock readings current recorded for this locality is added (n-k+1) basic compensation of delay amount doubly.
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Effective date of registration: 20190425 Address after: Dublin, Ireland Patentee after: Eaton Intelligent Power Co.,Ltd. Address before: Ohio Patentee before: Eaton Corp. |