CN115700904A - Method of coupling semiconductor dies and corresponding semiconductor device - Google Patents

Abstract

The present disclosure relates to a method of coupling semiconductor dies and a corresponding semiconductor device. A Laser Direct Structuring (LDS) material package is molded onto a substrate having a first semiconductor die and a second semiconductor die disposed thereon. Laser beam energy is applied to a surface of the LDS material package to construct therein die-to-die lines extending through the LDS material to die vias of the first and second semiconductor dies and at the surface of the LDS material between the die vias. A Laser Induced Forward Transfer (LIFT) process is applied to transfer the conductive material to the die vias and the die-to-die lines extending between the die vias. The electroless layer of conductive material grown over the die vias and die-to-die lines helps to improve the adhesion of the conductive material transferred via the LIFT process.

Description

Method of coupling semiconductor dies and corresponding semiconductor device

CROSS-APPLICATION OF RELATED APPLICATIONS

The present application claims priority from italian patent application No. 102021000020540, filed on 30/7/2021, the content of which is incorporated herein by reference in its entirety to the maximum extent allowed by law.

Technical Field

This specification relates to semiconductor devices.

One or more embodiments may be applied to a semiconductor device including a die-to-die connection.

A System In Package (SiP) device comprising a plurality of circuits integrated in one or more chip-carrier packages may be an example of such a device.

Background

For example, various types of semiconductor devices, such as power devices, may include die-to-die coupling.

Devices where it is desired that a power semiconductor chip or die (e.g., gallium nitride or gallium nitride) is connected to a driver chip or die fabricated using BCD (bipolar-CMOS-DMOS) technology may be an example of such a case.

Laser Direct Structuring (LDS) technology has recently been proposed to replace conventional wire bonding that provides die-to-wire electrical connections in semiconductor devices.

In laser direct structuring techniques currently implemented, after laser beam patterning (activation) of LDS materials, the conductivity of structures such as vias and traces is facilitated by electroless metallization and plating to reach metallization thicknesses of tens of microns for metal materials such as copper.

A problem that arises when attempting to apply LDS techniques to die-to-die coupling is that the associated conductive patterns are electrically floating nodes.

Thus, the anticipated use of electroplating to facilitate sufficient conductivity of conductive structures (vias and/or lines or traces) constructed via LDS techniques hinders the extension of the use of LDS techniques from die-to-lead coupling to die-to-die coupling.

There is a need in the art to contribute to adequately addressing such problems.

Disclosure of Invention

One or more embodiments relate to a method.

One or more embodiments relate to a corresponding semiconductor device. A semiconductor device such as a power device comprising a plurality of mutually coupled semiconductor chips or dies may be an example of such a device.

One or more embodiments combine laser direct structuring (including electroplating) with Laser Induced Forward Transfer (LIFT) techniques.

LIFT techniques may be used to complete the growth (filling) of vias/traces in the die-to-die interconnect.

One or more embodiments may benefit from the fact that: the electroless underlayer, as currently used in LDS technology, promotes adhesion of LIFT materials to (LDS) molding compounds.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is an example of a possible application of Laser Direct Structuring (LDS) technology to the fabrication of semiconductor devices;

fig. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present description;

FIG. 3 is an exemplary flow chart of possible steps in an embodiment of the present description;

FIGS. 4A and 4B schematically show the results of certain steps in the flow chart of FIG. 3;

FIG. 5 is a schematic illustration of a mechanical layout for implementing embodiments of the present description; and

FIG. 6 is a further example of possible results in a method according to embodiments of the present description.

Detailed Description

Corresponding numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated.

The drawings are drawn for clarity of illustrating relevant aspects of the embodiments and are not necessarily to scale.

The edges of a feature drawn in a drawing do not necessarily represent the end of the range of the feature.

In the following description, numerous specific details are shown to provide a thorough understanding of various examples in accordance with the described embodiments. Embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the embodiments.

Reference to "an embodiment" or "one embodiment" within the framework of the specification is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment," "in one embodiment," and the like that may be present in various points of the specification do not necessarily refer to the same embodiment with certainty. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The headings/references used herein are provided for convenience only and thus do not define the scope of protection or the scope of the embodiments.

Fig. 1 illustrates a possible application of Laser Direct Structuring (LDS) technology to provide die-to-lead coupling in the assembly flow of multiple semiconductor devices, which are manufactured simultaneously and ultimately separated into individual devices via a singulation step.

Fig. 1 relates to a (single) device including a lead frame having a plurality of die pads 12A (e.g., two die pads), on which die pads 12A respective semiconductor integrated circuit chips or dies 14 are mounted (e.g., attached via die-attach material 140) with lead arrays 12B, the lead arrays 12B surrounding the die pads 12A and the semiconductor chips or dies 14.

The name "lead frame" (or "lead frame") is currently used (see, for example, the united states patent and trademark office's USPC incorporated vocabulary) to denote a metal frame that provides support for an integrated circuit chip or die, as well as electrical leads that interconnect the die or integrated circuit in the chip to other components or contacts.

In essence, the lead frame comprises an array of conductive structures (leads) extending inwardly from a contour location in the direction of the semiconductor chip or die, thereby forming an array of conductive structures from a die pad configured to have at least one semiconductor chip or die attached thereto. This may be by conventional means such as a die attach adhesive (e.g., a Die Attach Film (DAF)).

In fig. 1, two die pads 12A are shown to which respective dies or chips 14 are attached (throughout this specification, "die/dies" and "chip/chips" are used synonymously).

In various embodiments, multiple chips 14 may be mounted on a single die pad 12A: for example, instead of the different elements shown in fig. 1, two die pads 12A may be joined to form a single die pad with two chips mounted thereon as shown in fig. 2.

Laser Direct Structuring (LDS), also commonly referred to as Direct Copper Interconnect (DCI) technology, is a laser-based processing technology now widely used in various industries of the industrial and consumer electronics markets, such as for high performance antenna integration, where antenna designs can be formed directly on molded plastic parts. In one exemplary process, the molded part may be produced using commercially available resins that include additives suitable for LDS processing; a wide range of resins (such as polymer resins like PC, PC/ABS, LCP) can currently be used for this purpose.

In LDS, a laser beam may be used to transfer the desired conductive pattern onto the plastic molding, which may then be metallized (e.g., by electroless plating and electroplating with copper or other metal) to complete the desired conductive pattern.

Documents such as U.S. patent application publication nos. 2018/0342453, 2019/0115287, 2020/0203264, 2020/0321274, 2021/0050226, 2021/0050299, or 2021/0183748 (all of which are incorporated herein by reference) are examples of possibilities for applying LDS techniques in the manufacture of semiconductor devices. For example, LDS technology facilitates replacing wires, clips or ribbons with wires/vias created by laser beam processing of LDS material and subsequent metallization (e.g., growing metal such as copper by an electroplating process).

Still referring to fig. 1, lds material package 16 may be molded onto lead frames 12A, 12B, lead frames 12A, 12B having semiconductor chip or die 14 mounted thereon.

Conductive die-to-lead coupling structures may be provided in LDS material 16 (e.g., in a manner known per se, see the previously referenced published application).

As shown in fig. 1, the die-to-lead coupling structure includes: a first via 181, a second via 182, and a conductive line or trace (trace) 183.

First vias 181 extend through LDS package 16 between a top (front) surface 16A of the package ( opposite lead frames 12A, 12B) and conductive pads (not visible for scale reasons) at the front or top surface of chip or die 14.

Second through holes 182 extend through LDS package 16 between top (front) surface 16A of the package and corresponding leads 12B in the leadframe.

A conductive line or trace (trace) 183 extends at the front or top surface 16A of the package 16 and electrically couples selected ones of the first vias 181 with selected ones of the second vias 182 to provide a desired die-to-lead electrical connection pattern between the chip or die 14 and the leads 12B.

Providing electrically conductive die to lead structures 181, 182, and 183 essentially comprises constructing structures (e.g., drilling holes therein at desired locations for vias 181, 182) in LDS material 16 followed by growing an electrically conductive material (e.g., a metal such as copper) at locations activated (constructed) by laser beam energy at a front or top surface 16A of LDS material 16.

Further details regarding the processing discussed above may be derived from, for example, the published applications referenced in the foregoing.

Extending the use of LDS processing as discussed above to produce die-to-die coupled structures faces issues related to the nature of the structure.

The die-to-die coupling structure as indicated at 200 in fig. 1 should desirably include: a conductive via 201 and a conductive line or trace line 202.

Conductive vias 201 extend through LDS package 16 between a top (front) surface 16A of the package and die pads (not visible for scale reasons) at a top or front surface of one and the other of two chips or dies 14, the two chips or dies 14 being connected to each other.

Conductive lines or traces 202 bridge between the first vias 201 at the front or top surface 16A of the package 16 to complete the desired die-to-die coupling pattern.

Laser beam shaping (also referred to as "activation") of vias 201 and lines or traces 202 in LDS material package 16 may be performed in the same manner as shaping vias 181, 182 and lines or traces 183, vias 181, 182 and lines or traces 183 being used to provide die-to-lead coupling structures as previously discussed.

A critical aspect arises from growing a conductive material, such as a metal (e.g., by electroplating), at the constructed locations to provide the desired conductivity-as in the case of die-to-lead coupling structures.

Growing conductive materials currently involves (in addition to electroless plating) electroplating, which is based on the reduction of the cations of the metal to be deposited contained in an electrolyte "bath" EB to a metallic material (e.g. copper).

Cations, such as Cu2+ cations, are reduced to metallic copper at the cathode C by taking electrons e from the current, as shown in fig. 1, where a denotes the anode of the electrolyte containing the metal cations to be deposited.

For example, the electrolyte EB may comprise (in case of copper deposition) Cu2+ cations and SO2 "4 anions (as otherwise known to the person skilled in the art).

This process, i.e., the reduction of Cu2+ cations to metallic copper at the anode to create a conductive path (and thus, the desired growth of a conductive metal such as copper at the coupling structure 200) includes obtaining electrons e from the current flowing through the cathode C represented by the lead 12B, for example. This current simply cannot flow in the arrangement shown in fig. 1: here, the structure 200 is electrically isolated from the leadframe (by the chip 14) so that Cu2+ cannot be reduced to metal (copper).

It should be noted that this problem can be solved, at least in principle, by employing LDS techniques to provide die-to-lead conductive structures 181, 182, 183, while other techniques are used to provide die-to-die coupling as illustrated at 200 in fig. 1.

Conventional wire bonding may represent a first candidate to account for die-to-die coupling. The undesired high impedance path and/or the stress applied on the device joint represent (disadvantageous) factors to be considered.

Providing the die-to-die coupling structure 200 by means of a conductive glue may be another considered option. It should be noted that filling vias configured in LDS material 16 with conductive glue may become impractical due to the glue viscosity.

Creating a victim path within a structure such as that shown in fig. 1 is yet another contemplated option. Also, this approach does not obviate drawbacks such as undesirable antenna effects and possibly resulting design limitations (especially in the case of devices comprising a large number of input/output connections).

One or more embodiments contemplate a Laser Induced Forward Transfer (LIFT) process instead of an (electro) plating process for growing metal material on vias and lines (trace lines) configured in LDS material 16.

LIFT processing is a deposition process that employs material transfer from a donor ribbon to a receptor substrate by laser pulses.

The designation LIFT applies to a process (known per se to those skilled in the art) that facilitates the transfer of material from a donor ribbon or sheet (see 300, 302 in fig. 5) to a recipient substrate (here LDS material) by laser pulses.

General information on LIFT processing can be found, for example, in p.serra, et al, "Laser-Induced Forward Transfer: fundamentals and Applications", advanced Materials Technologies/Volume 4, issue 1 (incorporated herein by reference).

Employing the LIFT process facilitates increased design flexibility in die-to-die coupling and also facilitates the use of copper as well as silver materials for filling vias and traces.

Fig. 2 (in which components or elements similar to those already discussed in connection with fig. 1 are indicated with the same reference numerals and corresponding detailed description will not be repeated) is an example of the possibility of providing a die-to-die coupling structure 200 using LIFT technology.

Note that in fig. 2, two semiconductor chips or dies 14 are shown mounted on the same die pad 12A, as an alternative to being mounted on separate different die pads as shown in fig. 1.

Further, fig. 2 shows the possibility of molding another protective package 20 (which may be a non-LDS material such as a conventional epoxy molding compound) on the front or top surface 16A of the "first" LDS material package 16, the protective package 20 extending on top of the vias 181, 182 and 201 and on the lines or traces 183 and 202.

The flow chart of fig. 3 is exemplary steps that facilitate providing a semiconductor device having the structure shown in the cross-sectional view of fig. 2.

It should be noted that the sequence of steps shown in the flowchart of fig. 3 is merely exemplary and not mandatory, for example: some of the steps illustrated in fig. 3 may be omitted and/or replaced by other steps; additional steps may be included in the sequence (not shown in fig. 3 for simplicity); and/or certain steps may be performed simultaneously, not subsequently, and/or in a different order than that shown by way of example in fig. 3.

Moreover, it should be understood that the LDS processing laser (to "build" or activate LDS material 16) and the LIFT processing laser (to transfer the metallic material to fill vias 201 and traces 202: see LB in FIG. 5), although possibly included in the same workstation, are typically different laser sources.

Block 100 in the flow chart of fig. 3 is an exemplary step of providing attachment (via a die-attach material such as 140) of the lead frames 12A, 12B and the chip or die 14 thereon.

Block 101 in the flow chart of fig. 3 is an example of molding and consolidating (e.g., via thermal curing) LDS package 16 onto lead frames 12A, 12B with chips or dies 14 attached thereon.

In the step of block 102, laser beam activation energy is applied to structures in LDS material 16, vias 181, 182 (die-to-lead coupling) and 201 (die-to-die coupling) and lines or traces 183 (die-to-lead coupling) and 202 (die-to-die coupling or couplings: in fact multiple such couplings may be provided).

Block 103 in the flow chart of fig. 3 is an example of electroless plating of an electroplated metallization material (e.g., copper) to complete the vias 181, 182 and lines or traces 183 in the die-to-lead coupling.

It should be further noted that: electroless plating will also form a seed layer(s) on die-to-die coupling(s) 200, i.e., on vias 201 and lines or traces 202 (see layer 200A of fig. 4A); and electroplating performed at die-to-lead connections (i.e., at vias 181, 182 and traces 183) cannot be performed at vias 201 and lines or traces 202, as long as no electrical ground connection is available at these locations.

Block 104 in the flow chart of fig. 3 is an example of the possibility to grow (fill or print) further conductive material (metal, such as copper or silver) as well as vias 201 and lines or traces 202 via LIFT process.

In the examples considered herein, electroplating (which cannot be performed at vias 201 and lines or traces 202 due to lack of ground connections) is thus "replaced" at vias 201 and lines or traces 202 by LIFT processing for metal deposition.

Note that layer 200A formed at via 201 and line or trace 202 (also) by electroless plating in step 103 promotes adhesion of the subsequent LIFT metallization in step 104 and thus improves robustness.

Such a layer is indicated by 200A in both fig. 4A and 4B. It should be noted that the provision of this layer 200A is optional, but does provide advantages in promoting adhesion.

Specifically, fig. 4A illustrates the act of filling via 201 and line(s) 202 (with "electroless" layer 200A pre-formed thereon) by LIFT processing.

Block 105 in the flow chart of fig. 3 represents an in-line (in-line) sintering of the LIFT-printed metallic material to complete the vias 201 and lines or traces 202 in the die-to-die coupling(s) 200: see fig. 4B.

Block 106 in the flow chart of fig. 3 represents a second (e.g., non-LDS) package 20 molded onto front or top surface 16A.

Finally, blocks 107 and 108 represent plating (in view of soldering to substrate S: see fig. 2) and singulation (singulation) of the back or bottom surface to produce individual semiconductor devices 10.

Fig. 4A and 4B schematically represent a process of "printing" a (metallic) material such as copper or silver by a LIFT process to fill vias 201 and traces 202 configured at the front or top surface 16A of the LDS material.

As can be seen in fig. 4A and 4B, the metallization of the die-to-die coupling structure 200 (e.g., 201, 202) includes a bilayer of electroless metal (see layer 200A) and LIFT metal.

The bilayer structure (first conductive material 200A electrolessly grown on LDS material 16 with the second conductive material transferred thereon by LIFT processing) is clearly identifiable even after sintering.

As described above, various examples may benefit from the fact that electroless underlayers (such as 200A in fig. 4A and 4B) promote LIFT material adhesion to (LDS) molding compounds.

A similar two-layer structure (again, a first conductive material electrolessly grown on LDS material 16 having a second conductive material electroplated thereon, as is conventional in LDS processing) is also identifiable at die-to- lead coupling structures 181, 182, 183.

As previously discussed in connection with block 103 of the flow diagram of fig. 3, a conductive material (e.g., copper) may be electrolessly grown (e.g., in the same step) at both the die-to-die coupling structures 200 (e.g., 201, 202) and the die-to- lead coupling structures 181, 182, 183.

The (further) conductive material may then: is electroplated (as is conventional in LDS processing) onto the conductive material grown electrolessly at the die-to- lead coupling structures 181, 182, 183; and transferred by LIFT onto a conductive material grown electrolessly at die-to-die coupling structures 200 (e.g., 201, 202) that are not suitable for conventional electroplating.

Sintering at the die-to-die coupling structure 200 (performed as otherwise known to those skilled in the art) is advantageous because it consolidates the conductive material stretched (filled) in the vias 201 and lines or traces 202. Accordingly, one or more embodiments may utilize sintered materials to provide high conductivity electrical connections.

As discussed previously (and conventional methods in the art), LIFT processing involves the use of a donor film (e.g., a polyethylene film coated with a thin metal layer).

Such donor film may be provided in the form of a donor tape 300, the donor tape 300 being coated with a material 302 (to fill the vias 201 and lines or traces 202 in the present case) coated thereon in a roll-to-roll coating process (between the two rolls R1, R2). This provides the advantage of facilitating the handling of multiple materials simultaneously. The thickness of the coating 302 determines the height of the final layer.

Laser beam energy as shown at LB in fig. 5 is then applied to the coated donor tape 300, 302 (from the uncoated side), at those locations generally indicated at 304 in fig. 5, where conductive material, such as copper or silver, will be transferred onto LDS material 16 to fill metal into the vias 201 by laser beam forming (activation) and onto the lines or traces 202 previously constructed therein.

Fig. 6 is an exemplary fact that the transfer of the fill material from the LIFT-treated donor tape may also include the formation of upstanding structures 400 at the front or top surface of die 14, the thickness of upstanding structures 400 being such that the distal (upper) end of the material is visible at the surface of LDS material 16. These upright structures can be used as a reference in LDS processing, as disclosed in U.S. patent application Ser. No. 17/752,503 (corresponding to Italian patent application 102021000014198), filed 24/5/2022, which is incorporated herein by reference.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the embodiments.

The claims are an integral part of the technical teaching provided herein with respect to the embodiments.

The scope of protection is determined by the appended claims.

Claims (17)

1. A method, comprising:

disposing a first semiconductor die and a second semiconductor die on a substrate;

molding a Laser Direct Structuring (LDS) material package onto the first semiconductor die and the second semiconductor die, the first semiconductor die and the second semiconductor die being disposed on the substrate, the LDS material package having a surface opposite the substrate;

providing at least one die-to-die coupling structure that is electrically conductive between the first semiconductor die and the second semiconductor die, the at least one die-to-die coupling structure comprising: a die via extending through the LDS material between the surface of the LDS material package opposite the substrate and the first and second semiconductor dies; and a die-to-die line extending at the surface of the LDS material package opposite the substrate and coupling the die via;

wherein providing the at least one die-to-die coupling structure that is electrically conductive comprises:

applying laser beam energy to selected locations of the surface of the LDS material package opposite the substrate to laser activate and construct the die vias and the die-to-die lines in the LDS material package; and

applying a Laser Induced Forward Transfer (LIFT) process to transfer conductive material onto the die vias and onto the die-to-die lines extending between the die vias.

2. The method of claim 1, further comprising: the sintering transfers to the conductive material over the die vias and over the die-to-die lines extending between the die vias.

3. The method of claim 1, in which applying LIFT processing to the die vias and the die-to-die lines extending between the die vias transfers a metallic material made of copper or silver onto the die vias and the die-to-die lines extending between the die vias.

4. The method of claim 1, further comprising: growing a conductive layer electrolessly onto the die via and onto the die-to-die line after applying laser beam energy and before applying a LIFT process; wherein the conductive material transferred onto the die vias and onto the die-to-die lines extending between the die vias is applied to the conductive layer.

5. The method of claim 1, wherein arranging comprises: disposing the first semiconductor die and the second semiconductor die on at least one die pad in the substrate, the substrate comprising an array of conductive leads surrounding the at least one die pad,

and the method further comprises: applying LDS processing to the LDS material package to provide a die-to-lead conductive structure that couples the first semiconductor die and the second semiconductor die with selected ones of the conductive leads in the array of conductive leads, wherein the die-to-lead conductive structure comprises:

a first via extending through the LDS material between the surface of the LDS material package opposite the substrate and one and the other of the first and second semiconductor dies;

a second via extending through the LDS material between the surface of the LDS material package opposite the substrate and a selected one of the conductive leads in the array of conductive leads; and

a conductive line extending between selected ones of the first vias and selected ones of the second vias at the surface of the LDS material package opposite the substrate.

6. The method of claim 5, further comprising: after applying the laser beam energy and before applying the LIFT process:

electrolessly growing a layer of conductive material onto the die via, onto the die-to-die line, onto the first via, onto the second via, and onto the conductive line; and

then electroplating a conductive material onto the electrolessly grown layer of conductive material at the first via, the second via, and the electrical lead;

wherein the conductive material transferred onto the die vias and onto the die-to-die lines extending between the die vias is applied to the layer of conductive material grown by electroless plating.

7. A device, comprising:

a substrate;

a first semiconductor die disposed on the substrate;

a second semiconductor die disposed on the substrate;

a Laser Direct Structuring (LDS) material package molded onto the first and second semiconductor dies disposed on the substrate, the LDS material package having a surface opposite the substrate;

at least one conductive die-to-die coupling structure between the first semiconductor die and the second semiconductor die, the at least one die-to-die coupling structure comprising:

a die via laser configured to pass through the LDS material between the surface of the LDS material package opposite the substrate and the first and second semiconductor dies;

a die-to-die line laser configured at the surface of the LDS material package opposite the substrate and coupled with the die vias; and

a conductive laser induced forward transfer LIFT material on the die vias constructed in the LDS material package and on the die-to-die lines extending between the die vias.

8. The device of claim 7, wherein the LIFT material comprises a metallic material made of copper or silver.

9. The device of claim 7, further comprising a sintering material on the die-to-die lines extending over and between the die vias.

10. The device of claim 7 further comprising a layer of conductive electroless growth material between the surfaces of the die-to-die lines and the die vias and the LIFT material, wherein the LIFT material is in contact with the layer of conductive electroless growth material.

11. The device of claim 7, wherein the first semiconductor die and the second semiconductor die are disposed on at least one die pad in the substrate, wherein the substrate includes an array of conductive leads surrounding the at least one die pad;

and further comprising a die-to-lead conductive structure coupling the first and second semiconductor dies with selected ones of the conductive leads in the array of conductive leads, wherein the die-to-lead conductive structure comprises:

a first via extending through the LDS material between the surface of the LDS material package opposite the substrate and the first and second semiconductor dies;

a second via extending through the LDS material between the surface of the LDS material package opposite the substrate and a selected one of the conductive leads in the array of conductive leads; and

a conductive line extending between selected ones of the first vias and selected ones of the second vias at the surface of the LDS material package opposite the substrate.

12. The device of claim 11, further comprising:

a layer of conductive electroless growth material between the surfaces of the die-to-die lines and the die vias and the LIFT material, wherein the LIFT material is in contact with the layer of conductive electroless growth material; and

a conductive electroless growth material layer and a conductive plated material on the conductive electroless growth material layer at surfaces of the first via, the second via, and the conductive line.

13. A method, comprising:

molding a Laser Direct Structuring (LDS) material package over the first and second circuits, the LDS material package having an upper surface;

applying laser beam energy to selected locations of the upper surface of the LDS material package to laser activate and configure first and second vias extending through the LDS material between the upper surface and the first and second circuits, respectively;

applying laser beam energy to selected locations of the upper surface of the LDS material package to laser activate and configure connection lines in the LDS material package that extend at the upper surface between the first and second vias;

electrolessly growing a conductive layer onto the first via and onto the second via and onto the connecting line; and

applying a laser induced forward transfer LIFT process to transfer conductive material onto the conductive layer at the first and second vias and at the connection lines.

14. The method of claim 13, further comprising: the sintering is transferred to the conductive material on the conductive layer at the first and second vias and at the connection line.

15. The method of claim 13, wherein a LIFT process is applied to transfer a metallic material made of copper or silver onto the conductive layer at the first and second vias and at the connection lines.

16. The method of claim 13, wherein the first and second circuits are supported by a substrate comprising an array of conductive leads, the method further comprising:

applying laser beam energy to selected locations of the upper surface of the LDS material package to laser activate and configure third and fourth vias extending through the LDS material between the upper surface and the array of electrically conductive leads;

applying laser beam energy to selected locations of the top surface of the LDS material package to laser activate and construct another connection line extending in the LDS material package between the third and fourth vias at the top surface;

growing another conductive layer electrolessly onto the third via and onto the fourth via and onto the another connection line; and

applying LIFT processing to transfer conductive material onto the further conductive layer at the third and fourth vias and at the further connection line.

17. The method of claim 16, further comprising: after growing the further conductive layer electrolessly and before applying the LIFT process, a conductive material is electroplated onto the further conductive layer.

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