CN220510010U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Download PDF

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Publication number
CN220510010U
CN220510010U CN202321010587.5U CN202321010587U CN220510010U CN 220510010 U CN220510010 U CN 220510010U CN 202321010587 U CN202321010587 U CN 202321010587U CN 220510010 U CN220510010 U CN 220510010U
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die pad
thermally conductive
package
semiconductor
die
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CN202321010587.5U
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Chinese (zh)
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R·维拉
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STMicroelectronics SRL
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STMicroelectronics SRL
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Priority claimed from US18/140,194 external-priority patent/US20230361010A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present disclosure relates to semiconductor devices. A semiconductor device, comprising: a semiconductor die disposed on a first surface of a thermally conductive die pad of the substrate, the thermally conductive die pad having a second surface opposite the first surface; a package molded onto a thermally conductive die pad having a semiconductor die disposed on a first surface; wherein at the second surface of the thermally conductive die pad, the package has a recessed portion surrounding the package of the thermally conductive die pad; and a heat conductive member in the concave portion of the package; wherein a surface area of the thermally conductive die pad at the second surface is increased by the thermally conductive member in the recessed portion of the package. The thermal performance of the device can be advantageously improved by using the embodiments of the present disclosure.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
Technical Field
The present specification relates to semiconductor devices.
One or more embodiments may be applied to, for example, power semiconductor devices, including gallium nitride (GaN) or silicon carbide (SiC) devices.
Background
For example, the trend toward miniaturization of semiconductor die based on gallium nitride (GaN) or silicon carbide (SiC) devices has led to the search for improved heat dissipation in packages of small Integrated Circuit (IC) die.
Methods of achieving such improved performance may include die pad expansion at the lead frame design level.
This affects the leadframe size and the length of the leads in the wire bond pattern.
Another solution relies on a lead frame that includes leads overhanging the die pad.
Although conceptually attractive, this approach can be quite complex and expensive to implement.
There is a need in the art to help adequately address the foregoing problems.
Disclosure of Invention
It is an object of the present disclosure to provide a semiconductor device to at least partially solve the above-mentioned problems occurring in the prior art.
An aspect of the present disclosure provides a semiconductor device including: a semiconductor die disposed on a first surface of a thermally conductive die pad of the substrate, the thermally conductive die pad having a second surface opposite the first surface; a package molded onto a thermally conductive die pad having a semiconductor die disposed on a first surface; wherein at the second surface of the thermally conductive die pad, the package has a recessed portion surrounding the package of the thermally conductive die pad; and a heat conductive member in the concave portion of the package; wherein a surface area of the thermally conductive die pad at the second surface is increased by the thermally conductive member in the recessed portion of the package.
In accordance with one or more embodiments, wherein the thermally conductive member in the recessed portion of the package provides a continuous and/or contiguous frame around the thermally conductive die pad at the second surface of the thermally conductive die pad.
In accordance with one or more embodiments, wherein the thermally conductive member in the recessed portion of the package has a thickness equal to a thickness of the thermally conductive die pad.
In accordance with one or more embodiments, the thermally conductive member filled in the recessed portion of the package has a thickness different from a thickness of the thermally conductive die pad.
In accordance with one or more embodiments, the semiconductor device further includes an array of conductive leads surrounding the thermally conductive die pad, wherein the conductive leads in the array of conductive leads protrude above the thermally conductive member filled in the recessed portion of the package.
The thermal performance of the device can be advantageously improved by using the embodiments of the present disclosure.
Drawings
One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIGS. 1A and 1B are exemplary partial cross-sectional views of a step or stage in the manufacture of a semiconductor device;
fig. 2A and 2B are partial cross-sectional views of another step or stage of exemplary fabrication of a semiconductor device;
fig. 3A and 3B are partial cross-sectional views of an example of yet another step or stage of manufacturing a semiconductor device; and
fig. 4 and 5 are functional flowcharts comparing a conventional sequence of steps in semiconductor device fabrication with a sequence of steps in semiconductor device fabrication according to embodiments of the present description.
Detailed Description
Corresponding numerals and symbols in the various drawings generally indicate corresponding parts unless otherwise indicated.
The drawings are for clarity of illustration of related aspects of the embodiments and are not necessarily drawn to scale.
The edges of features depicted in the drawings do not necessarily represent the termination of the range of features.
In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.
Reference in the framework of this specification to "one embodiment" or "an embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present specification do not necessarily refer to the same embodiment.
Furthermore, in one or more embodiments, the particular conformations, structures, or features may be combined in any suitable manner.
Headings/references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.
For simplicity and ease of explanation, throughout the specification: like parts or elements in the various figures are denoted by like reference numerals, and the corresponding description is not repeated for each figure; and the fabrication of a single device will be described, it should be further understood that the current fabrication process of semiconductor devices involves the simultaneous fabrication of multiple devices that are separated into individual devices in a final singulation.
Fig. 1A-1B, 2A-2B and 3A-3B are exemplary partial cross-sectional views of certain steps or stages in the manufacture of a semiconductor device 10 having a plastic package.
Specifically: the left side view (fig. 1A, fig. 2A and fig. 3A) is an example of an arrangement that uses wire bond connections to provide electrical connections to a semiconductor chip or die; and the right-hand drawing (fig. 1B, fig. 2B and fig. 3B) is an example of an arrangement in which electrical connections to a semiconductor chip or die are provided using Laser Direct Structuring (LDS) technology.
As is conventional in the art, the device 10 includes a substrate (leadframe) on which one or more semiconductor chips or dies are disposed.
As used herein, the terms chip and die are considered synonymous with reference to integrated circuit.
Fig. 1A-1B, fig. 2A-2B and fig. 3A-3B refer by way of example to a semiconductor device 10 including a die pad 12A in a leadframe that also includes an array of leads 12B surrounding the die pad 12A, the die pad 12A having a semiconductor Integrated Circuit (IC) chip or die 14 attached thereto, for example, via a Die Attach Film (DAF) 140.
The designation "leadframe" (or "leadframe") (see, for example, the united states patent and trademark office's USPC consolidated vocabulary) refers to a metal frame that provides support for an integrated circuit chip or die, as well as electrical leads that interconnect the integrated circuits in the chip or die to other components or contacts.
Essentially, the leadframe includes an array of conductive structures (or leads, e.g., 12B) extending inwardly from the contoured location in the direction of a semiconductor chip or die (e.g., 14), forming an array of conductive structures from die pads (e.g., 12A) configured with at least one semiconductor integrated circuit chip or die attached thereto.
Some semiconductor devices may in fact include multiple die pads and/or multiple dies or chips attached to the or each die pad. For simplicity and ease of explanation, the present description refers to a device 10 that includes a single die pad 12A with a single chip or die attached to the single die pad 12A (on the first surface, facing upward in the figures).
Conductive structures are provided to electrically couple the semiconductor chip 14 to selected ones of the leads 12B in the leadframe.
As shown in fig. 1A, 2A, and 3A, these conductive structures may include wire bond patterns 16 that couple the chip 14 to selected ones of the leads 12B. Wires in wire bond pattern 16 couple to die pads (not visible for scale reasons) provided at the front or top surface of chip 141.
An insulating package 20 (e.g., epoxy) is molded over the assembly formed above to complete the plastic body of device 10.
Laser direct structuring (LDS-also commonly referred to as Direct Copper Interconnect (DCI) technology) is a laser-based processing technology that is now widely used in various sectors of the industrial and consumer electronics markets, for example for high performance antenna integration, where antenna designs can be formed directly on molded plastic parts.
In an exemplary process, the molded part may be produced with a commercially available insulating resin that includes additives suitable for use in the LDS process; a wide range of resins, for example polymeric resins such as PC, PC/ABS, ABS, LCP, are currently available for this purpose.
In LDS, a laser beam may be used to transfer ("build") a desired conductive pattern onto a plastic molding, which may then be metallized to complete the desired conductive pattern.
The metallization may include electroless plating, and then electrolytic plating.
Electroless plating, also known as electroless plating, is a class of industrial chemical processes that produce metal coatings on a variety of materials by autocatalytic chemical reduction of metal cations in a liquid bath.
In electrolytic plating, an electric field between an anode and a workpiece as a cathode forces positively charged metal ions to move to the cathode where they release their charge and deposit themselves as metal on the surface of the workpiece.
Reference to U.S. patent application publication nos. 2018/342453A1, 2019/115287A1, 2020/203264A1, 2020/321274A1, 2021/050226A1, 2021/050299A1, 2021/183748A1 or 2021/305503 A1 (all incorporated herein by reference) are examples of possibilities for applying LDS technology in the manufacture of semiconductor devices.
As shown in fig. 1B,2B, and 3B, the LDS technique facilitates replacement of a wire such as 16 with a wire/via created by a laser beam process of the LDS material followed by metallization (e.g., growing a metal such as copper by an electroplating process).
Conductive die-to-lead coupling structures (e.g., as discussed in the commonly assigned application referenced above) may be provided in an insulating package 18 of LDS material (once cured, e.g., by thermal curing).
As shown in fig. 1B,2B, and 3B, these die-to-wire coupling structures include: a first through-molding compound through-hole (TMV) 181 extending through the LDS package 18 between a top (front) surface 18A of the LDS package 18 and conductive pads (mentioned in connection with the wire bond pattern 16 and not visible for scale reasons) at the front or top surface of the chip or die 14; a second through-mold compound through-hole (TMV) 182 extending through the LDS package 18 between a top (front) surface 18A of the LDS package 18 and corresponding leads 12B in the lead frame; and conductive lines or traces 183 extending at the front or top surface 18A of the LDS package 18 and electrically coupling selected ones of the first vias 181 with selected ones of the second vias 182 to provide a desired die-to-lead electrical connection (routing) pattern between the chip or die 14 and the leads 12B.
Providing conductive die to lead structures 181, 182 and 183 basically comprises (see fig. 2B and 3B): these structures are structured in the LDS material of package 18, for example, by applying laser beam energy to "activate" (and partially drill/ablate) the LDS material 18 at desired locations 181',182', 183' for the through holes 181, 182 and lines or traces 183; and growing a conductive material (e.g., a metal such as copper) at locations 181',182', 183' that were previously activated (structured) via laser beam energy.
Growing the conductive material may involve depositing a metal, such as copper, by electroless/electrolytic metal growth to promote conductivity of the structured structure.
The conductive material may also be grown by a Laser Induced Forward Transfer (LIFT) process, which includes a deposition process in which transfer of material from a donor ribbon or sheet to an acceptor substrate (here, LDS material) is facilitated by a laser pulse.
General information about LIFT procedures can be found in, for example, p.serra et al: "Laser-Induced Forward Transfer: fundamentals and Applications", advanced Materials Technologies/volume 4, found in section 1 (incorporated herein by reference).
The semi-split arrangement of fig. 1A-3A and 1B-3B is intended to emphasize that processes may be applied that result in an increase in the surface area of the die pad 12A (i.e., by adding to the die pad, making it larger or increasing in size) as discussed below: i) For devices 10 that include wire bond patterns 16 such as in fig. 1A, 2A, and 3A, where package 20 may be a conventional package (e.g., epoxy) that insulates wire bond patterns 16 (fig. 1A, 2A, and 3A); and ii) for devices 10 in which package 18 is an LDS material, thus facilitating the provision of conductive structures 181, 182, and 183 (FIGS. 1B,2B, and 3B) therein.
Thus, a device 10 would be expected to employ either of schemes i) or ii) above, and thus include: two (substantially) mirror-symmetrical portions, each as shown in fig. 1A, 2A and 3A; or two (substantially) mirror-symmetrical portions, each as shown in fig. 1B,2B and 3B.
The term "roughly" is intended to take into account the fact that neither the wire bond patterns such as 16 (in the "wired" version of fig. 1A, 2A and 3A) nor the conductive structures such as 181, 182 and 183 (in the "laser structured" version of fig. 1B,2B and 3B) need to have a wire/line routing pattern that is strictly mirror symmetrical with respect to any intermediate plane of the device 10.
It should be understood that the examples discussed herein relate primarily to package thermal performance of devices such as device 10, and not to the specific details of die-to-wire (or die-to-die) electrical coupling therein.
The package thermal performance of the device 10 considered herein is determined by the package design and material selection and can be modeled based on various parameters.
For example: theta JA (θja) =junction-to-air thermal resistance; this is a measure of the device's ability to dissipate heat from the die surface to the surrounding environment through all possible paths; theta JC (θjc) =junction to housing thermal resistance; this is a measure of the ability of the device to dissipate heat from the surface of the die to the top or bottom surface of the package; theta Jb (θjb) =thermal resistance from the junction to the board on which the device is mounted; and psi JB (ψjb) is the junction-to-plate thermal characterization parameter; this is a measure of the power flowing from the device through multiple thermal paths rather than a single direct path (e.g., thermal resistance).
The parameters introduced in the foregoing were measured in units of K/W.
As discussed in the introductory portion of this specification, semiconductor (silicon) miniaturization results in a change in package design. These involve reducing the die pad (or heat spreader) size, which in itself will have a negative impact on thermal performance.
The current trend in chip miniaturization requires improved (higher) package heat dissipation, while package designs are not always compatible with the present description: when smaller dies are accommodated, the die pad size is reduced to reduce the length of the connection.
In fact, heat dissipation is improved in response to an increase in die pad size. New technologies such as gallium nitride (GaN) or silicon carbide (SiC) may dictate tighter heat dissipation specifications, resulting in package selection limitations.
Package redesign or package change may be considered an option to solve this problem: however, package redesign involves higher development costs and may not meet customer requirements.
Other options may involve modifications of the material, such as a reduction in die thickness or an improvement in die attach material. However, these measures are not as effective as package redesign.
It is therefore desirable to be able to enhance package thermal characteristics without adversely affecting the wire connection and leadframe design (and the range of applicability and customization, and thus device flexibility).
The example presented herein "enlarges" (enlarges) the back or bottom area (facing downward in fig. 1A-1B through 3A-3B) of die pad 12A without affecting die size and die-to-wire bond length.
Fig. 1A and 1B are examples of steps or stages in which at least one semiconductor chip 14 is disposed on a first surface (facing upward in the figures) of a thermally conductive (e.g., metal such as copper) die pad 12A in a substrate (leadframe).
The die pad 12A has a second surface (facing downwards in the figure) opposite the first surface, and packages 18, 20 of insulating material are molded (in a manner known per se to a person skilled in the art) onto the die pad 12A, the die pad 12A having the (at least one) semiconductor chip 14 arranged on the first surface.
As a result of the molding, at the second surface of the die pad 12A, the packages 18, 20 border (are substantially flush with) on the second surface of the die pad 12A along boundary lines around the die pad 12A (i.e., along the peripheral contour of the second surface of the die pad 12A).
As illustrated in fig. 2A and 2B, a recess or groove (continuous/discontinuous) 120A may be formed around the periphery of the second (back or bottom) surface of the die pad 12A.
As shown in fig. 3A and 3B, a thermally conductive member (e.g., a metal such as copper) is grown (filled) in the recess 120A to increase the surface area of the die pad area at the bottom side of the package (i.e., by increasing the surface area), as shown at 122A.
This concept, namely: providing a (continuous/discontinuous) recessed portion 120A of the package 18, 20 around the periphery of the second (back or bottom) surface of the die pad 12A, e.g., by removing insulating material from the package 18, 20 molded onto the die pad 12A at the boundary line of the second surface of the die pad 12A, to provide a recessed portion 120A of the package 18, 20 around the die pad 12A, or otherwise (e.g., via molding); filling the heat conductive member 122A in the recessed portion 120A of the package 18, 20 around the die pad 12A to increase the surface area of the heat conductive die pad 12A by filling the heat conductive member 122A therein; and helps to achieve this in different ways: regardless of the particular implementation options, the thickness of the die pad extension indicated by reference numeral 122A may be different from or the same as the thickness of the die pad 12A.
Forming the recess 120A may include, for example, selectively removing the encapsulation material.
As schematically indicated at LB in fig. 2A and 2B, ablation by a laser beam has been found to be advantageous due to its flexibility (e.g. the etching mask may be omitted).
The growth (filling) of the heat conductive member 122A in the groove 120A, as shown by MG in fig. 3A and 3B, may also be realized in a different manner.
For example, a seed layer or all of the desired thickness of material (e.g., copper) may be jet printed into the recess 120A, optionally followed by electroplating.
The use of Laser Direct Structuring (LDS) material for the encapsulation 18 represents an advantageous option in terms of: the laser beam energy LB used to form the recess 120A in the package 18 at the back or bottom surface of the device 10 can likewise be used to "structure" (by "activating" the LDS material) the through-holes 181, 182 and lines or traces 183 (see 181',182' and 183' of fig. 2B) at the front or top surface 18A therein; and the same process, such as electroplating (e.g., electroless electrowinning) or LIFT process, may be used to grow an electrically/thermally conductive component (e.g., metal, such as copper) at recess 120A to extend the heat spreader die pad area at the bottom side of the package at 122A and facilitate electrical conductivity of the through-mold vias 181, 182 and lines or traces 183 at the front or top surface of device 10 (see fig. 2B).
Laser Direct Structuring (LDS) materials may also be used for packages 20 as shown in fig. 1A, 2A and 3A, i.e., packages for wire bond patterns (e.g., wire bond pattern 16) in the form of "wires" for packaging device 10.
Also in the latter case, laser beam energy LB may be used to drill/ablate the LDS material of the package to form grooves 120A, e.g., electroplating (e.g., electroless electrowinning), LIFT process (or jet printing) is used to grow electrically/thermally conductive features at grooves 120A to extend the heat spreader die pad area at the bottom side of the package at 122A.
It should be noted that the laser beam energy LB drills/ablates some LDS material (thus providing a shaping effect or action) and in doing so also activates the LDS material (thus affecting the properties of the surface of the LDS molding compound).
Laser Direct Structuring (LDS) may be used in combination with conventional mold apparatus and known packaging.
The examples presented herein facilitate enlarging the area of the die pad 12A without otherwise affecting the package design. Die pad expansion is performed after molding and does not affect the leadframe design. Leadframe features (e.g., short connections from die to leads) can be maintained while improving heat dissipation.
This is demonstrated by the functional flow diagrams of fig. 4 and 5. These flowcharts relate to a conventional sequence of steps for manufacturing a semiconductor device (fig. 4) and a sequence of steps for manufacturing a semiconductor device according to an embodiment of the present specification (fig. 5), respectively.
It should further be understood that the order of the steps of fig. 4 and 5 is merely exemplary, so long as: one or more of the steps shown therein may be omitted, performed in a different manner (e.g., with other tools) and/or replaced by other steps; additional steps may be added; and one or more steps may be performed in an order different than that shown.
In fig. 4 and 5, block 100 collectively indicates those steps prior to molding an insulating package thereon to create the basic structure of a semiconductor device (e.g., attach one or more chips or dies 14 to die pad 12A, etc.) in a manner known to those skilled in the art.
This step (e.g., molding the conventional package 20 of epoxy) is shown at 102 in fig. 4, followed by (tin) plating and "shearing" as represented by blocks 104 and 106, respectively, in fig. 4.
The resulting "standard" die pad 12A is shown at the bottom of fig. 4: this may be seen as a schematic view of the device 10 as seen from the back or bottom side of the device 10.
In the exemplary case shown in fig. 5, block 100 is followed by a sequence 102' of molding steps of the package of LDS material 18, followed by an LDS process at 102B.
As previously discussed in connection with fig. 2B and 3B, this process may involve applying laser beam energy LB to form grooves 120A at the back or bottom surface of device 10 and to structure vias 181, 182 and lines or traces 183 at the front or top surface of device 10.
In fig. 5, electroplating at 104' may represent copper electroplating + tin electroplating (e.g., electroless plus electrolytic deposition) or LIFT process for growing an electrically/thermally conductive component (e.g., metal, such as copper) at recess 120A to extend the heat spreader die pad area at the bottom side of the package at 122A and facilitate electrical conductivity of the through-plastic vias 181, 182 and lines or traces 183 at the front or top surface of device 10.
The resulting standard die pad 12A with "increased" surface area at 122A is shown at the bottom of fig. 5: this may be seen as a schematic view of the device 10 as seen from the back or bottom side of the device 10.
Although shown here as a continuous and contiguous frame around the original die pad 12A, in some embodiments the enlarged portion 122A may be discontinuous (i.e., include multiple segments or points in a dashed/dotted line pattern) and/or not contiguous with the original die pad 12A (i.e., have a separation gap).
It should be appreciated that expanding die pad 12A at 122A (thus improving heat dissipation of device 10) occurs without increasing the overall size of device 10, and more particularly, without increasing the length of the electrical connection path (e.g., wires 16 or "LDS structured" structures 181, 182, 183) between semiconductor chip 14 and leads 12B.
Indeed, as can be seen in the examples presented herein, the leads 12B may be caused to protrude above (overhang) the enlarged portion 122A of the die pad 12A.
The examples presented herein are applicable to virtually any leadframe-based plastic package.
The following table reports die sizes on the order of μm (X: Y: Z) obtained by TRAC simulation: 4182 to 3262 to 375 of PSSO36 encapsulated comparison data. A wired version. Die attach material: and (5) soft welding.
An aspect of the present disclosure provides a method comprising: disposing a semiconductor integrated circuit die on a first surface of a thermally conductive die pad of a substrate, the thermally conductive die pad having a second surface opposite the first surface; molding a package of insulating material onto the thermally conductive die pad, wherein at a second surface of the thermally conductive die pad, the package interfaces with the thermally conductive die pad at a boundary line around the thermally conductive die pad; providing a recessed portion of the package surrounding the thermally conductive die pad at a boundary line surrounding the thermally conductive die pad; and filling the heat conductive member in the concave portion of the package; wherein a surface area of the thermally conductive die pad at the second surface is increased by the thermally conductive member in the recessed portion of the package.
According to one or more embodiments, wherein filling the thermally conductive member comprises one of: jet printing the heat conductive member at the recessed portion; plating a heat conductive member at the recessed portion; or laser-induced forward transfer of the heat conductive member at the concave portion.
In accordance with one or more embodiments, wherein providing the recessed portion includes removing insulating material from the package molded onto the thermally conductive die pad at a boundary line around the thermally conductive die pad.
In accordance with one or more embodiments, wherein removing includes applying laser beam energy to the package.
In accordance with one or more embodiments, wherein the encapsulated insulating material comprises a laser direct structuring LDS material, and wherein removing comprises applying laser structuring to the encapsulated LDS material at a boundary line around the thermally conductive die pad.
In accordance with one or more embodiments, wherein the encapsulated LDS material has a front surface opposite the thermally conductive die pad, and further comprising: structuring a through-mold via in the encapsulated LDS material extending from the front surface into the encapsulation; and structuring in the encapsulated LDS material connection lines extending between selected ones of the through holes above the front surface.
According to one or more embodiments, the method further comprises: applying laser energy to the encapsulated LDS material at candidate locations for the through holes and the connection lines; and filling the conductive material at the candidate locations after applying the laser beam energy to provide conductive vias and bond lines at the candidate locations.
In accordance with one or more embodiments, wherein filling the conductive material comprises: electroplating a conductive material at the candidate locations; or laser induced forward transfer of the thermally conductive member at the candidate location.
In accordance with one or more embodiments, the thermally conductive member filled in the recessed portion of the package has a thickness different from a thickness of the thermally conductive die pad.
In accordance with one or more embodiments, wherein the substrate includes an array of electrically conductive leads surrounding the thermally conductive die pad, and wherein the electrically conductive leads protrude above the thermally conductive member filled in the recessed portion of the package.
In accordance with one or more embodiments, wherein the thermally conductive die pad is made of an electrically conductive material, and wherein the thermally conductive member in the recessed portion of the package is made of an electrically conductive material.
One or more embodiments may relate to a method.
One or more embodiments may relate to a corresponding semiconductor device.
The examples presented herein relate to increasing (i.e., expanding) the back or bottom area of a die pad without otherwise affecting die size and die-to-wire bond length.
For example, a laser beam may be used to form a groove around the periphery of the bottom surface of the die pad. A thermally conductive member (e.g., a metal such as copper) is filled (e.g., grown) in the recess to extend the die pad area on the bottom side of the package.
The seed layer of printed copper or the entire desired thickness may be sprayed, optionally followed by electroplating.
Laser Direct Structuring (LDS) materials may be used as the encapsulation molding material and thermally conductive components (e.g., metals such as copper) may be grown in the grooves by conventional methods in standard LDS processes (electroless plating).
Thermally conductive components, such as metals of copper, may also be grown in the grooves by means of a Laser Induced Forward Transfer (LIFT) process.
The resulting die pad extension thickness may be equal to or different than the thickness of the leadframe die pad.
One or more embodiments relate to the use of molding materials compatible with Laser Direct Structuring (LDS).
The process may be used in combination with conventional molding equipment and known packages. The higher cost of the LDS compound has little impact on the total package cost due to the small amount of LDS material involved, and is advantageously less than any cost associated with a possible package redesign.
The embodiments of the present description used may be identified by, for example, a different surface morphology of the basic die pad compared to the surrounding grown material to increase the die pad size. The leads in the leadframe that "overhang" the die pad may additionally indicate that the die pad has been enlarged by additional material grown around it after fabrication of the leadframe. In addition, molding compound analysis may highlight the use of molding compounds compatible with Laser Direct Structuring (LDS) processes.
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection. The scope of protection is determined by the appended claims.
The claims are an integral part of the technical teaching of the embodiments provided herein.

Claims (5)

1. A semiconductor device, comprising:
a semiconductor die disposed on a first surface of a thermally conductive die pad of a substrate, the thermally conductive die pad having a second surface opposite the first surface;
a package molded onto the thermally conductive die pad, the thermally conductive die pad having the semiconductor die disposed on the first surface;
wherein at the second surface of the thermally conductive die pad, the package has a recessed portion surrounding the package of the thermally conductive die pad; and
a heat conductive member in the concave portion of the package;
wherein a surface area of the thermally conductive die pad at the second surface is increased by the thermally conductive member in the recessed portion of the package.
2. The semiconductor device of claim 1, wherein the thermally conductive member in the recessed portion of the package provides a continuous and/or contiguous frame around the thermally conductive die pad at the second surface of the thermally conductive die pad.
3. The semiconductor device of claim 1, wherein the thermally conductive member in the recessed portion of the package has a thickness equal to a thickness of the thermally conductive die pad.
4. The semiconductor device according to claim 1, wherein the heat conductive member filled in the concave portion of the package has a thickness different from a thickness of the heat conductive die pad.
5. The semiconductor device of claim 1, further comprising an array of electrically conductive leads surrounding the thermally conductive die pad, wherein electrically conductive leads in the array of electrically conductive leads protrude above the thermally conductive member filled in the recessed portion of the package.
CN202321010587.5U 2022-05-03 2023-04-28 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Active CN220510010U (en)

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