CN115693391A - N electrode applied to chip, preparation method and VCSEL chip - Google Patents
N electrode applied to chip, preparation method and VCSEL chip Download PDFInfo
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Abstract
The invention discloses an N electrode applied to a chip, a preparation method and a VCSEL chip, wherein the N electrode comprises: the Pd layer is arranged on the GaAs substrate of the chip; the Ge layer is arranged on the surface of the Pd layer far away from the GaAs substrate; the metal adhesion layer is arranged on the surface of the Ge layer far away from the Pd layer; the metal barrier layer is arranged on the surface of the metal adhesion layer far away from the Ge layer; and the metal routing layer is arranged on the surface of the metal barrier layer, which is far away from the metal adhesion layer. The Pd layer and the Ge layer of the invention can realize lower contact resistance with the GaAs substrate through lower annealing temperature, thereby further improving the reliability of the device. Meanwhile, the Pd layer and the Ge layer can be formed by evaporation respectively, and the control of the proportion of each metal is convenient to realize in the evaporation process, so that the problem of deviation of the AuGeNi alloy components does not exist.
Description
Technical Field
The invention relates to the fields of photoelectrons, microelectronics and power device technology, in particular to an N electrode applied to a chip, a preparation method and a VCSEL chip.
Background
A Vertical Cavity Surface Emitting Laser (VCSEL) is different from other Light sources such as an LED (Light Emitting Diode) and an LD (Laser Diode), has the advantages of small volume, circular output Light spot, single longitudinal mode output, small threshold current, easy integration of a large-area array, and the like, and is widely applied to the fields of optical communication, optical interconnection, optical storage, and the like. With the continuous development of science and technology, various VCSEL chips are widely applied to daily life, work and industry of people, and bring great convenience to the life of people.
The N electrode metal in the VCSEL chip is generally evaporated by using an AuGeNi alloy and Au. Wherein, the ratio of each metal in the AuGeNi alloy is as follows: the metal Ni accounts for 3-5% of the total molar mass, the Au accounts for 88% of the molar mass except Ni, and the Ge accounts for 12% of the molar mass except Ni. The AuGeNi alloy layer is directly contacted with the N-type GaAs substrate, and the Au layer is arranged on the surface of the AuGeNi alloy layer far away from the GaAs substrate. After the electrode metal system is prepared, annealing treatment is carried out at 400-450 ℃ by using RTA equipment (rapid annealing furnace), after annealing is carried out in oxygen-free atmosphere of 30s-3min, ohmic contact can be formed between the N electrode and N type GaAs, and the contact resistance Rc is 10 -4 ~10 -5 Ω·cm 2 。
However, this technique has the following disadvantages:
1. the AuGeNi alloy needs to carry out annealing treatment on the alloy layer by using rapid heat treatment at 400 to 450 ℃ and 30s to 3min so as to reduce the contact resistance between the N electrode and the N-type GaAs substrate. The VCSEL chip comprises other multi-layer materials besides the N electrode, the thermal expansion coefficients of the materials of all layers are different, the high-temperature process of the rapid thermal treatment of the N electrode can have adverse effects on the reliability of a device, the annealing temperature needs to be reduced as much as possible, and the purpose of annealing the AuGeNi alloy layer cannot be achieved due to too low temperature.
2. The AuGeNi alloy is a ternary metal alloy of Au, ge and Ni, and the melting points and the evaporation rates of all metals are different under the same steam pressure. Therefore, in the evaporation process, the ratio of each metal in the electrode gradually deviates from the standard value, and the contact resistance with N-type GaAs is finally affected.
3. The eutectic temperature of the AuGeNi alloy is 350-370 ℃, and the annealing temperature of the AuGeNi alloy for forming good ohmic contact exceeds the eutectic temperature of the AuGeNi layer, so that the AuGeNi layer is subjected to a high-temperature annealing process and then is balling up on the surface of the metal electrode, and globular alloy points (a globular phenomenon) are formed on the surface of the metal electrode, thereby not only influencing the appearance of a product, but also influencing the adhesion of subsequent SiN and the electrode.
Disclosure of Invention
The present invention is directed to solving, at least in part, one of the technical problems in the related art. To this end, an object of the present invention is to provide an N-electrode applied to a chip, a method of manufacturing the same, and a VCSEL chip. The Pd layer and the Ge layer of the invention can realize lower contact resistance with the GaAs substrate through lower annealing temperature, thereby further improving the reliability of the device. Meanwhile, the Pd layer is a Pd metal single-layer, the Ge layer is a Ge metal single-layer, and the two layers can be formed by evaporation respectively, so that the control of the proportion of each metal is convenient to realize in the evaporation process, and the problem of deviation of the AuGeNi alloy components does not exist. In addition, the Pd layer and the Ge layer are arranged as N electrodes, so that the annealed metal surface has better appearance, and the subsequent PECVD SiN deposition process is facilitated.
In one aspect of the invention, the invention provides an N electrode for a chip. According to an embodiment of the present invention, the N-electrode applied to the chip includes: the Pd layer is arranged on the GaAs substrate of the chip; a Ge layer disposed on at least a portion of a surface of the Pd layer distal from the GaAs substrate; the metal adhesion layer is arranged on at least part of the surface of the Ge layer far away from the Pd layer; the metal barrier layer is arranged on at least part of the surface of the metal adhesion layer far away from the Ge layer; the metal routing layer is arranged on at least part of the surface of the metal barrier layer, which is far away from the metal adhesion layer.
According to the N electrode applied to the chip, the Pd layer and the Ge layer have lower contact resistance with the GaAs substrate through lower annealing temperature, so that the reliability of the device is further improved. Meanwhile, the Pd layer is a Pd metal single-layer, the Ge layer is a Ge metal single-layer, and the two layers can be formed by evaporation respectively, so that the control of the proportion of each metal is convenient to realize in the evaporation process, and the problem of deviation of the AuGeNi alloy components does not exist. In addition, the Pd layer and the Ge layer are arranged as N electrodes, so that the annealed film has better metal surface appearance, and a subsequent PECVD SiN deposition process is facilitated.
In addition, the N-electrode applied to the chip according to the above embodiment of the present invention may also have the following additional technical features:
in some embodiments of the invention, the thickness of the Pd layer is 40 to 60nm.
In some embodiments of the invention, the thickness of the Ge layer is 100 to 150nm.
In some embodiments of the invention, the metal adhesion layer is a Ti layer.
In some embodiments of the invention, the thickness of the metal adhesion layer is 40 to 60nm.
In some embodiments of the invention, the metal barrier layer is a Pt layer; and/or the thickness of the metal barrier layer is 40 to 60nm.
In some embodiments of the present invention, the metal routing layer is an Au layer; and/or the thickness of the metal routing layer is 300 to 500nm.
In another aspect of the present invention, the present invention provides a method for preparing the above N-electrode, comprising:
(1) Sequentially forming a Pd layer, a Ge layer, a metal adhesion layer, a metal barrier layer and a metal routing layer on the GaAs substrate by adopting an evaporation method;
(2) And annealing the Pd layer, the Ge layer, the metal adhesion layer, the metal barrier layer and the metal routing layer.
The method for preparing the N electrode is simple and easy to implement, and the method can realize lower contact resistance with a GaAs substrate through lower annealing temperature, so that the reliability of the device is further improved. Meanwhile, the Pd metal single-layer and the Ge metal single-layer are formed by evaporation respectively, and the control of the proportion of each metal is convenient to realize in the evaporation process, so that the problem of deviation of the AuGeNi alloy components is solved. In addition, the Pd layer and the Ge layer are formed as N electrodes, so that the annealed metal surface has better appearance, and the subsequent PECVD SiN deposition process is facilitated.
In addition, the method according to the above embodiment of the present invention may also have the following additional technical features:
in some embodiments of the invention, the temperature of the annealing treatment is 250-300 ℃, and the time of the annealing treatment is 10-20min.
In a third aspect of the invention, a VCSEL chip is presented. According to an embodiment of the present invention, the VCSEL chip includes the N-electrode described in the above embodiment or the N-electrode manufactured by the method described in the above embodiment. Therefore, the reliability of the VCSEL chip is further improved, the preparation process of the VCSEL chip is further simplified, and energy and cost are saved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic structural diagram of an N electrode applied to a chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a VCSEL chip according to an embodiment of the present invention.
The figure marks 100-GaAs substrate, 200-NDBR layer, 300-MQW layer, 400-oxidation layer, 500-PDBR layer, 600-P contact layer, 700-P electrode, 800-N electrode, 810-Pd layer, 820-Ge layer, 830-metal adhesion layer, 840-metal barrier layer, 850-metal routing layer and 900-SiN passivation layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientations and positional relationships indicated in the drawings, which are based on the orientations and positional relationships indicated in the drawings, and are used for convenience in describing the present invention and for simplicity in description, but do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, e.g., two, three, four, five, six, etc., unless explicitly specified otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In one aspect of the invention, the invention provides an N electrode for a chip. Referring to fig. 1, according to an embodiment of the present invention, the N electrode 800 includes: a Pd layer 810, the Pd layer 810 being disposed on the GaAs substrate 100 of the chip; a Ge layer 820, the Ge layer 820 being disposed on at least a portion of a surface of the Pd layer 810 remote from the GaAs substrate 100; a metal adhesion layer 830, wherein the metal adhesion layer 830 is arranged on at least part of the surface of the Ge layer 820 far away from the Pd layer 810; a metal barrier layer 840, the metal barrier layer 840 disposed on at least a portion of a surface of the metal adhesion layer 830 distal from the Ge layer 820; a metal wire bonding layer 850, wherein the metal wire bonding layer 850 is disposed on at least a portion of the surface of the metal barrier layer 840 away from the metal adhesion layer 830. Thus, the Pd layer 810 and the Ge layer 820 can achieve lower contact resistance with the GaAs substrate 100 by a lower annealing temperature, thereby further improving the reliability of the device. Meanwhile, the Pd layer 810 is a Pd metal single-layer, the Ge layer 820 is a Ge metal single-layer, and the two layers can be formed by evaporation respectively, so that the control of the proportion of each metal is convenient to realize in the evaporation process, and the problem of deviation of the AuGeNi alloy components does not exist. In addition, the Pd layer 810 and the Ge layer 820 are arranged to serve as N electrodes, so that the annealed film has better metal surface appearance, and a subsequent PECVD SiN deposition process is facilitated.
The following is a detailed description of the principle of the present invention that the N electrode can achieve the above beneficial effects:
first, the present invention forms a Pd-rich PdxGayAs compound at the interface by sequentially disposing a Pd layer 810 and a Ge layer 820 on the surface of a GaAs substrate 100, and diffusing part of Pd disposed on GaAs with respect to the GaAs interface, thereby forming a Pd-rich PdxGayAs compound at the interfaceLeaving Ga vacancies on the GaAs surface; after annealing, partial GaAs on the surface of the substrate is decomposed, ga diffuses to the contact layer, ga vacancy is continuously generated in GaAs, and Ge penetrates through the Pd layer to occupy Ga vacancy, so that heavily doped n is formed on the GaAs surface + GaAs layer, achieving a low contact resistance (up to 10) with GaAs substrate 100 -5 Ω·cm 2 ). And the Pd layer 810 and the Ge layer 820 can realize lower contact resistance with the GaAs substrate 100 through lower annealing temperature (250-300 ℃), thereby solving the problem that adverse effects on the reliability of devices are caused by higher annealing temperature of AuGeNi alloy in the prior art. Therefore, the present invention reduces the annealing temperature of the N electrode by using the Pd layer 810 and the Ge layer 820, thereby further improving the reliability of the device. In addition, in the preparation of the VCSEL chip, after the metal deposition of each layer of the N electrode is finished, a PECVD SiN deposition process is carried out in the chip process, the temperature of the PECVD process is set to be 250-300 ℃, the process time is 10-15min, and the annealing effect of the N electrode can be synchronously realized in the PECVD SiN deposition process, so that an additional annealing procedure is not needed in the process, the preparation process of the VCSEL chip is further simplified, and the energy and the cost are saved.
Note that, the Pd layer 810 and the Ge layer 820 must be provided in this order on the surface of the GaAs substrate 100, and if the Ge layer and the Pd layer are provided in this order on the surface of the GaAs substrate 100, a contact with good ohmic characteristics cannot be obtained even if the annealing time is longer.
Second, the Pd layer 810 is a Pd metal single layer, the Ge layer 820 is a Ge metal single layer, and the two layers can be formed by evaporation respectively, which is convenient for realizing the control of each metal proportion in the evaporation process, so that the problem of deviation of each metal component content in the AuGeNi alloy does not exist. Therefore, the present invention further reduces the contact resistance with the N-type GaAs substrate 100 by separately providing the Pd layer 810 and the Ge layer 820, compared to the prior art.
Thirdly, the Pd layer 810 and the Ge layer 820 are arranged to serve as N electrodes, so that the annealed metal surface has better appearance, and the subsequent PECVD SiN deposition process is facilitated. In the prior art, the AuGeNi alloy needs higher annealing temperature to form good ohmic contact and exceeds the eutectic temperature of alloy metal, so that the AuGe alloy is easy to pill in annealing and has poor appearance. The Pd layer and the Ge layer have low annealing temperature and no pilling phenomenon, so the film has good appearance.
According to an embodiment of the invention, the thickness of the Pd layer 810 is 40 to 60nm, the thickness of the Pd layer 810 is limited to the above range, and after annealing, a good ohmic contact can be formed. Specifically, if the thickness of the Pd layer 810 is too small, the amount of diffusion of Pd into GaAs is small, and good ohmic contact cannot be obtained after annealing; if the thickness of the Pd layer 810 is too large, this may result in poor ohmic contact after annealing due to difficulty in the Ge occupying Ga vacancies through the Pd layer.
According to another embodiment of the invention, the thickness of the Ge layer 820 is 100 to 150nm, the thickness of the Ge layer 820 is limited to the above range, and after annealing, a good ohmic contact can be formed. Specifically, if the thickness of the Ge layer 820 is too small, this may result in less Ge occupying Ga vacancies after annealing, and a good ohmic contact may not be obtained; if the thickness of the Ge layer 820 is too large, this will result in too large a Ge thickness that does not pass through the Pd layer after annealing, which will result in a higher overall resistance of the electrode metal due to the higher resistance of the Ge metal.
In the embodiment of the present invention, the metal adhesion layer 830 functions as an adhesion layer for the Ge layer 820 and the metal barrier layer 840, and increases the adhesion between the Ge layer 820 and the metal barrier layer 840. Specifically, the metal adhesion layer 830 may be a Ti layer, which has a strong adhesion. Furthermore, the thickness of the metal adhesion layer 830 is 40 to 60nm, and the thickness of the metal adhesion layer 830 is limited within the above range, so that the metal adhesion layer has an adhesion effect on the Ge layer and the Pt layer, and no energy and cost waste is caused.
In the embodiment of the present invention, the metal barrier layer 840 serves as a barrier layer between the metal adhesion layer 830 and the metal wire bonding layer 850, so as to prevent a metal alloying phenomenon from occurring between the metal wire bonding layer 850 (e.g., au layer) and the metal adhesion layer 830 (e.g., ti layer), thereby preventing the metal wire bonding layer 850 (e.g., au layer) and the metal adhesion layer 830 (e.g., ti layer) from decreasing in toughness and being easily peeled off from the N electrode due to the metal alloying phenomenon. Specifically, the metal barrier layer 840 may be a Pt layer, which has stable properties and is not easily alloyed. Furthermore, the thickness of the metal barrier layer 840 is 40 to 60nm, the thickness of the metal barrier layer 840 is limited within the range, the metal barrier layer has the effect of blocking the Ti layer and the Au layer, the phenomenon of metal alloying of the interface of the Ti layer and the Au layer is prevented, and energy and cost waste is avoided.
In the embodiment of the present invention, the metal wire bonding layer 850 functions as a wire bonding layer, which facilitates the adhesion of the gold wire to the electrode in the subsequent wire bonding process. Specifically, the metal routing layer 850 may be an Au layer. Furthermore, the thickness of the metal wire bonding layer 850 is 300 to 500nm, the thickness of the metal wire bonding layer 850 is limited within the range, the metal wire bonding layer has the effect of gold wire bonding in the subsequent process, and energy and cost waste is avoided.
In another aspect of the present invention, the present invention provides a method for preparing the above N-electrode, comprising:
s100: and a Pd layer, a Ge layer, a metal adhesion layer, a metal barrier layer and a metal routing layer are sequentially formed on the GaAs substrate.
In the step, a Pd layer, a Ge layer, a metal adhesion layer, a metal barrier layer and a metal routing layer are sequentially formed on the GaAs substrate by adopting an evaporation method.
S200: and (5) annealing treatment.
In the step, annealing treatment is carried out on the Pd layer, the Ge layer, the metal adhesion layer, the metal barrier layer and the metal routing layer at the same time in an oxygen-free atmosphere, and after the annealing treatment, the Pd layer and the Ge layer realize lower ohmic contact (up to 10) with the N-type GaAs substrate -5 Ω·cm 2 ）。
According to a specific embodiment of the invention, the temperature of the annealing treatment is 250-300 ℃, and the time of the annealing treatment is 10-20min, so that the Pd layer and the Ge layer can realize lower contact resistance with the GaAs substrate through lower annealing temperature, and the adverse effect on the reliability of a device caused by higher annealing temperature of the AuGeNi alloy in the prior art is solved. In addition, in the preparation of the VCSEL chip, after the deposition of each layer of metal of the N electrode is finished, a PECVD SiN deposition process is carried out in the chip process, the temperature of the PECVD process is set to be 250-300 ℃, the process time is 10-15min, and the annealing effect of the N electrode can be synchronously realized in the PECVD SiN deposition process, so that an additional annealing procedure is not needed in the process, the preparation process of the VCSEL chip is further simplified, and the energy and the cost are saved.
The method for preparing the N electrode is simple and easy to implement, and the method can realize lower contact resistance with the GaAs substrate through lower annealing temperature, so that the reliability of the device is further improved. Meanwhile, the Pd metal single-layer and the Ge metal single-layer are formed by evaporation respectively, and the control of the proportion of each metal is convenient to realize in the evaporation process, so that the problem of deviation of the AuGeNi alloy components is solved. In addition, the Pd layer and the Ge layer are formed as N electrodes, so that the annealed metal surface has better appearance, and the subsequent PECVD SiN deposition process is facilitated.
In a third aspect of the invention, a VCSEL chip is presented. According to an embodiment of the present invention, the VCSEL chip includes the N-electrode described in the above embodiment or the N-electrode manufactured by the method described in the above embodiment. Therefore, the reliability of the VCSEL chip is further improved, the preparation process of the VCSEL chip is further simplified, and energy and cost are saved.
Specifically, referring to fig. 2, the vcsel chip includes a GaAs substrate 100, wherein an NDBR layer 200, an MQW layer 300, an oxide layer 400, a PDBR layer 500, and a P contact layer 600 are sequentially formed on the GaAs substrate 100 from bottom to top in a layered structure.
The following takes a VCSEL chip with a lens structure as an example, and the fabrication method of the VCSEL chip is specifically described with reference to fig. 2, where the following conditions are:
sequentially forming an NDBR layer 200, an MQW layer 300, an oxide layer 400, a PDBR layer 500 and a P contact layer 600 on the GaAs substrate 100 from bottom to top according to a layered structure;
on the P contact layer 600, a P electrode 700 is prepared by a photoresist stripping technique after evaporation;
etching the epitaxial layer to the oxide layer by utilizing an ICP etching technology, and performing wet oxidation by utilizing an oxidation furnace to complete the preparation of the oxide layer 400;
etching the epitaxial layer to the conductive substrate by utilizing an ICP (inductively coupled plasma) etching technology, and preparing the N electrode 800 by utilizing a photoresist stripping technology after evaporation;
the preparation of the SiN passivation layer 900 is performed on the surface of the VCSEL chip using a PECVD technique, thereby completing the preparation of the VCSEL chip.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. An N electrode for chip applications, comprising:
the Pd layer is arranged on the GaAs substrate of the chip;
a Ge layer disposed on at least a portion of a surface of the Pd layer distal from the GaAs substrate;
the metal adhesion layer is arranged on at least part of the surface of the Ge layer far away from the Pd layer;
the metal barrier layer is arranged on at least part of the surface of the metal adhesion layer far away from the Ge layer;
the metal routing layer is arranged on at least part of the surface of the metal barrier layer, which is far away from the metal adhesion layer.
2. The N electrode applied to a chip of claim 1, wherein the thickness of the Pd layer is 40 to 60nm.
3. The N electrode applied to a chip of claim 1, wherein the thickness of the Ge layer is 100 to 150nm.
4. The N-electrode for chip application according to any one of claims 1 to 3, wherein the metal adhesion layer is a Ti layer.
5. The N electrode applied to a chip according to claim 4, wherein the thickness of the metal adhesion layer is 40 to 60nm.
6. The N-electrode applied to a chip according to any one of claims 1 to 3, wherein the metal barrier layer is a Pt layer;
and/or the thickness of the metal barrier layer is 40 to 60nm.
7. The N electrode applied to the chip as claimed in any one of claims 1 to 3, wherein the metal routing layer is an Au layer;
and/or the thickness of the metal routing layer is 300 to 500nm.
8. A method for preparing an N-electrode for a chip according to any one of claims 1 to 7, comprising:
(1) Sequentially forming a Pd layer, a Ge layer, a metal adhesion layer, a metal barrier layer and a metal routing layer on the GaAs substrate by adopting an evaporation method;
(2) And annealing the Pd layer, the Ge layer, the metal adhesion layer, the metal barrier layer and the metal routing layer.
9. The method according to claim 8, wherein the temperature of the annealing treatment is 250 to 300 ℃, and the time of the annealing treatment is 10 to 20min.
10. A VCSEL chip comprising the N-electrode of any of claims 1 to 7 or the N-electrode produced by the method of claim 8 or 9.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001077458A (en) * | 1999-07-07 | 2001-03-23 | Nec Corp | Semiconductor optical element |
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