CN115692416A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: the semiconductor device comprises a substrate, a plurality of fins and a plurality of fins, wherein the substrate is provided with the plurality of fins; a first gate structure located on the substrate; the source-drain doping layers are positioned on two sides of the first grid structure; a dielectric structure located on the substrate, the dielectric structure being higher than the first gate structure; a first opening in the dielectric structure; an isolation structure located within the first opening; a gate conductive opening within the dielectric structure; and the grid conducting layer is positioned in the grid conducting opening and is electrically connected with the first grid structure. The isolation structure is used as a self-aligned film layer of the formed grid conductive opening, so that the forming accuracy of the grid conductive opening is effectively improved, the occurrence of the short circuit problem of a circuit is reduced, and the performance of the finally formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

The electronics industry has experienced an increasing demand for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. Accordingly, a continuing trend in the semiconductor industry is to fabricate low cost, high performance, and low power Integrated Circuits (ICs). These goals have been achieved to a great extent by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of the semiconductor manufacturing process. Accordingly, the realization of continued progress in semiconductor ICs and devices requires similar advances in semiconductor fabrication processes and technologies.

The gate is part of the device and its material greatly affects the performance of the device. In the traditional polysilicon gate process, a metal gate is introduced because the polysilicon depletion effect influences the conduction of a device. To achieve better epitaxial stress, it is necessary to cut off the metal gate beyond the 5nm node, a process that not only achieves good profile but also shrinks the feature size beyond 20 nm.

However, there are still many problems in the prior art during the metal gate cutting process.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.

To solve the above problems, the present invention provides a semiconductor structure, comprising: the substrate is provided with a plurality of fin parts parallel to a first direction; the isolation layer is positioned on the substrate, covers partial side walls of the fin parts, and the top surfaces of the isolation layer are lower than the top surfaces of the fin parts; the first grid electrode structure is positioned on the isolation layer and spans the plurality of fin parts along a second direction, and the first direction is vertical to the second direction; the side wall is positioned on the side wall of the first grid structure; the source-drain doping layers are positioned in the fin parts on two sides of the first grid structure; the source-drain conducting layers are connected with the source-drain doping layers on one side of the first grid structure, and the top surface of the first grid structure is higher than that of the source-drain conducting layers; the dielectric structure is positioned on the isolation layer, covers the first grid structure and the source drain conducting layer, and is higher than the top surfaces of the first grid structure and the source drain conducting layer; a first opening in the dielectric structure, the first opening penetrating the first gate structure along the first direction and exposing a portion of the isolation layer; a second opening in the dielectric structure, the second opening exposing the top surface of the source drain conductive layer; an isolation structure within the first opening and the second opening, the isolation structure being of a different material than the dielectric structure; the grid electrode conductive openings are positioned in the dielectric structure and are respectively adjacent to the isolation structures, and the grid electrode conductive openings expose partial top surfaces of the first grid electrode structures and partial side walls of the isolation structures; a gate conductive layer within the gate conductive opening, the gate conductive layer electrically connected to the first gate structure.

Optionally, the method further includes: the second gate structures are located on the substrate and cross the fin portions along the second direction, and the source-drain doping layers are located between the adjacent first gate structures and the adjacent second gate structures or between the adjacent second gate structures.

Optionally, the media structure includes: and the first dielectric layer is positioned on the isolation layer, covers the side wall of the first grid structure, exposes the top surface of the first grid structure and is positioned on the second dielectric layer on the first dielectric layer.

Optionally, the material of the first dielectric layer is the same as the material of the second dielectric layer.

Optionally, the material of the isolation structure includes: silicon carbide, dense silicon oxide, silicon carbonitride, or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer comprise: silicon oxide, low K dielectric materials, or ultra low K dielectric materials.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a plurality of fin parts parallel to a first direction; forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part; forming a dielectric structure, an initial first gate structure, a side wall and a plurality of source drain doping layers, wherein the initial first gate structure is located on the isolation layer, the initial first gate structure stretches across the plurality of fin portions along a second direction, the first direction is perpendicular to the second direction, the side wall is located on the side wall of the initial first gate structure, the source drain doping layers are located in the fin portions on two sides of the initial first gate structure, the dielectric structure covers the initial first gate structure, and the top surface of the dielectric structure is higher than the top surface of the initial first gate structure; forming a plurality of initial source drain conductive layers in the medium structure, wherein each initial source drain conductive layer is connected with a plurality of source drain doped layers on one side of the first grid structure, and the top surface of the initial source drain conductive layer is flush with the top surface of the medium structure; removing part of the initial first gate structure and part of the initial source-drain conductive layer to enable the initial first gate structure to form a first gate structure, the initial source-drain conductive layer to form a source-drain conductive layer, the top surface of the first gate structure is higher than that of the source-drain conductive layer, a first opening and a second opening are formed in the dielectric structure, the first opening penetrates through the first gate structure along the first direction to expose part of the isolation layer, and the second opening exposes the top surface of the source-drain conductive layer; forming an isolation structure in the first opening and the second opening, wherein the top surface of the isolation structure is flush with the top surface of the dielectric structure, and the material of the isolation structure is different from that of the dielectric structure; forming a gate conductive opening adjacent to the isolation structure in the dielectric structure, wherein the gate conductive opening exposes a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure; and forming a grid conducting layer in the grid conducting opening, wherein the grid conducting layer is electrically connected with the first grid structure.

Optionally, the initial source-drain conductive layer has a first size along a direction of a normal of the substrate surface; the initial first gate structure has a second dimension in a direction along the substrate surface normal, and a ratio of the first dimension to the second dimension is greater than 3:2.

Optionally, the method for forming the isolation structure includes: forming a layer of spacer material within the first and second openings and a top surface of the dielectric structure; and carrying out planarization treatment on the isolation material layer until the top surface of the dielectric structure is exposed, so as to form the isolation structure.

Optionally, the method for forming the gate conductive layer includes: forming a gate conductive material layer within the gate conductive opening and on top surfaces of the dielectric structure and the isolation structure; and carrying out planarization treatment on the grid conductive material layer until the top surfaces of the dielectric structure and the isolation structure are exposed, and forming the grid conductive layer.

Optionally, in the process of forming the initial first gate structure, the method further includes: and forming a plurality of second gate structures on the substrate, wherein the source drain doping layer is positioned between the initial first gate structure and the second gate structure which are adjacent to each other, or positioned between the second gate structures which are adjacent to each other.

Optionally, the medium structure includes: and the first dielectric layer is positioned on the substrate, covers the side wall of the initial first grid structure, exposes the top surface of the initial first grid structure and is positioned on the second dielectric layer on the first dielectric layer.

Optionally, the material of the first dielectric layer is the same as the material of the second dielectric layer.

Optionally, the material of the isolation structure includes: silicon carbide, dense silicon oxide, silicon carbonitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer comprise: silicon oxide, low K dielectric materials, or ultra low K dielectric materials.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the structure of the technical scheme of the invention comprises a grid electrode conductive opening positioned in the medium structure, wherein the grid electrode conductive opening exposes part of the top surface of the first grid electrode structure and part of the side wall of the isolation structure. The isolation structure is used as a self-aligned film layer of the formed grid conductive opening, so that the forming accuracy of the grid conductive opening is effectively improved, the occurrence of the short circuit problem of a circuit is reduced, and the performance of the finally formed semiconductor structure is improved.

In the forming method of the technical scheme of the invention, an isolation structure is formed in the first opening, the top surface of the isolation structure is higher than that of the first gate structure and is flush with the top surface of a subsequently formed gate conducting layer, and the material of the isolation structure is different from that of the dielectric structure. The isolation structure is used as a self-aligned film layer of the formed grid conductive opening, so that the forming accuracy of the grid conductive opening is effectively improved, the occurrence of the short circuit problem of a circuit is reduced, and the performance of the finally formed semiconductor structure is improved.

Drawings

FIGS. 1 and 2 are schematic structural views of steps in a semiconductor structure formation process;

fig. 3 to fig. 22 are schematic structural diagrams of steps of another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As described in the background, there are still problems with the prior art in the metal gate cut-off process. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 1 and 2 are schematic structural views of steps in a semiconductor structure formation process.

Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a plurality of fins 101 separated from each other, the substrate 100 includes an isolation region A1, a first device region B1 and a second device region B2, the isolation region A1 is located between the first device region B1 and the second device region B2, and the plurality of fins 101 are located in the first device region B1 and the second device region B2, respectively; forming a first dielectric layer 102, a gate structure 103 and a plurality of source-drain doped layers (not shown), wherein the gate structure 103 is located on the substrate 100, the source-drain doped layers are located in the substrate 100 at two sides of the gate structure 103, and the first dielectric layer 102 covers the side wall of the gate structure 103; removing the gate structure 103 on the isolation region A1, and forming a first opening (not labeled) in the first dielectric layer 102; isolation structures 104 are formed within the first openings.

Referring to fig. 2, a second dielectric layer 105 is formed on the gate structure 103 and the isolation structure 104; forming a gate conductive opening (not labeled) in the second dielectric layer 105, wherein the gate conductive opening exposes the top surface of the gate structure 103 located on the first device region B1; a gate conductive layer 106 is formed in the gate conductive opening, and the gate conductive layer 106 is electrically connected to the gate structure 103 located on the first device region B1.

In this embodiment, the isolation structure 104 is formed to effectively isolate the gate structure 103, so that the gate structure 103 can obtain a good profile and the feature size can be reduced.

However, in the process of forming the gate conductive opening in the second dielectric layer 105, since the self-aligned film layer is not used as a reference, the requirement on the alignment accuracy of the photomask is high, so that the formed gate conductive opening can easily expose the top surface (as shown in part a in fig. 2) of the gate structure 103 located on the second device region B2, and the formed gate conductive layer 106 can be simultaneously electrically connected to the gate structure 103 located on the first device region B1 and the gate structure 103 located on the second device region B2, thereby causing a short circuit.

On the basis, the invention provides a semiconductor structure and a forming method thereof, wherein an isolation structure is formed in the first opening, the top surface of the isolation structure is higher than that of the first gate structure and is flush with the top surface of a subsequently formed gate conducting layer, and the material of the isolation structure is different from that of the dielectric structure. The isolation structure is used as a self-aligned film layer of the formed grid conductive opening, so that the forming accuracy of the grid conductive opening is effectively improved, the occurrence of the short circuit problem of a circuit is reduced, and the performance of the finally formed semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to fig. 22 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 3 and 4, fig. 3 isbase:Sub>A top view ofbase:Sub>A semiconductor structure, and fig. 4 isbase:Sub>A cross-sectional view taken along linebase:Sub>A-base:Sub>A in fig. 3, providingbase:Sub>A substrate 200, wherein the substrate 200 hasbase:Sub>A plurality of fins 201 parallel tobase:Sub>A first direction X.

In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown) having a mask layer (not shown) thereon, the mask layer exposing a portion of a top surface of the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form the substrate 200.

In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.

In this embodiment, the fin 201 is made of silicon; in other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

Referring to fig. 5 and 6, fig. 5 is a perspective view of a semiconductor structure, and fig. 6 is a cross-sectional view taken along line B-B in fig. 5. An isolation layer 202 is formed on the substrate, wherein the isolation layer 202 covers a portion of the sidewalls of the fin 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201.

In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; and etching to remove part of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than that of the fin 201.

The isolation layer 202 is made of an insulating material, and the insulating material comprises silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide.

In this embodiment, after the isolation layer 202 is formed, a dielectric structure, an initial first gate structure, a side wall, and a plurality of source-drain doping layers are formed, where the initial first gate structure is located on the isolation layer 202, the initial first gate structure spans a plurality of fin portions along a second direction, the first direction X is perpendicular to the second direction, the side wall is located on the side wall of the initial first gate structure, the source-drain doping layers are located in the fin portions 201 on two sides of the initial first gate structure, the dielectric structure covers the initial first gate structure, and a top surface of the dielectric structure is higher than a top surface of the initial first gate structure. Please refer to fig. 7 to fig. 10.

Referring to fig. 7, a first dummy gate structure 203 is formed on the isolation layer.

In this embodiment, in the process of forming the first dummy gate structure 203, the method further includes: a plurality of second dummy gate structures 204 are formed on the isolation layer 202.

In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 respectively cross over the plurality of fins 201 along the second direction Y.

In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 respectively include: a dummy gate dielectric layer, and a dummy gate layer (not labeled) on the dummy gate dielectric layer.

In this embodiment, the gate dielectric layer is made of silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also adopt silicon oxynitride.

In this embodiment, the material of the dummy gate layer is polysilicon.

In this embodiment, please continue to refer to fig. 7, which further includes: spacers (not shown) are formed on sidewalls of the initial first gate structure 203 and the second gate structure 204.

In this embodiment, the sidewall spacer is made of silicon nitride.

Referring to fig. 8, a plurality of source-drain doping layers 205 are formed in the fin 201, and the source-drain doping layers 205 are located between the first dummy gate structure 203 and the second dummy gate structure 204 which are adjacent to each other, or between the second dummy gate structures 204 which are adjacent to each other.

In this embodiment, the method for forming the source-drain doping layer 205 includes: etching the fin portion 201 by using the first dummy gate structure 203 and the second dummy gate structure 204 as masks, and forming a plurality of source-drain openings (not marked) in the fin portion 201; and forming the source and drain doping layer 205 in the source and drain opening.

Referring to fig. 9, after the source-drain doping layer 205 is formed, a first dielectric layer 206 is formed on the isolation layer 202.

In this embodiment, the first dielectric layer 206 covers sidewalls of the first dummy gate structure 203 and the second dummy gate structure 204, and exposes top surfaces of the first dummy gate structure 203 and the second dummy gate structure 204.

In this embodiment, the first dielectric layer 206 is made of silicon oxide; in other embodiments, the material of the first dielectric layer may also be a low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

Referring to fig. 10, after the first dielectric layer 206 is formed, an initial first gate structure 207 is formed.

In this embodiment, in the process of forming the initial first gate structure 207, the method further includes: several second gate structures 208 are formed.

In this embodiment, the method for forming the initial first gate structure 207 and the second gate structure 208 includes: removing the first dummy gate structure 203 and the second dummy gate structure 204, and forming a first gate opening and a plurality of second gate openings (not labeled) in the first dielectric layer 206; the first gate structure 207 is formed within the first gate opening and the second gate structure 208 is formed within the second gate opening.

In this embodiment, the initial first gate structure 207 and the second gate structure 208 include: the gate structure comprises a gate dielectric layer, a gate layer located on the gate dielectric layer, and a mask layer (not labeled) located on the gate layer.

The material of the gate layer comprises a metal comprising: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the gate layer is tungsten.

Referring to fig. 11, after forming the initial first gate structure 207, a second dielectric layer 209 is formed on the first dielectric layer 206 and the initial first gate structure 207.

In this embodiment, the first dielectric layer 206 and the second dielectric layer 209 constitute a dielectric structure.

In this embodiment, the second dielectric layer 209 is made of silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

Referring to fig. 12, after the second dielectric layer 209 is formed, a plurality of initial source drain conductive layers 210 are formed in the dielectric structure, each of the initial source drain conductive layers 210 is connected to the plurality of source drain doping layers 205 on one side of the first gate structure 207, and a top surface of the initial source drain conductive layer 210 is higher than a top surface of the first gate structure 207.

In this embodiment, the method for forming the initial source/drain conductive layer 210 includes: forming a plurality of source-drain conductive openings (not shown) in the dielectric structure, wherein each source-drain conductive opening exposes a plurality of source-drain doping layers 205 on one side of the initial first gate structure 207; and forming the initial source drain conductive layer 210 in the source drain conductive opening, wherein the initial source drain conductive layer 210 fills the source drain conductive opening.

In this embodiment, the initial source-drain conductive layer 210 has a first size d1 along the direction of the normal of the substrate surface; the initial first gate structure 207 has a second dimension d2 along a direction of the substrate surface normal, and a ratio of the first dimension d1 to the second dimension d2 is greater than 3:2.

In this embodiment, after forming the initial source drain conductive layer 210, the method further includes: removing a part of the initial first gate structure 207 and a part of the initial source drain conductive layer 210, so that the initial first gate structure 207 forms a first gate structure, the initial source drain conductive layer 210 forms a source drain conductive layer, the top surface of the first gate structure is higher than the top surface of the source drain conductive layer, and a first opening and a second opening are formed in the dielectric structure, the first opening penetrates through the first gate structure along the first direction X to expose a part of the isolation layer 202, and the second opening exposes the top surface of the source drain conductive layer. Please refer to fig. 13 to fig. 17 for a specific forming process.

Referring to fig. 13 to 15, fig. 13 is a top view of a semiconductor structure, fig. 14 is a schematic cross-sectional view taken along line C-C of fig. 13, and fig. 15 is a schematic cross-sectional view taken along line D-D of fig. 14, in which a portion of the initial first gate structure 207 is removed, and an initial first opening 211 is formed in the dielectric structure.

In this embodiment, the mask layer in the initial first gate structure 207 is specifically removed. In the process of removing the mask layer, the adjacent initial source/drain conductive layer 210 can be used as a self-aligned film layer, thereby effectively reducing the difficulty of the etching process.

Referring to fig. 16 and 17, the view directions of fig. 16 and 14 are the same, and the view directions of fig. 17 and 15 are the same, after the initial first opening 211 is formed, the exposed gate layer in the initial first gate structure 207 is removed until the top surface of the isolation layer 202 is exposed, so that the initial first gate structure 207 forms a first gate structure 216, and the initial first opening 211 forms the first opening 212.

In this embodiment, in the process of removing the exposed gate layer in the initial first gate structure 207, the method further includes: removing a part of the initial source-drain conductive layer 210 to form a source-drain conductive layer 213 and a second opening 214, where the second opening 214 is located at two sides of the first opening 212, the second opening 214 exposes the top surface of the source-drain conductive layer 213, and the bottom surface of the second opening 214 is lower than the top surface of the first gate structure 207.

Referring to fig. 18 and 19, after the first opening 212 and the second opening 214 are formed, an isolation structure 215 is formed in the first opening 212 and the second opening 214, a top surface of the isolation structure 215 is flush with a top surface of the dielectric structure, and a material of the isolation structure 215 is different from a material of the dielectric structure.

In the present embodiment, by forming the isolation structure 215 in the first opening 212, the top surface of the isolation structure 215 is higher than the top surface of the first gate structure 216 and is flush with the top surface of the subsequently formed gate conductive layer, and the material of the isolation structure 215 is different from that of the dielectric structure. The isolation structure 215 is used as a self-aligned film layer of a subsequently formed gate conductive opening, so that the forming accuracy of the gate conductive opening is effectively improved, the occurrence of a short circuit problem is reduced, and the performance of a finally formed semiconductor structure is improved.

In this embodiment, the method for forming the isolation structure 215 includes: forming a layer of spacer material (not shown) within the first opening 212 and the second opening 214, and a top surface of the dielectric structure; the isolation material layer is planarized until the top surface of the dielectric structure is exposed, forming the isolation structure 215.

The material of the isolation structure 215 includes: silicon carbide, dense silicon oxide, silicon carbonitride (SiBCN), or silicon oxynitride. In this embodiment, the material of the isolation structure 215 is silicon carbide.

Referring to fig. 20 and 21, fig. 20 is a top view of a semiconductor structure, fig. 21 is a cross-sectional view taken along line E-E of fig. 20, after forming the isolation structure 215, a gate conductive opening 217 is formed in the dielectric structure adjacent to the isolation structure 215, and the gate conductive opening 217 exposes a portion of the top surface of the first gate structure 216 and a portion of the sidewall of the isolation structure 215.

In the embodiment, the isolation structure 215 is used as a self-aligned film layer for forming the gate conductive opening 217, so that the forming accuracy of the gate conductive opening 217 is effectively improved, and the occurrence of a short circuit problem is reduced, thereby improving the performance of the finally formed semiconductor structure.

Referring to fig. 22, fig. 22 and fig. 21 are oriented in the same direction, a gate conductive layer 218 is formed in the gate conductive opening 217, and the gate conductive layer 218 is electrically connected to the first gate structure 216.

In this embodiment, the method for forming the gate conductive layer 218 includes: forming a layer of gate conductive material (not shown) within the gate conductive opening 217 and on top surfaces of the dielectric structure and the isolation structure 215; the gate conductive material layer is planarized until the top surfaces of the dielectric structures and the isolation structures 215 are exposed, forming the gate conductive layer 218.

In this embodiment, the planarization process employs a chemical mechanical polishing process.

Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 22, including: the structure comprises a substrate 200, wherein the substrate 200 is provided with a plurality of fin parts 201 parallel to a first direction X; an isolation layer 202 located on the substrate 200, wherein the isolation layer 202 covers a portion of the sidewall of the fin 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201; a first gate structure 216 on the isolation layer 202, the first gate structure 216 crossing over the plurality of fins 201 along a second direction Y, the first direction X being perpendicular to the second direction Y; a sidewall on a sidewall of the first gate structure 216; the source-drain doping layer 205 is positioned in the fin parts on two sides of the first gate structure 216; a plurality of source-drain conductive layers 213, the source-drain conductive layers 213 being connected to the plurality of source-drain doping layers 205 on one side of the first gate structure 216, the top surface of the first gate structure 216 being higher than the top surface of the source-drain conductive layers 213; a dielectric structure located on the isolation layer 202, where the dielectric structure covers the first gate structure 216 and the source/drain conductive layer 213, and a top surface of the dielectric structure is higher than top surfaces of the first gate structure 216 and the source/drain conductive layer 213; a first opening 212 in the dielectric structure, wherein the first opening 212 penetrates the first gate structure 216 along the first direction X and exposes a portion of the isolation layer 202; a second opening 214 located in the dielectric structure, where the second opening 214 exposes a top surface of the source-drain conductive layer 213; an isolation structure 215 located within the first opening 212 and the second opening 214, the isolation structure 215 being of a different material than the dielectric structure; a gate conductive opening 217 within the dielectric structure and adjacent to the isolation structure 215, respectively, the gate conductive opening 217 exposing a portion of the top surface of the first gate structure 216 and a portion of the sidewall of the isolation structure 215; a gate conductive layer 218 within the gate conductive opening 217, the gate conductive layer 218 being electrically connected to the first gate structure 216.

In the present embodiment, the gate conductive opening 217 exposes a portion of the top surface of the first gate structure 216 and a portion of the sidewall of the isolation structure 215. By using the isolation structure 215 as a self-aligned film layer of the formed gate conductive opening 217, the accuracy of forming the gate conductive opening 217 is effectively improved, and the occurrence of short circuit problem is reduced, thereby improving the performance of the finally formed semiconductor structure

In this embodiment, the method further includes: the second gate structures 208 are located on the substrate 200, the second gate structures 208 cross the fins 201 along the second direction Y, and the source-drain doping layer 205 is located between the first gate structure 216 and the second gate structure 208 which are adjacent to each other, or located between the second gate structures 208 which are adjacent to each other.

In this embodiment, the media structure includes: a first dielectric layer 206 disposed on the isolation layer 202, wherein the first dielectric layer 206 covers sidewalls of the first gate structure 216 and exposes a top surface of the first gate structure 216 and a second dielectric layer 209 disposed on the first dielectric layer 206.

In this embodiment, the material of the first dielectric layer 206 is the same as the material of the second dielectric layer 209.

In this embodiment, the material of the isolation structure 215 includes: silicon carbide, dense silicon oxide, silicon carbonitride or silicon oxynitride; the material of the first dielectric layer 206 and the material of the second dielectric layer 209 include: silicon oxide, low K dielectric materials, or ultra low K dielectric materials.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A semiconductor structure, comprising:

the substrate is provided with a plurality of fin parts parallel to a first direction;

the isolation layer is positioned on the substrate, covers partial side walls of the fin parts, and the top surfaces of the isolation layer are lower than the top surfaces of the fin parts;

the first grid electrode structure is positioned on the isolation layer and spans the plurality of fin parts along a second direction, and the first direction is vertical to the second direction;

the side wall is positioned on the side wall of the first grid structure;

the source-drain doping layers are positioned in the fin parts on two sides of the first grid structure;

the source-drain conducting layers are connected with the source-drain doping layers on one side of the first grid structure, and the top surface of the first grid structure is higher than that of the source-drain conducting layers;

the dielectric structure is positioned on the isolation layer, covers the first grid structure and the source drain conducting layer, and is higher than the top surfaces of the first grid structure and the source drain conducting layer;

a first opening in the dielectric structure, the first opening penetrating the first gate structure along the first direction and exposing a portion of the isolation layer;

a second opening in the dielectric structure, the second opening exposing the top surface of the source drain conductive layer;

an isolation structure within the first opening and the second opening, the isolation structure being of a different material than the dielectric structure;

the grid electrode conductive openings are positioned in the dielectric structure and are respectively adjacent to the isolation structures, and the grid electrode conductive openings expose partial top surfaces of the first grid electrode structures and partial side walls of the isolation structures;

a gate conductive layer within the gate conductive opening, the gate conductive layer electrically connected to the first gate structure.

2. The semiconductor structure of claim 1, further comprising: the second gate structures are located on the substrate and cross the fin portions along the second direction, and the source-drain doping layers are located between the adjacent first gate structures and the adjacent second gate structures or between the adjacent second gate structures.

3. The semiconductor structure of claim 1, wherein the dielectric structure comprises: and the first dielectric layer is positioned on the isolation layer, covers the side wall of the first grid structure, exposes the top surface of the first grid structure and is positioned on the second dielectric layer on the first dielectric layer.

4. The semiconductor structure of claim 3, wherein a material of the first dielectric layer is the same as a material of the second dielectric layer.

5. The semiconductor structure of claim 3, wherein the isolation structure comprises a material comprising: silicon carbide, dense silicon oxide, silicon carbonitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer comprise: silicon oxide, low K dielectric materials, or ultra low K dielectric materials.

6. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a plurality of fin parts parallel to a first direction;

forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part;

forming a dielectric structure, an initial first gate structure, a side wall and a plurality of source drain doping layers, wherein the initial first gate structure is located on the isolation layer, the initial first gate structure stretches across the plurality of fin portions along a second direction, the first direction is perpendicular to the second direction, the side wall is located on the side wall of the initial first gate structure, the source drain doping layers are located in the fin portions on two sides of the initial first gate structure, the dielectric structure covers the initial first gate structure, and the top surface of the dielectric structure is higher than the top surface of the initial first gate structure;

forming a plurality of initial source-drain conductive layers in the dielectric structure, wherein each initial source-drain conductive layer is connected with the source-drain doped layers on one side of the first gate structure, and the top surface of the initial source-drain conductive layer is flush with the top surface of the dielectric structure;

removing part of the initial first gate structure and part of the initial source-drain conductive layer to enable the initial first gate structure to form a first gate structure, the initial source-drain conductive layer to form a source-drain conductive layer, the top surface of the first gate structure is higher than that of the source-drain conductive layer, a first opening and a second opening are formed in the dielectric structure, the first opening penetrates through the first gate structure along the first direction to expose part of the isolation layer, and the second opening exposes the top surface of the source-drain conductive layer;

forming an isolation structure in the first opening and the second opening, wherein the top surface of the isolation structure is flush with the top surface of the dielectric structure, and the material of the isolation structure is different from that of the dielectric structure;

forming a gate conductive opening adjacent to the isolation structure in the dielectric structure, wherein the gate conductive opening exposes a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure;

and forming a grid conducting layer in the grid conducting opening, wherein the grid conducting layer is electrically connected with the first grid structure.

7. The method for forming a semiconductor structure according to claim 6, wherein the initial source drain conductive layer has a first size along a direction of a normal of the surface of the substrate; the initial first gate structure has a second dimension in a direction along the normal to the surface of the substrate, and a ratio of the first dimension to the second dimension is greater than 3:2.

8. The method of forming a semiconductor structure of claim 6, wherein the method of forming the isolation structure comprises: forming a layer of spacer material within the first and second openings and a top surface of the dielectric structure; and carrying out planarization treatment on the isolation material layer until the top surface of the dielectric structure is exposed, so as to form the isolation structure.

9. The method of forming a semiconductor structure of claim 6, wherein the method of forming the gate conductive layer comprises: forming a gate conductive material layer within the gate conductive opening and on top surfaces of the dielectric structure and the isolation structure; and carrying out planarization treatment on the grid conductive material layer until the top surfaces of the dielectric structure and the isolation structure are exposed, and forming the grid conductive layer.

10. The method of forming a semiconductor structure of claim 6, further comprising, during the forming of the initial first gate structure: and forming a plurality of second gate structures on the substrate, wherein the source-drain doping layer is positioned between the adjacent initial first gate structure and the second gate structure or between the adjacent second gate structures.

11. The method of forming a semiconductor structure of claim 6, wherein the dielectric structure comprises: and the first dielectric layer is positioned on the substrate, covers the side wall of the initial first grid structure, exposes the top surface of the initial first grid structure and is positioned on the second dielectric layer.

12. The method of forming a semiconductor structure of claim 11, wherein a material of the first dielectric layer is the same as a material of the second dielectric layer.

13. The method of forming a semiconductor structure of claim 12, wherein the isolation structure comprises a material comprising: silicon carbide, dense silicon oxide, silicon carbonitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer comprise: silicon oxide, low K dielectric materials, or ultra low K dielectric materials.

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