CN114188318A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114188318A
CN114188318A CN202010962082.3A CN202010962082A CN114188318A CN 114188318 A CN114188318 A CN 114188318A CN 202010962082 A CN202010962082 A CN 202010962082A CN 114188318 A CN114188318 A CN 114188318A
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layer
dielectric layer
forming
opening
interlayer dielectric
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韩秋华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A semiconductor structure and a method of forming the same, wherein the semiconductor structure comprises: a substrate having an interlayer dielectric layer thereon; a gate structure on the substrate; the source-drain doping layer is positioned in the substrate at two sides of the grid structure; the first opening is positioned in the interlayer dielectric layer and exposes the top of the grid structure; the first inner side walls are positioned on the side walls of the first opening, and a first gap is formed between the first inner side walls; the second opening is positioned in the interlayer dielectric layer and exposes the top of the source-drain doping layer; the conducting layer is positioned in the second opening, and the top surface of the conducting layer is lower than that of the interlayer dielectric layer; and the second inner side walls are positioned on the side walls of the second openings exposed by the conductive layers, and second gaps are formed between the second inner side walls. According to the semiconductor structure provided by the embodiment of the invention, the short circuit problem between the first interconnection layer and the conductive layer and between the second interconnection layer and the grid structure is avoided, and the electrical property and the stability of the semiconductor structure are improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
Scaling of feature sizes in integrated circuits has been a driving force behind the growing semiconductor industry over the last decades. Scaling to smaller and smaller feature sizes enables increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing transistor size allows for an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the urging for larger capacities is not without problems. The necessity to optimize the performance of each device becomes increasingly significant.
In the fabrication of integrated circuit devices, such as multi-gate transistors, are becoming more common as device dimensions continue to shrink. In conventional processes, multi-gate transistors are typically fabricated on a silicon substrate or a silicon-on-insulator substrate.
Scaling down the size of multi-gate transistors is not without its consequences, as the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints of the photolithographic process used to pattern the building blocks become difficult to overcome. The electrical performance of the prior art multi-gate transistors is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the device comprises a substrate, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the substrate is provided with an interlayer dielectric layer; the grid structure is positioned on the substrate, and the top surface of the grid structure is lower than that of the interlayer dielectric layer; the source-drain doping layers are positioned in the substrate on two sides of the grid structure; a first opening in the interlayer dielectric layer, the first opening exposing a top surface of the gate structure; the first inner side walls are positioned on the side walls of the first opening, and a first gap is formed between the first inner side walls; the second opening is positioned in the interlayer dielectric layer and exposes the top surface of the source-drain doping layer; the conducting layer is positioned in the second opening, and the top surface of the conducting layer is lower than that of the interlayer dielectric layer; and the second inner side walls are positioned on the side walls of the second openings exposed by the conducting layer, and second gaps are formed between the second inner side walls.
Optionally, the method further includes: a first interconnect layer located within the first void and on top of the gate structure; a second interconnect layer located within the second void and on top of the conductive layer.
Optionally, the method further includes: and the second dielectric layer is positioned on the interlayer dielectric layer, and part of the first interconnection layer and part of the second interconnection layer are also positioned in the second dielectric layer.
Optionally, the material of the first inner sidewall spacer includes silicon nitride, silicon oxycarbide, or nitrogen-doped silicon carbide.
Optionally, the material of the second inner sidewall spacer includes silicon nitride, silicon oxycarbide, or nitrogen-doped silicon carbide.
Optionally, the material of the second dielectric layer is different from the material of the first inner sidewall, and the material of the second dielectric layer is different from the material of the second inner sidewall, and the material of the second dielectric layer includes a low-k dielectric material, an ultra-low-k dielectric material, or silicon oxide.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with an interlayer dielectric layer, a gate structure positioned in the interlayer dielectric layer and source drain doping layers positioned on two sides of the gate structure in the substrate; etching the grid structure until the top surface of the grid structure is lower than the top surface of the interlayer dielectric layer, and forming a first opening in the interlayer dielectric layer; forming first inner side walls on the side walls of the first opening, wherein first gaps are formed among the first inner side walls; forming a first dielectric layer in the first gap; etching the interlayer dielectric layer on the source-drain doped layer until the top surface of the source-drain doped layer is exposed to form a second opening; forming a conductive layer in the second opening, wherein the top surface of the conductive layer is lower than that of the interlayer dielectric layer; and forming second inner side walls on the side walls of the second openings exposed by the conductive layer, wherein second gaps are formed between the second inner side walls.
Optionally, the method further includes: forming a first interconnection layer in the first gap, wherein the first interconnection layer is positioned at the top of the gate structure; a second interconnect layer is formed within the second void, and the second interconnect layer is located on top of the conductive layer.
Optionally, before forming the first interconnect layer and the second interconnect layer, the method further includes: and forming a second dielectric layer on the interlayer dielectric layer, wherein the second dielectric layer is also filled in the second gap.
Optionally, the step of forming a first interconnect layer in the first void includes: etching the second dielectric layer and the first dielectric layer in the first gap until the top of the grid structure is exposed, and forming a third opening in the second dielectric layer; a first interconnect layer is formed within the first void and the third opening.
Optionally, the step of forming a second interconnect layer in the second void includes: etching the second dielectric layer until the top of the conductive layer is exposed, and forming a fourth opening in the second dielectric layer; forming a second interconnect layer within the second void and the fourth opening.
Optionally, the method for forming the conductive layer in the second opening includes: forming an initial conducting layer in the second opening, wherein the top surface of the initial conducting layer is flush with the top surface of the interlayer dielectric layer; and etching the initial conducting layer until the top surface of the initial conducting layer is lower than that of the interlayer dielectric layer to form the conducting layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the first inner side walls are formed on the side walls of the first openings on the grid structure, first gaps are formed among the first inner side walls, the first gaps provide space for forming a first interconnection layer on the grid structure subsequently, and due to the existence of the first inner side walls, the distance between the first interconnection layer formed subsequently and the conducting layer is increased, so that the first interconnection layer and the conducting layer are prevented from being short-circuited; similarly, a second inner side wall is formed on the side wall of the second opening exposed by the conducting layer, a second gap is formed between the second inner side walls, the second gap provides a space for forming a second interconnection layer on the conducting layer subsequently, and after the second interconnection layer is formed in the second gap subsequently, due to the existence of the second inner side wall, the distance between the second interconnection layer and the grid structure is increased, short circuit between the second interconnection layer and the grid structure is avoided, and therefore the electrical performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment;
fig. 3 to 19 are schematic structural diagrams corresponding to steps of a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
The electrical performance of the MOSFET of the COAG structure in the prior art still remains to be improved. The following detailed description will be made in conjunction with the accompanying drawings.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Referring to fig. 1, the semiconductor structure includes: a substrate 100; a fin 101 on the substrate 100; a gate structure 102 spanning the fin 101; the side wall 103 is positioned on the side wall of the gate structure 102; the source-drain doping layer 104 is positioned in the fin portion 101 on two sides of the gate structure 102; a conducting layer 105 positioned on the top of the source drain doping layer 104; a first hard mask layer 106 on a top surface of the gate structure 102; the second hard mask layer 107 is positioned on the top of the conductive layer 105 and also covers the top surface of the side wall 103; a dielectric layer 108 on the first hard mask layer 106 and the second hard mask layer 107; a second interconnect layer 109 within the second hard mask layer 107 and on top of the conductive layer 105.
The inventors found that, in the above-described embodiment, after the second interconnect layer 109 is formed, since the distance between the second interconnect layer 109 and the gate structure 102 is small (refer to a dotted circle portion in fig. 1), short circuit between the second interconnect layer 109 and the gate structure 102 is likely to occur during electrical connection, thereby affecting the performance of the semiconductor structure.
Another method for forming a semiconductor structure is described in detail below with reference to the accompanying drawings.
FIG. 2 is a cross-sectional view of a semiconductor structure in another embodiment.
Referring to fig. 2, the semiconductor structure includes: a substrate 200; a fin 201 on the substrate 200; a gate structure 202 spanning the fin 201; the side wall 203 is positioned on the side wall of the gate structure 202, and the top of the side wall 203 is higher than the top of the gate structure 202; the source-drain doping layer 204 is positioned in the fin portion 201 on two sides of the gate structure 202; the conducting layer 205 is positioned at the top of the source drain doping layer 204; a first hard mask layer 206 on a top surface of the gate structure 202; a second hard mask layer 207 on the top surface of the conductive layer 205; a dielectric layer 208 on the first hard mask layer 206, the second hard mask layer 207 and the sidewall spacers 203; a first interconnect layer 209 is located in the first hard mask layer 206 and on top of the gate structure 202 between the source-drain doped layers 204.
The inventors found that, in the above-described embodiment, after the first interconnect layer 209 is formed, since the distance between the first interconnect layer 209 and the conductive layer 205 is small, a short circuit (refer to a dotted-line portion in fig. 2) between the first interconnect layer 209 and the conductive layer 205 is likely to occur during electrical connection, thereby affecting the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, where a first inner sidewall is formed on a sidewall of a first opening at the top of a gate structure, a first gap is formed between the first inner sidewalls, a second inner sidewall is formed on a sidewall of a second opening exposed at the top of a conductive layer, a second gap is formed between the second inner sidewalls, a first interconnection layer is subsequently formed in the first gap, and a second interconnection layer is formed in the second gap, where a distance between the first interconnection layer and the conductive layer is increased due to the presence of the first inner sidewall between the first interconnection layer and the conductive layer, so as to avoid a short circuit between the first interconnection layer and the conductive layer; in a similar way, due to the existence of the second inner side wall between the second interconnection layer and the grid structure, the distance between the second interconnection layer and the grid structure is increased, short circuit between the second interconnection layer and the grid structure is avoided, and the electrical performance of the semiconductor structure is favorably improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 19 are schematic structural diagrams corresponding to steps of a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 3, a substrate 300 is provided.
In this embodiment, the base 300 includes a substrate 301 and a plurality of fins 302 separately arranged on the substrate 301, and the fins 302 extend along a first direction X.
In other embodiments, the fin portion may not be formed on the substrate 301.
In this embodiment, the substrate 301 is made of silicon.
In other embodiments, the material of the substrate 301 may also be germanium, silicon germanium, gallium arsenide, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or other semiconductor materials.
In this embodiment, the fin portion 302 is made of silicon; in other embodiments, the material of the fin 302 may also be a semiconductor material such as silicon germanium.
In this embodiment, the method of forming the fin portion 302 includes: forming a fin material film (not shown) on the substrate 301; forming a patterned layer (not shown) on the fin material film; and etching the fin material film by using the patterning layer as a mask until the surface of the substrate 301 is exposed to form a fin 302.
In this embodiment, an isolation structure 303 is further formed on the substrate 301, and the isolation structure 303 covers a portion of the sidewall of the fin 302.
In this embodiment, the isolation structure 303 is made of silicon oxide; in other embodiments, the material of the isolation structure 303 may further include one or more of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.
In this embodiment, the method for forming the isolation structure 303 includes: forming an isolation structure film (not shown) covering the fin 302 on the substrate 301; and etching back the isolation structure film to form the isolation structure 303.
The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.
After the isolation structure 303 is formed, an interlayer dielectric layer, a gate structure and source-drain doped layers located in the fin portions 302 on two sides of the gate structure are formed on the substrate 301.
The specific steps of forming the interlayer dielectric layer, the grid structure and the source-drain doped layer comprise:
referring to fig. 4, a dummy gate structure 304 is formed on the substrate 300.
In this embodiment, a dummy gate structure 304 is formed on the substrate 301 across the fin 302.
In this embodiment, the dummy gate structure 304 includes: a dummy gate dielectric layer 305 on the fin portion 302, a dummy gate layer 306 on the dummy gate dielectric layer 305, and a protection layer 307 on the dummy gate layer 306.
In this embodiment, the dummy gate dielectric layer 305 is made of silicon oxide.
In this embodiment, the material of the dummy gate layer 306 is polysilicon.
In this embodiment, the material of the protection layer 307 includes: silicon nitride or silicon oxide; in other embodiments, the material of the protection layer 307 may also be one or more of silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.
In this embodiment, the protection layer 307 protects the dummy gate layer 306 during the subsequent formation of the source-drain doping layer, and serves as a stop layer for the subsequent planarization of the interlayer dielectric layer.
In this embodiment, a sidewall spacer 308 is further formed on the sidewalls of the dummy gate layer 306 and the protection layer 307.
In this embodiment, the sidewall spacers 308 are made of silicon nitride; in other embodiments, the material of the sidewall spacers 308 may also be one or more combinations of silicon oxide, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.
The side wall 308 is used for defining the position of a source-drain doping layer formed subsequently, and the side wall 308 is used for protecting the side wall of the pseudo gate layer 306, so that the phenomenon that the subsequently formed gate layer has appearance defects and affects the electrical performance of the semiconductor structure is avoided.
Referring to fig. 5, the source-drain doping layers 309 are formed in the substrate 300 at two sides of the dummy gate structure 304.
In this embodiment, the fin portion 302 on both sides of the dummy gate structure 304 is etched, and a source-drain doping layer 309 is formed in the fin portion 302.
The source drain doped layer 309 has source drain dopant ions.
The process for forming the source-drain doping layer 309 comprises an epitaxial growth process; the process of doping the source-drain doping ions in the source-drain doping layer is an in-situ doping process.
When the semiconductor device is a P-type device, the materials of the source-drain doping layer 309 include: silicon, germanium, or silicon germanium; the source and drain doped ions are P-type ions including boron ions and BF2-Ions or indium ions; when the semiconductor device is an N-type device, the source-drain doping layer 309 comprises: silicon, gallium arsenide, or indium gallium arsenide; the source and drain doped ions are N-type ions and comprise phosphorus ions or arsenic ions.
In this embodiment, the semiconductor device is a P-type device, the source-drain doping layer 309 is made of silicon, and the source-drain doping ions are boron ions. In other embodiments, the semiconductor device is an N-type device, the source-drain doping layer 309 is made of silicon, and the source-drain doping ions are phosphorus ions.
Referring to fig. 6, an interlayer dielectric layer 310 is formed on the substrate 300 and on the source-drain doping layer 309, and the interlayer dielectric layer 310 exposes the top surface of the dummy gate structure 304.
In this embodiment, the interlayer dielectric layer 310 is formed on the substrate 301 and the source-drain doping layer 309, and the interlayer dielectric layer 310 covers the sidewall of the dummy gate structure 304 and exposes the top surface of the protection layer 307.
In this embodiment, the method for forming the interlayer dielectric layer 310 includes: forming an interlayer dielectric material layer (not shown) on the substrate 301 and the source-drain doping layer 309, wherein the interlayer dielectric material layer covers the top surface of the dummy gate structure 304; and performing planarization treatment on the interlayer dielectric material layer until the top surface of the protection layer 307 is exposed, so as to form the interlayer dielectric layer 310.
In this embodiment, the interlayer dielectric layer 310 is made of silicon oxide; in other embodiments, the material of the interlayer dielectric layer 310 may also be a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).
In this embodiment, the forming process of the interlayer dielectric layer 310 is a chemical vapor deposition process; in other embodiments, the forming process of the interlayer dielectric layer 310 may also be one or more of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 7, the dummy gate structure 304 is etched away until the surface of the substrate 300 is exposed, forming a gate opening 311.
In this embodiment, the protection layer 307, the dummy gate layer 306 and the dummy gate dielectric layer 305 are removed, and the gate opening 311 is formed between the sidewalls 308.
The process of removing the dummy gate structure 304 includes a dry etching process or a wet etching process.
Referring to fig. 8, a gate structure 312 is formed in the gate opening 311, and a top surface of the gate structure 312 is flush with a top surface of the interlayer dielectric layer 310.
In this embodiment, the gate structure 312 includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the gate dielectric layer is made of a high-K dielectric material, such as: oxide-Al2O3，HfO2，Ta2O5，TiO2，ZrO2And the like.
In other embodiments, the material of the gate dielectric layer may further include other dielectric materials with a dielectric constant higher than 3.9.
In this embodiment, the material of the gate layer is a metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.
In this embodiment, the method for forming the gate structure 312 includes: forming the gate dielectric layer on the sidewall and the bottom of the gate opening 311, forming an initial gate material layer on the gate dielectric layer, and planarizing the initial gate material layer until the top surface of the gate material layer is flush with the top of the interlayer dielectric layer 310, thereby forming the gate structure 312.
Referring to fig. 9, the gate structure 312 is etched until the top surface of the gate structure 312 is lower than the top surface of the interlayer dielectric layer 310, and a first opening 320 is formed in the interlayer dielectric layer 310.
In this embodiment, the first openings 320 are formed between the sidewalls 308.
In this embodiment, the depth of the first opening 320 is 100 to 500 nm. If the depth of the first opening 320 is too deep, the gate structure 312 removed by etching is too much, resulting in a higher resistance of the gate structure; if the depth of the first opening 320 is too shallow, the first inner sidewall 321 formed on the sidewall of the first opening 320 is too short to protect.
In this embodiment, the method for etching the gate structure 312 is dry etching.
Referring to fig. 10, after forming the first opening 320, first inner sidewalls 321 are formed on sidewalls of the first opening 320 (refer to fig. 9), and a first gap 322 is formed between the first inner sidewalls 321.
In this embodiment, the first voids 322 provide space for a subsequent formation of a first interconnect layer on the gate structure 312.
In this embodiment, the first inner sidewall spacers 321 are made of silicon nitride; in other embodiments, the material of the first inner sidewall spacers 321 may also be silicon oxycarbide or nitrogen-doped silicon carbide.
In this embodiment, the method for forming the first inner sidewall 321 is a chemical vapor deposition method; in other embodiments, the first inner sidewalls 321 may also be formed by a physical vapor deposition method or an atomic layer deposition method.
In this embodiment, the thickness of the first inner sidewall 321 along the extending direction of the fin 302 is 2 to 15 nm. If the thickness of the first inner sidewall 321 is too small, the distance between the subsequently formed first interconnection layer and the conductive layer cannot be effectively increased, and short circuit still occurs between the first interconnection layer and the conductive layer; if the thickness of the first inner sidewalls 321 is too large, the width of the first gaps 322 between the first inner sidewalls 321 along the extending direction of the fin 302 is small, and the width of the first interconnect layer formed in the first gaps 322 is small, which results in a large resistance of the interconnect structure. Therefore, the thickness of the first inner sidewall 321 along the extending direction of the fin 302 is in a range of 2 to 15 nm.
In this embodiment, the first inner sidewall spacers 321 are formed on the sidewalls of the first opening 320 at the top of the gate structure 312, and when a first interconnection layer is formed in the first gap 322 between the first inner sidewall spacers 321 subsequently, due to the presence of the first inner sidewall spacers 321, the distance between the first interconnection layer and the conductive layer formed on the source-drain doping layer subsequently is increased, and the possibility of short circuit is reduced, thereby facilitating the improvement of the performance of the semiconductor structure.
Referring to fig. 11, a first dielectric layer 323 is formed within the first voids 322.
In this embodiment, the first dielectric layer 323 is made of silicon oxide.
In this embodiment, the method for forming the first dielectric layer 323 includes: filling the first gap 322 with the first dielectric layer film (not shown), wherein the first dielectric layer film further covers the interlayer dielectric layer 310, the sidewall 308 and the top surface of the first inner sidewall 321; and performing planarization treatment on the first dielectric layer film until the top surface of the first dielectric layer film is flush with the top surface of the interlayer dielectric layer 310, and forming a first dielectric layer 323 in the first gap 322.
In this embodiment, the method for forming the first dielectric layer film is a chemical vapor deposition method; in other embodiments, the first dielectric layer film may also be formed by physical vapor deposition or atomic layer deposition.
In this embodiment, a chemical mechanical polishing process is used to planarize the first dielectric layer film.
Referring to fig. 12, the interlayer dielectric layer 310 on the source-drain doped layer 309 is etched until the top surface of the source-drain doped layer 309 is exposed, so as to form a second opening 330.
In this embodiment, the second opening 330 provides a space for a conductive layer formed on the source-drain doping layer 309.
Referring to fig. 13, a conductive layer 331 is formed in the second opening 330, and a top surface of the conductive layer 331 is lower than a top surface of the interlayer dielectric layer 310.
In this embodiment, the method for forming the conductive layer 331 includes: forming an initial conductive layer (not shown) within the second opening 330, a top surface of the initial conductive layer being flush with a top surface of the interlayer dielectric layer 310; and etching the initial conducting layer until the top surface of the initial conducting layer is lower than the top surface of the interlayer dielectric layer 310 to form the conducting layer 331.
In this embodiment, the conductive layer 331 is made of metal, including copper, tungsten, or aluminum.
In this embodiment, the process of forming the conductive layer 331 is an electrochemical plating method; in other embodiments, the conductive layer 331 may also be formed by a physical vapor deposition method.
The method for etching the initial conducting layer comprises one or two of dry etching and wet etching processes.
In this embodiment, the conductive layer 331 is used to electrically connect the source/drain doped layer 309 with the outside in the following step.
Referring to fig. 14, second inner sidewalls 332 are formed on the sidewalls of the second opening 330 (refer to fig. 13) exposed by the conductive layer 331, and a second gap 333 is formed between the second inner sidewalls 332.
In this embodiment, the second void 333 provides a space for a second interconnect layer to be formed subsequently on the conductive layer 331.
In this embodiment, the second inner sidewall 332 is made of silicon nitride; in other embodiments, the material of the second inner sidewall spacers 332 may also be silicon oxycarbide or nitrogen-doped silicon carbide.
In this embodiment, the method for forming the second inner sidewall 332 is a chemical vapor deposition method; in other embodiments, the second inner sidewall 332 may also be formed by a physical vapor deposition method or an atomic layer deposition method.
In this embodiment, the thickness of the second inner sidewall 332 in the extending direction of the fin 302 is 2 to 15 nm. If the thickness of the second inner sidewall 332 is too small, the distance between the subsequently formed second interconnection layer and the gate structure cannot be effectively increased, and short circuit still occurs between the second interconnection layer and the gate structure; if the thickness of the second inner sidewalls 332 is too large, the width of the second gap 333 between the second inner sidewalls 332 along the extending direction of the fin 302 is small, and the width of a second interconnect layer subsequently formed in the second gap 333 is small, resulting in a large resistance of the interconnect structure. Therefore, the thickness of the second inner sidewall 332 along the extending direction of the fin 302 is 2 to 15 nm.
In this embodiment, when the second inner sidewall 332 is formed on the sidewall of the second opening 330 and the second interconnection layer is formed in the second gap 333 between the second inner sidewalls 332, the second inner sidewall 332 exists between the second interconnection layer and the gate structure, so that the distance between the second interconnection layer and the gate structure is increased, the possibility of short circuit is reduced, and the performance of the semiconductor structure is improved.
Referring to fig. 15, after the second inner spacers 332 are formed, a second dielectric layer 340 is formed on the interlayer dielectric layer 310, and the second gap 333 is filled with the second dielectric layer 340.
In this embodiment, the second dielectric layer 340 further covers the top surfaces of the sidewall spacers 308, the first dielectric layer 323, the first inner sidewall spacers 321, and the second inner sidewall spacers 332.
In this embodiment, the second dielectric layer 340 is made of silicon oxide; in other embodiments, the material of the second dielectric layer 340 may also be a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).
In this embodiment, the material of the second dielectric layer 340 is the same as that of the first dielectric layer 323.
After the second dielectric layer 340 is formed, a third opening exposing the top of the gate structure 312 and a fourth opening exposing the top of the conductive layer 331 are formed in the second dielectric layer 340.
Specifically, the method for forming the third opening and the fourth opening includes:
referring to fig. 16, a metal hard mask layer 350 and a patterned photoresist layer 360 are formed on the second dielectric layer 340, and the patterned photoresist layer 360 defines the positions and sizes of the third opening and the fourth opening to be formed.
Referring to fig. 17, the metal hard mask layer 350 is etched by using the patterned photoresist layer 360 as a mask to form a patterned metal hard mask layer 351; the patterned photoresist layer 360 is removed.
Referring to fig. 18, using the patterned metal hard mask layer 351 as a mask, the second dielectric layer 340 and the first dielectric layer 323 in the first gap 322 are etched until the top of the gate structure 312 and the top of the conductive layer 331 are exposed, a third opening 341 is formed at the top of the gate structure 312, and a fourth opening 342 is formed at the top of the conductive layer 331.
In this embodiment, the bottom of the third opening 341 is communicated with the top of the first gap 322; the bottom of the fourth opening 342 communicates with the top of the second gap 333.
In this embodiment, the process of etching the second dielectric layer 340 and the first dielectric layer 323 is a dry etching process; in other embodiments, the second dielectric layer 340 and the first dielectric layer 323 may be etched by a wet etching process.
In this embodiment, the third opening 341 provides a space for forming a first interconnect layer; the second opening 342 provides space for a second interconnect layer to be subsequently formed.
Referring to fig. 19, a first interconnect layer 3411 is formed within the first voids 322 and the third openings 341; a second interconnect layer 3421 is formed within the second void 333 and the fourth opening.
In this embodiment, the material of the first interconnect layer 3411 is a metal, and includes aluminum, copper, nickel, and the like.
In this embodiment, the first interconnect layer 3411 serves to connect different devices together to form a circuit, and also serves to transmit an external electrical signal to different portions inside the semiconductor device, thereby forming a semiconductor device having a certain function.
In this embodiment, the process of forming the first interconnect layer 3411 is an electrochemical plating process, because the first interconnect layer 3411 can be formed with high density and high uniformity by using the electroplating process.
In this embodiment, due to the existence of the first inner sidewall 321, the distance between the first interconnection layer 3411 and the adjacent conductive layer 331 is increased, so that the short circuit problem between the first interconnection layer 3411 and the conductive layer 331 is avoided, and the electrical performance of the formed semiconductor structure is improved.
In this embodiment, the material of the second interconnect layer 3421 is metal, and includes aluminum, copper, nickel, and the like.
In this embodiment, the second interconnection layer 3421 is used to connect different devices together to form a circuit, and can also transmit external electrical signals to different parts inside the semiconductor device, thereby forming a semiconductor device with certain functions.
In this embodiment, the process of forming the second interconnect layer 3421 is an electrochemical plating process, because the second interconnect layer 3421 with high density and high uniformity can be formed by the electroplating process.
In this embodiment, due to the existence of the second inner sidewall 332, a distance between the second interconnection layer 3421 and the adjacent gate structure 312 is increased, so that a short circuit problem between the second interconnection layer 3421 and the gate structure 312 is avoided, and electrical properties of the formed semiconductor structure are improved.
Correspondingly, the invention also provides a semiconductor structure.
Referring to fig. 18, the semiconductor structure includes: a substrate 300, wherein the substrate 300 is provided with an interlayer dielectric layer 310; a gate structure 312 located on the substrate 300, wherein a top surface of the gate structure 312 is lower than a top surface of the interlayer dielectric layer 310; a source-drain doping layer 309 located in the substrate 300 at two sides of the gate structure 312; a first opening 320 located in the interlayer dielectric layer 310, wherein the first opening 320 exposes a top surface of the gate structure 312; first inner side walls 321 located on the side walls of the first openings 320, wherein first gaps 322 are formed between the first inner side walls 321; a second opening 330 located in the interlayer dielectric layer 310, where the second opening 330 exposes the top surface of the source-drain doping layer 309; a conductive layer 331 located in the second opening 330, wherein a top surface of the conductive layer 331 is lower than a top surface of the interlayer dielectric layer 310; and second inner sidewalls 332 disposed on the sidewalls of the second opening 330 exposed by the conductive layer 331, wherein a second gap 333 is formed between the second inner sidewalls 332.
In this embodiment, the first inner sidewall spacers 321 are made of silicon nitride; in other embodiments, the material of the first inner sidewall spacers 321 may also be silicon oxycarbide or nitrogen-doped silicon carbide.
In this embodiment, the second inner sidewall 332 is made of silicon nitride; in other embodiments, the material of the second inner sidewall spacers 332 may also be silicon oxycarbide or nitrogen-doped silicon carbide.
In this embodiment, the first gap 322 provides a space for forming a first interconnection layer on the top of the gate structure 312, and the first inner sidewalls 321 are present on two sides of the first gap 322, so that a distance between the subsequently formed first interconnection layer and the conductive layer 331 is increased, short circuit between the first interconnection layer and the conductive layer 331 is avoided, and electrical properties of the formed semiconductor structure are improved.
In this embodiment, the second gap 333 provides a space for forming a second interconnection layer on the conductive layer 331 in the following, and because the second inner side walls 332 are present at two sides of the second gap 333, a distance between the second interconnection layer formed in the following and the gate structure 312 is increased, short circuit between the second interconnection layer and the gate structure 312 is avoided, and electrical properties of the formed semiconductor structure are improved.
With continued reference to fig. 18, the semiconductor structure further includes: and the side wall 308 is positioned on the side wall of the gate structure 312, and the top surface of the side wall 308 is flush with the top surface of the interlayer dielectric layer 310.
With continued reference to fig. 18, the semiconductor structure further includes: a second dielectric layer 340, wherein the second dielectric layer 340 is located on the interlayer dielectric layer 310; a third opening 341, located in the second dielectric layer 340, where the third opening 341 exposes the top of the gate structure 312; and a fourth opening 342 is located in the second dielectric layer 340, and the top of the conductive layer 331 is exposed out of the fourth opening 342.
In this embodiment, the second dielectric layer 340 is made of silicon oxide; in other embodiments, the material of the second dielectric layer 340 may also be a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).
In this embodiment, the material of the second dielectric layer 340 is different from the material of the first inner sidewall 321 and the material of the second inner sidewall 332, and the second dielectric layer 340 is etched in a subsequent etching process, so that etching damage to the first inner sidewall 321 and the second inner sidewall 332 is avoided, and a distance between a subsequently formed first interconnection layer and a conductive layer and a distance between the second interconnection layer and a gate structure can be ensured.
Referring to fig. 19, the semiconductor structure further includes: a first interconnect layer 3411 located within the first voids 322 and the third opening 341; a second interconnect layer 3421 located within the second void 333 and the fourth opening 342.
In this embodiment, the material of the first interconnect layer 3411 is a metal, and includes aluminum, copper, nickel, and the like.
In this embodiment, the material of the second interconnect layer 3421 is metal, and includes aluminum, copper, nickel, and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A semiconductor structure, comprising:
the device comprises a substrate, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the substrate is provided with an interlayer dielectric layer;
the grid structure is positioned on the substrate, and the top surface of the grid structure is lower than that of the interlayer dielectric layer;
the source-drain doping layers are positioned in the substrate on two sides of the grid structure;
a first opening in the interlayer dielectric layer, the first opening exposing a top surface of the gate structure;
the first inner side walls are positioned on the side walls of the first opening, and a first gap is formed between the first inner side walls;
the second opening is positioned in the interlayer dielectric layer and exposes the top surface of the source-drain doping layer;
the conducting layer is positioned in the second opening, and the top surface of the conducting layer is lower than that of the interlayer dielectric layer;
and the second inner side walls are positioned on the side walls of the second openings exposed by the conducting layer, and second gaps are formed between the second inner side walls.
2. The semiconductor structure of claim 1, further comprising:
a first interconnect layer located within the first void and on top of the gate structure;
a second interconnect layer located within the second void and on top of the conductive layer.
3. The semiconductor structure of claim 2, further comprising: and the second dielectric layer is positioned on the interlayer dielectric layer, and part of the first interconnection layer and part of the second interconnection layer are also positioned in the second dielectric layer.
4. The semiconductor structure of claim 1, wherein a material of the first inner sidewall spacers comprises silicon nitride, silicon oxycarbide, or nitrogen-doped silicon carbide.
5. The semiconductor structure of claim 1, wherein a material of the second inner sidewall spacers comprises silicon nitride, silicon oxycarbide, or nitrogen-doped silicon carbide.
6. The semiconductor structure of claim 3, wherein a material of the second dielectric layer is different from a material of the first inner sidewall spacer, and the material of the second dielectric layer is different from a material of the second inner sidewall spacer, and the material of the second dielectric layer comprises a low-k dielectric material, an ultra-low-k dielectric material, or silicon oxide.
7. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with an interlayer dielectric layer, a gate structure positioned in the interlayer dielectric layer and source drain doping layers positioned on two sides of the gate structure in the substrate;
etching the grid structure until the top surface of the grid structure is lower than the top surface of the interlayer dielectric layer, and forming a first opening in the interlayer dielectric layer;
forming first inner side walls on the side walls of the first opening, wherein first gaps are formed among the first inner side walls;
forming a first dielectric layer in the first gap;
etching the interlayer dielectric layer on the source-drain doped layer until the top surface of the source-drain doped layer is exposed to form a second opening;
forming a conductive layer in the second opening, wherein the top surface of the conductive layer is lower than that of the interlayer dielectric layer;
and forming second inner side walls on the side walls of the second openings exposed by the conductive layer, wherein second gaps are formed between the second inner side walls.
8. The method of forming a semiconductor structure of claim 7, further comprising:
forming a first interconnection layer in the first gap, wherein the first interconnection layer is positioned at the top of the gate structure;
a second interconnect layer is formed within the second void, and the second interconnect layer is located on top of the conductive layer.
9. The method of forming a semiconductor structure of claim 8, further comprising, prior to forming the first interconnect layer and the second interconnect layer: and forming a second dielectric layer on the interlayer dielectric layer, wherein the second dielectric layer is also filled in the second gap.
10. The method of forming a semiconductor structure of claim 9, wherein the step of forming a first interconnect layer within the first void comprises:
etching the second dielectric layer and the first dielectric layer in the first gap until the top of the grid structure is exposed, and forming a third opening in the second dielectric layer;
a first interconnect layer is formed within the first void and the third opening.
11. The method of forming a semiconductor structure of claim 9, wherein the step of forming a second interconnect layer within the second void comprises:
etching the second dielectric layer until the top of the conductive layer is exposed, and forming a fourth opening in the second dielectric layer;
forming a second interconnect layer within the second void and the fourth opening.
12. The method of forming a semiconductor structure of claim 7, wherein forming a conductive layer within the second opening comprises:
forming an initial conducting layer in the second opening, wherein the top surface of the initial conducting layer is flush with the top surface of the interlayer dielectric layer;
and etching the initial conducting layer until the top surface of the initial conducting layer is lower than that of the interlayer dielectric layer to form the conducting layer.
CN202010962082.3A 2020-09-14 2020-09-14 Semiconductor structure and forming method thereof Pending CN114188318A (en)

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