CN115687220B

CN115687220B - Identification circuit, identification method, electronic device and storage medium for multi-server identification

Info

Publication number: CN115687220B
Application number: CN202310001385.2A
Authority: CN
Inventors: 王晓松; 张淑君
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-01-03
Filing date: 2023-01-03
Publication date: 2023-04-18
Anticipated expiration: 2043-01-03
Also published as: CN115687220A

Abstract

The embodiment of the invention provides a recognition circuit, a recognition method, electronic equipment and a storage medium of a multi-server identifier; the system comprises a first sub-I2 CIO identification chip connected with any first high-speed signal connection port, and is used for generating and storing a first high-speed signal connection port identifier; the first primary I2CIO identification chip is positioned under the I2C of the IO server, and the first primary I2CIO identification chip is connected with a plurality of first branch I2CIO identification chips and controls the I2C signal transmission of the first high-speed signal connection port; a second sub I2CIO identification chip connected with any second high-speed signal connection port generates and stores a second high-speed signal connection port identifier; when the first primary I2CIO identification chip is in an operable state, identifying a first high-speed signal connection port identification and a second high-speed signal connection port identification; a first high-speed signal connection port and a second high-speed signal connection port which are connected with each other are determined. The embodiment of the invention can accurately identify the high-speed signal connection port for connecting the IO server and the SSD server.

Description

Identification circuit, identification method, electronic device and storage medium for multi-server identification

Technical Field

The present invention relates to the field of server technologies, and in particular, to a circuit for identifying a multi-server identifier, a method for identifying a circuit for identifying a multi-server identifier, an apparatus for identifying a circuit for identifying a multi-server identifier, an electronic device, and a storage medium.

Background

The development of many complex computing scenes such as artificial intelligence, machine learning, high-performance computing and the like is changing day by day, and new requirements are put forward on a data center architecture. The computing platforms with different processing tasks have different requirements and different computing power requirements in different application scenes, and in order to meet different data processing, data throughput requirements and resource requirements in different scenes, a data center accelerates the transition from a computing-centered architecture to a data-centered fusion architecture.

One of the design features of the converged architecture is "resource decoupling". The whole system is decoupled into independent pooling modules such as a computing resource pool, a memory resource pool, an I/O (Input/Output) device resource pool and the like, which is beneficial to a Central Processing Unit (CPU), a memory, a Graphic Processing Unit (GPU), in the fusion architecture, all IO resources are concentrated in an IO server, terminal equipment is all hung under the IO server, the management software can allocate IO resources for the actual access situation of the device, taking the SSD resource pool as an example, because the physical structures of the SSD servers are completely the same, the old ID identification scheme cannot be normally used in a multi-server system of the whole cabinet, in the related technology, each IO server HE SSD server has a unique ID code, the signals are sent to a BMC (Baseboard Management Controller) or a BIOS (Basic Input Output System) through a dial switch or a resistor which is pulled up and down, so that the System knows the number of the System, but under the application scene of the resource pooling System, when a plurality of same servers exist in the system, the core node cannot effectively distinguish the plurality of the same servers existing below.

Disclosure of Invention

In view of the above problems, embodiments of the present invention are provided to provide an identification circuit of a multi-server identity, an identification method of an identification circuit based on a multi-server identity, an identification apparatus of an identification circuit based on a multi-server identity, an electronic device, and a storage medium that overcome or at least partially solve the above problems.

The embodiment of the invention discloses a circuit for identifying a multi-server identifier, wherein the multi-server comprises at least one input/output (IO) server and a Solid State Disk (SSD) server; the IO server comprises a plurality of first high-speed signal connection ports; the SSD server comprises a plurality of second high-speed signal connection ports; the identification circuit includes:

the first I2CIO identification chip is connected with any one first high-speed signal connection port and used for generating and storing a first high-speed signal connection port identifier;

a first primary I2CIO identification chip under the I2C of the IO server, wherein the first primary I2CIO identification chip is connected with a plurality of first sub I2CIO identification chips and is used for controlling the I2C signal transmission of the first high-speed signal connection port;

the second I2CIO identification chip is connected with any second high-speed signal connection port and is used for generating and storing a second high-speed signal connection port identifier;

when the first primary I2CIO identification chip is in an operable state, identifying the first high-speed signal connection port identification and the second high-speed signal connection port identification; a first high-speed signal connection port and a second high-speed signal connection port that are connected to each other are determined.

Optionally, the first primary I2CIO identification chip includes an operability bit; and when the operability bit is in a high bit, determining that the first primary I2CIO identification chip is in the operable state.

Optionally, the method further comprises:

and the first I2C expansion chip is connected with the plurality of first I2CIO identification chips, is positioned under the I2C of the same IO server as the first primary I2CIO identification chip, is used for expanding the I2C of the IO server to any one first I2CIO identification chip, and stores a first I2C expansion identifier.

Optionally, the method further comprises:

and the second I2C expansion chip is connected with the second sub I2CIO identification chips and is used for expanding the I2C of the SSD server to any second sub I2CIO identification chip and storing a second I2C expansion identifier.

Optionally, the method further comprises:

and the second primary I2CIO identification chip and the second I2C expansion chip are positioned under the same I2C of the SSD server and are used for controlling the I2C signal transmission of the second high-speed signal connection port.

Optionally, the first high-speed signal connection port identifier includes a wideband number and a first high-speed signal connection port code;

the first sub-I2 CIO identification chip is used for generating and storing the broadband number and the first high-speed signal connection port code.

Optionally, the first high-speed signal connection port identification is eight-bit coded; the first bit code to the third bit code are the first high-speed signal connection port code, the fourth bit code to the fifth bit code are the preset pending code, and the sixth bit code to the eighth bit code are the wideband number.

Optionally, the second high-speed signal connection port identifier includes an SSD server number, an SSD server identity identifier, and a second high-speed signal connection port code;

the second I2CIO identification chip is used for generating and storing the SSD server number, the SSD server identity and the second high-speed signal connection port code.

Optionally, the second high-speed signal connection port identifier is coded by eight bits; the first bit code to the fourth bit code are used for coding the second high-speed signal connection port, the fifth bit code to the sixth bit code are used for coding the SSD server identity, and the seventh bit code to the eighth bit code are used for coding the SSD server number.

The embodiment of the invention also discloses a recognition method of the recognition circuit based on the multi-server identification, wherein the recognition circuit comprises the recognition circuit; the method is applied to the IO server and comprises the following steps:

setting the first primary I2CIO identification chip to be in the operable state;

reading the first high-speed signal connection port identification;

and determining a first high-speed signal connection port connected with the SSD server based on the first high-speed signal connection port identification.

Optionally, the setting the first top level I2CIO identification chip in the operable state includes:

and setting the operable bit of the first primary I2CIO identification chip to be a preset high level.

Optionally, the determining, based on the first high-speed signal connection port identifier, a first high-speed signal connection port connected to the SSD server includes:

reading the first high-speed signal connection port identification;

determining the number of the codes of the first high-speed signal connection port identifications and the number of the first high-speed signal connection port identifications matched with a preset first high-speed signal connection code;

when the number corresponding to the first high-speed signal connection port identification is single, determining that the first high-speed signal connection port corresponding to the first high-speed signal connection port identification is a first high-speed signal connection port connected with the SSD server;

when the number corresponding to the first high-speed signal connection port identification is multiple, setting the IO server identity identification bit code of the first primary I2CIO identification chip to modify the code of the first high-speed signal connection port identification;

and when the modified code of the first high-speed signal connection port identifier contains the IO server identity identification bit code, determining that the first high-speed signal connection port corresponding to the modified first high-speed signal connection port identifier is the first high-speed signal connection port connected with the SSD server.

The embodiment of the invention also discloses a recognition method of the recognition circuit based on the multi-server identification, and the recognition circuit comprises the recognition circuit; the method is applied to the SSD server, and comprises the following steps:

when the first primary I2CIO identification chip is in the operable state, reading the second high-speed signal connection port identification; the operable state is determined by the IO server setting the first primary I2CIO identification chip;

and determining a second high-speed signal connection port connected with the IO server based on the second high-speed signal connection port identification.

Optionally, when the IO server sets an operable bit of the first top-level I2CIO identification chip to a preset high level, it is determined that the first top-level I2CIO identification chip is in the operable state.

Optionally, the determining, based on the second high-speed signal connection port identifier, a second high-speed signal connection port connected to the IO server includes:

reading the second high-speed signal connection port identification;

determining the number of the second high-speed signal connection port identifications corresponding to the codes of the second high-speed signal connection port identifications matched with preset second high-speed signal connection codes;

when the number corresponding to the second high-speed signal connection port identification is single, determining that the second high-speed signal connection port corresponding to the second high-speed signal connection port identification is a second high-speed signal connection port connected with the IO server;

when the number corresponding to the second high-speed signal connection port identifiers is multiple, setting the SSD server identity identification bit code of the second primary I2CIO identification chip to modify the code of the second high-speed signal connection port identifiers;

and when the modified code of the second high-speed signal connection port identifier contains the SSD server identity identification bit code, determining the second high-speed signal connection port corresponding to the modified second high-speed signal connection port identifier as the second high-speed signal connection port connected with the IO server.

The embodiment of the invention also discloses a recognition device of the recognition circuit based on the multi-server identification, wherein the recognition circuit comprises the recognition circuit; the device is applied to the IO server, and the device comprises:

the setting module is used for setting the first primary I2CIO identification chip to be in the operable state;

the first reading module is used for reading the first high-speed signal connection port identification;

and the first identification module is used for determining a first high-speed signal connection port connected with the SSD server based on the first high-speed signal connection port identifier.

The embodiment of the invention also discloses a recognition device of the recognition circuit based on the multi-server identification, wherein the recognition circuit comprises the recognition circuit; the device is applied to the SSD server and comprises:

a second reading module, configured to read the second high-speed signal connection port identifier when the first primary I2CIO identification chip is in the operable state; the operable state is determined by the IO server setting the first primary I2CIO identification chip;

and the second identification module is used for determining a second high-speed signal connection port connected with the IO server based on the second high-speed signal connection port identifier.

The embodiment of the invention also discloses electronic equipment, which comprises a processor, a memory and a computer program which is stored on the memory and can run on the processor, wherein when the computer program is executed by the processor, the steps of the identification method based on the identification circuit of the multi-server identification are realized.

The embodiment of the invention also discloses a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the steps of the identification method based on the identification circuit of the multi-server identification are realized.

The embodiment of the invention also discloses a server cabinet, which comprises the IO server, the SSD server and the identification circuit of the multi-server identifier;

one end of the identification circuit is connected with the IO server, and the other end of the identification circuit is connected with the SSD server.

The embodiment of the invention has the following advantages:

the embodiment of the invention generates and stores a first high-speed signal connection port identifier through a first sub I2CIO identification chip connected with any first high-speed signal connection port; the first primary I2CIO identification chip is positioned under the I2C of the IO server, and the first primary I2CIO identification chip is connected with a plurality of first branch I2CIO identification chips and controls the I2C signal transmission of the first high-speed signal connection port; a second sub I2CIO identification chip connected with any second high-speed signal connection port generates and stores a second high-speed signal connection port identifier; when the first primary I2CIO identification chip is in an operable state, identifying a first high-speed signal connection port identification and a second high-speed signal connection port identification; a first high-speed signal connection port and a second high-speed signal connection port that are connected to each other are determined. The method comprises the steps that I2C identification is carried out on a first high-speed signal connection port of each IO server and a second high-speed signal connection port of an SSD server under the I2C of an IO server through a first I2CIO identification chip, and I2C identification is carried out on a second I2CIO identification chip under the I2C of the SSD server, when the first-level I2CIO identification chip is in an operable state, the first high-speed signal connection port identification and the second high-speed signal connection port identification are identified, so that the connected IO server and the connected SSD server are accurately positioned, and the IO server and the SSD server are identified.

Drawings

FIG. 1 is a schematic diagram of an embodiment of a multi-server identification circuit of the present invention;

FIG. 2 is a schematic diagram of another embodiment of a multi-server identification circuit of the present invention;

FIG. 3 is a schematic diagram of the connection between the IO server and the SSD server according to the present invention;

FIG. 4 is a flowchart illustrating the steps of an embodiment of a method for identifying a circuit based on multi-server identification according to the present invention;

FIG. 5 is a flow chart of steps of another embodiment of a method for identifying a circuit based on multi-server identification according to the present invention;

FIG. 6 is a schematic diagram of an exemplary identification circuit of an identification method of the identification circuit based on multi-server identification according to the present invention;

FIG. 7 is a schematic diagram illustrating steps of an exemplary identification method of an identification circuit based on multi-server identification according to the present invention;

FIG. 8 is a block diagram of an embodiment of the identification device of the identification circuit based on multi-server identification according to the present invention;

FIG. 9 is a block diagram of an embodiment of the identification device of the identification circuit based on multi-server identification according to the present invention;

fig. 10 is a block diagram of an electronic device according to an embodiment of the present invention;

fig. 11 is a block diagram of a storage medium according to an embodiment of the present invention;

fig. 12 is a block diagram of a server rack according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to fig. 1, a schematic diagram of an embodiment of an identification circuit for multiple server identifiers according to the present invention is shown, where the multiple servers include at least one IO server and a SSD server; the IO server comprises a plurality of first high-speed signal connection ports; the SSD server comprises a plurality of second high-speed signal connection ports.

In the embodiment of the invention, the multiple servers comprise at least one IO server and an SSD server, and the multiple servers form a resource pooling system. Wherein the IO server comprises a plurality of first high-speed signal connection ports, i.e. CDFP (high-speed signal connector) ports on the IO server. The SSD server includes a plurality of second high speed signal connection ports, i.e., CDFP ports on the SSD server. The CDFP interface on the IO server can be randomly connected with the CDFP port on the SSD server.

The identification circuit may specifically include:

a first add-drop bidirectional two-wire system synchronous serial bus I2CIO identification chip connected with any one first high-speed signal connection port and used for generating and storing a first high-speed signal connection port identification;

the first primary I2CIO identification chip is positioned under the I2C of the IO server, and the first primary I2CIO identification chip is connected with the plurality of first sub I2CIO identification chips and is used for controlling the I2C signal transmission of the first high-speed signal connection port;

when the first primary I2CIO identification chip is in an operable state, identifying the first high-speed signal connection port identification and the second high-speed signal connection port identification; a first high-speed signal connection port and a second high-speed signal connection port which are connected with each other are determined.

In the embodiment of the invention, an I2CIO identification chip, namely a first branch I2CIO identification chip, is hooked on each first high-speed signal connection port of the IO server, so that the first high-speed signal connection port can be accessed to an I2C and can carry out data transmission based on the I2C. The first sub I2CIO identification chip generates a first high-speed signal connection port identifier corresponding to each first high-speed signal connection port based on the logic position of the first sub I2CIO identification chip, and stores the first high-speed signal connection port identifiers; and distinguishing the first high-speed signal connection port on the IO server through the first high-speed signal connection port identification.

The I2C of the IO server is also connected with a first primary I2CIO identification chip, the first primary I2CIO identification chip is connected with each first branch I2CIO identification chip, and the first primary I2CIO identification chip controls the I2C signal transmission of the first high-speed signal connection port; under the I2C bus, I2C signals firstly pass through the first primary I2CIO identification chip and then are transmitted to each first sub I2CIO identification chip after passing through the first primary I2CIO identification chip.

And an I2CIO identification chip, namely a second sub I2CIO identification chip, is hooked on each second high-speed signal connection port of the SSD server, so that the second high-speed signal connection port can be accessed to the I2C of the SSD server and can perform data transmission based on the I2C. The second I2CIO identification chip generates a second high-speed signal connection port identifier corresponding to each second high-speed signal connection port based on the logic position served by the SSD and stores the second high-speed signal connection port identifiers; and distinguishing a second high-speed signal connection port on the SSD server through the second high-speed signal connection port identifier.

The second high-speed signal connection port on the SSD server and the first high-speed signal connection port on the IO server are random. When the first primary I2CIO identification chip is in an operable state, an I2C signal in the IO server may be sent to the first sub I2CIO identification chip through the first primary I2CIO identification chip, and if a second high-speed signal connection port on the SSD server is connected to the first high-speed signal connection port on the IO server, the I2C signal may be transmitted to the second high-speed signal connection port; that is, the first high-speed signal connection port and the second high-speed signal connection port that are connected to each other may be determined by identifying the first high-speed signal connection port identifier and the second high-speed signal connection port identifier, so that the IO server and the SSD server that perform data interaction in the resource pooling system may be determined.

The specific type of the first-level I2CIO identification chip, the first sub-I2 CIO identification chip, and the second first-level I2CIO identification chip may be PCA9554.

The embodiment of the invention generates and stores a first high-speed signal connection port identifier through a first sub-I2 CIO identification chip connected with any first high-speed signal connection port; the first primary I2CIO identification chip is positioned under the I2C of the IO server, and the first primary I2CIO identification chip is connected with the plurality of first branch I2CIO identification chips and controls the I2C signal transmission of the first high-speed signal connection port; a second sub I2CIO identification chip connected with any second high-speed signal connection port generates and stores a second high-speed signal connection port identifier; when the first primary I2CIO identification chip is in an operable state, identifying a first high-speed signal connection port identification and a second high-speed signal connection port identification; a first high-speed signal connection port and a second high-speed signal connection port that are connected to each other are determined. The method comprises the steps that I2C of an IO server is set through a first I2CIO identification chip, I2C identification is carried out on a first high-speed signal connection port of each IO server and a second high-speed signal connection port of an SSD server under the I2C of the IO server and a second I2CIO identification chip under the I2C of the SSD server, when the first-level I2CIO identification chip is in an operable state, the first high-speed signal connection port identification and the second high-speed signal connection port identification are identified, the IO server and the SSD server which are connected are accurately located, and the IO server and the SSD server are identified.

Referring to fig. 2, a schematic diagram of another embodiment of the identification circuit for identifying a multi-server identifier according to the present invention is shown, where the multi-server includes at least one IO server and a SSD server; the IO server comprises a plurality of first high-speed signal connection ports; the SSD server comprises a plurality of second high-speed signal connection ports.

The IO server is an IO resource control node of the computing system, and has the specific functions of: PCIe (high speed serial computer expansion bus standard) resources from a plurality of different CPUs are expanded, networked and distributed through 8 PCIe Switch chips contained in the IO server. The whole IO server may finally present 40 CDFP interfaces, i.e. first high-speed signal connection ports, to the outside, each first high-speed signal connection port containing a set of PCIe 5.0 × 16 (bandwidth) high-speed IO signals.

The SSD server is a terminal device of the server system, and is a container dedicated for carrying NVMe SSD (nonvolatile memory host controller interface specification solid state disk). Each SSD server may be fully loaded with 32 high capacity NVMe SSDs, connected to the IO server through 6 CDFP interfaces, i.e., the second high speed signal connection ports, on the SSD server. As shown in fig. 3, the 6 second high-speed signal connection ports of the SSD server can be connected to any 6 of the 40 first high-speed signal connection ports of the IO server without specifying a fixed plugging sequence.

The identification circuit may specifically include:

the first I2C expansion chip is connected with a plurality of first I2CIO identification chips, the first I2C expansion chip and the first primary I2CIO identification chip are positioned under the I2C of the same IO server, and are used for expanding the I2C of the IO server to any first I2CIO identification chip and storing a first I2C expansion identifier;

the second I2C expansion chip is connected with the plurality of second I2CIO identification chips and is used for expanding the I2C of the SSD server to any one of the second I2CIO identification chips and storing a second I2C expansion identifier;

a second primary I2CIO identification chip under the same I2C of the SSD server as the second I2C expansion chip, for controlling the I2C signal transmission of the second high-speed signal connection port

In the embodiment of the invention, each first high-speed signal connection port in an IO server is connected with a first sub-I2 CIO identification chip in a hanging mode, and the first sub-I2 CIO identification chip generates and stores a first high-speed signal connection port identifier; the plurality of first I2CIO identification chips are connected with the first I2C expansion chip, and the first I2C expansion chip expands the IO resources in the IO server to each first I2CIO identification chip. And the first I2C expansion chip and the first primary I2CIO identification chip are positioned under the same I2C level of the IO server, and the first I2C expansion chip stores a first I2C expansion identifier. To distinguish branches of IO resources on the basis of the first high-speed signal connection port identification of the first sub I2CIO identification chip.

Each second high-speed signal connection port in the SSD server is connected with a second sub I2CIO identification chip in a hanging mode, and the second sub I2CIO identification chip generates and stores a second high-speed signal connection port identifier; the plurality of second sub I2CIO identification chips are connected with the second I2C expansion chip, and the second I2C expansion chip expands the IO resources in the SSD server to each second sub I2CIO identification chip. And the second I2C expansion chip and the second primary I2CIO identification chip are positioned at the I2C level of the same SSD server, and the second I2C expansion chip stores a second I2C expansion identifier. The method is used for distinguishing the branches of the IO resources of the SSD server on the basis of the first high-speed signal connection port identification of the second I2CIO identification chip.

The first-level I2CIO identification chip is connected with each first sub I2CIO identification chip, when an IO server performs data interaction with the SSD server based on an I2C bus, I2C signals are firstly transmitted to each first sub I2CIO identification chip through the first-level I2CIO identification chip, so that the corresponding first high-speed signal connection port is controlled to perform data interaction.

The second first-level I2CIO identification chips are connected with each second sub I2CIO identification chip, and when the SSD server performs data interaction with the IO server based on the I2C bus, I2C signals are firstly transmitted to each second sub I2CIO identification chip through the second first-level I2CIO identification chips so as to control the corresponding second high-speed signal connection ports to perform data interaction.

In the identification process, the identification is initiated by an IO server, namely the operability bit of the first-level I2CIO identification chip can be set; when the operability bit is at the high bit, it is determined that the top-level I2CIO identification chip is in an operable state.

When the first-level I2CIO identification chip is in an operable state, the first high-speed signal connection port and the second high-speed signal connection port which are connected with each other are determined by identifying the first high-speed signal connection port identification and the second high-speed signal connection port identification, so that an IO server and an SSD server for data interaction in the resource pooling system can be determined.

The specific type of the first top level I2CIO identification chip, the first sub-I2 CIO identification chip, the second top level I2CIO identification chip, and the second first top level I2CIO identification chip may be PCA9554. The specific model of the first I2C extended chip and the second I2C extended chip may be PCA9548.

Further, the first high-speed signal connection port identification comprises a broadband number and a first high-speed signal connection port code. The wideband number can be determined based on the wideband branch to which the first high-speed signal connection port code belongs, and the first high-speed signal connection port code is the identity of the first high-speed signal connection port. The first sub-I2 CIO identification chip generates and stores a broadband number and a first high-speed signal connection port code.

Specifically, the first I2CIO identification chip is PCA9554; and PCA9554 may be eight-bit encoded for 8-way IO input, i.e., first high speed signal connection port identification. The first bit code to the third bit code are first high-speed signal connection port codes, namely the marks of the broadband ports; the fourth bit code to the fifth bit code are preset undetermined codes, and operation bits are reserved when other codes are carried out on PCA9554 subsequently by reserving the preset undetermined codes. The sixth bit through the eighth bit are encoded as wideband numbers. That is, the first high speed signal connection port code may be 000-111; the wideband number may be 000-111; thus, the first high speed signal connection port identification may be:

further, the second high-speed signal connection port identifier includes an SSD server number, an SSD server identity identifier, and a second high-speed signal connection port code. The SSD server number is the number of the SSD server in the resource pooling system. The SSD server identity is an SSD server identity code. The second high-speed signal connection port code is the identity of the second high-speed signal connection port. And the second I2CIO identification chip generates and stores the SSD server number, the SSD server identity and a second high-speed signal connection port code.

Specifically, the second I2CIO identification chip is PCA9554; and PCA9554 may be eight-bit encoded for 8-way IO input, i.e., second high speed signal connection port identification. Unlike IO servers, there may be multiple SSD servers, so the seventh bit to the eighth bit of PCA9554 are subsequently used for differentiation of the same SSD server, i.e. the seventh bit to the eighth bit are encoded as SSD server numbers; since the entire system architecture includes not only the SSD server but also different servers such as the GPU server and the memory server, the codes from the fifth bit to the sixth bit of the PCA9554 are defined as the SSD server IDs, that is, the codes from the fifth bit to the sixth bit are the SSD server IDs. And the first bit code to the fourth bit code are the second high-speed signal connection port codes to distinguish the second high-speed signal connection ports. That is, for one SSD server, the second high-speed signal connection port identification may be:

in addition, PCA9548 addresses of the IO server and the SSD server must be set to different values to prevent data read conflicts. All PCA9548 addresses within the same server must be set to the same value to ensure valid reading of the ID (Identity document) at any cable termination.

According to the embodiment of the invention, I2C identification is carried out on a first high-speed signal connection port of each IO server and a second high-speed signal connection port of an SSD server under the I2C of the IO server and the I2C of the SSD server by the arrangement of a first I2CIO identification chip and the arrangement of a second I2CIO identification chip under the I2C of the SSD server, when the first-level I2CIO identification chip is in an operable state, the connected IO server and the SSD server are accurately positioned by identifying the first high-speed signal connection port identification and the second high-speed signal connection port identification, and the IO server and the SSD server are identified; the I2C can be connected to each first high-speed signal connection port or the second high-speed signal connection port through the first I2C extension chip and the first I2C extension chip, so that the identification range is larger.

Referring to fig. 4, a flow chart of steps of an embodiment of a method for identifying a multi-server identification based identification circuit of the present invention is shown, wherein the identification circuit comprises the identification circuit as described above; the identification method is applied to the IO server, and the identification method may specifically include the following steps:

step 401, setting the first primary I2CIO identification chip in the operable state;

the identification process needs to be initiated by an IO server, and for this reason, when identification is carried out, a first primary I2CIO identification chip is set to be in an operable state; so that the respective first and second I2CIO identification chips can communicate based on the I2C bus.

In an optional embodiment of the present invention, the step of setting the first top level I2CIO identification chip in the operable state may include the sub-steps of:

and a substep S4021 of setting the operable bit of the first-stage I2CIO identification chip to a preset high level.

In practical applications, the operable bit of the first-level I2CIO identification chip may be set to a preset high level, and the first-level I2CIO identification chip is pulled up, so that the first-level I2CIO identification chip is in an operable state.

For example, the preset high level may be "1", and the operable bit of the first-level I2CIO identification chip is the 1 st bit; at this time, the state code first bit of the first-level I2CIO identification chip may be set to 1.

Step 402, reading the first high-speed signal connection port identifier;

reading a first high-speed signal connection port identifier carried in a transmission I2C signal; the first high-speed signal connection port identification can be read specifically by the BISO or BMC.

Step 403, determining a first high-speed signal connection port connected with the SSD server based on the first high-speed signal connection port identifier.

And determining a specific first high-speed signal connection port according to the read code in the first high-speed signal connection port identifier, namely determining that the first high-speed signal connection port is a first high-speed signal connection port connected with the SSD server.

In an embodiment of the present invention, the step of determining the first high-speed signal connection port connected to the SSD server based on the first high-speed signal connection port identification includes the sub-steps of:

substep S4031, reading the identifier of the first high-speed signal connection port;

and reading the code of the first high-speed signal connection port identifier, if the first sub-I2 CIO identification chip is PCA9554, reading the eight-bit code corresponding to the first high-speed signal connection port identifier carried in the transmission I2C signal.

Substep S4032, determining the number of the first high-speed signal connection port identifiers corresponding to the code of the first high-speed signal connection port identifier matching with a preset first high-speed signal connection code;

when the first-level I2CIO identification chip is in an operable state, the first-level I2CIO identification chip is in an awakening state, the first-level I2CIO identification chip is located at the front end of the I2C bus and can have a corresponding preset first high-speed signal connection code, and the preset first high-speed signal connection code is the feature code of the first high-speed signal connection port identification when the first-level I2CIO identification chip is awakened. The codes of all the first high-speed signal connection port identifiers can be judged, whether the codes are matched with the preset first high-speed signal connection codes or not is determined one by one, and the number corresponding to the codes of the first high-speed signal connection port identifiers matched with the preset first high-speed signal connection codes is determined.

Substep S4033, when the number corresponding to the first high-speed signal connection port identifier is single, determining that the first high-speed signal connection port corresponding to the first high-speed signal connection port identifier is the first high-speed signal connection port connected to the SSD server;

when the number corresponding to the first high-speed signal connection port identifier is single, that is, when the first primary I2CIO identification chip is in an operable state, only one first high-speed signal connection port responds, that is, it can be directly determined that the first high-speed signal connection port corresponding to the first high-speed signal connection port identifier is the first high-speed signal connection port connected to the SSD server.

Substep S4034, when the number corresponding to the first high-speed signal connection port identifiers is multiple, setting an IO server identity identifier bit code of the first primary I2CIO identification chip to modify the code of the first high-speed signal connection port identifiers;

when the number of the first high-speed signal connection port identifiers is multiple, that is, multiple first high-speed signal connection ports are connected in parallel under the same I2C, it is necessary to further determine the first high-speed signal connection port identifier corresponding to the first high-speed signal connection port actually connected in the first high-speed signal connection port identifiers. For this purpose, an IO server id bit code of the first-level I2CIO identification chip may be set, and the IO server id bit code of the code corresponding to the first sub I2CIO identification chip under the IO server I2C may be modified accordingly by setting the IO server id bit code of the first-level I2CIO identification chip.

In sub-step S4035, when the modified code of the first high-speed signal connection port identifier includes the IO server identification bit code, it is determined that the first high-speed signal connection port corresponding to the modified first high-speed signal connection port identifier is the first high-speed signal connection port connected to the SSD server.

And determining that the code of the modified first high-speed signal connection port identifier comprises the code of the IO server identity identifier bit code, and determining that the first high-speed signal connection port corresponding to the modified first high-speed signal connection port identifier of the code is the first high-speed signal connection port connected with the SSD server.

In the embodiment of the invention, the first primary I2CIO identification chip is set to be in the operable state; reading the first high-speed signal connection port identification; and determining a first high-speed signal connection port connected with the SSD server based on the first high-speed signal connection port identification. When the first-level I2CIO identification chip is in an operable state, the identification of the first high-speed signal connection port is directly read, and the first high-speed signal connection port is determined, so that the I2C signal transmission port of the IO server is identified.

Referring to fig. 5, a flow chart of steps of an embodiment of a method for identifying a multi-server identification based identification circuit of the present invention is shown, the identification circuit including an identification circuit as described above; the identification method is applied to the SSD server, and the identification method may specifically include the steps of:

step 501, when the first primary I2CIO identification chip is in the operable state, reading the second high-speed signal connection port identifier; the operable state is determined by the IO server setting the first primary I2CIO identification chip;

when the first-level I2CIO identification chip is in an operable state, and correspondingly, when an I2C signal is transmitted to the SSD server, and the second first-level I2CIO identification chip is set to be in an operable state, the second high-speed signal connection port identifier carried in the I2C signal may be read at this time. Wherein, the operable state is determined by the IO server setting the first primary I2CIO identification chip.

Specifically, when the IO server sets the operable bit of the first-level I2CIO identification chip to a preset high level, it is determined that the first-level I2CIO identification chip is in an operable state; to begin reading the second high speed signal connection port identification.

Step 502, determining a second high-speed signal connection port connected with the IO server based on the second high-speed signal connection port identifier.

And determining a specific second high-speed signal connection port according to the read code in the second high-speed signal connection port identifier, namely determining that the second high-speed signal connection port is a second high-speed signal connection port connected with the IO server.

In an optional embodiment of the present invention, the determining, based on the second high-speed signal connection port identifier, a second high-speed signal connection port connected to the IO server includes the following sub-steps:

substep S5021, reading the second high-speed signal connection port identification;

and reading the code of the second high-speed signal connection port identifier, if the second I2CIO identification chip is PCA9554, reading the eight-bit code corresponding to the second high-speed signal connection port identifier carried in the transmission I2C signal.

Substep S5022, determining the number of the second high-speed signal connection port identifiers corresponding to the codes of the second high-speed signal connection port identifiers matched with preset second high-speed signal connection codes;

when the second first-level I2CIO identification chip is in an operable state, the second first-level I2CIO identification chip is in an awakening state, the second first-level I2CIO identification chip is located at the front end of an I2C bus of the SSD server and can have a corresponding preset second high-speed signal connection code, and the preset second high-speed signal connection code is a feature code of a second high-speed signal connection port identifier when the second first-level I2CIO identification chip is awakened. The codes of all the second high-speed signal connection port identifications can be judged, whether the codes are matched with the preset second high-speed signal connection codes or not is determined one by one, and the number corresponding to the codes of the second high-speed signal connection port identifications matched with the preset second high-speed signal connection codes is determined.

Substep S5023, determining that the second high-speed signal connection port corresponding to the second high-speed signal connection port identifier is the second high-speed signal connection port connected with the IO server when the number corresponding to the second high-speed signal connection port identifier is single;

when the number corresponding to the second high-speed signal connection port identifier is single, that is, when the second primary I2CIO identification chip is in an operable state, only one second high-speed signal connection port responds, that is, it can be directly determined that the second high-speed signal connection port corresponding to the second high-speed signal connection port identifier is the second high-speed signal connection port connected to the IO server.

Substep S5024, when the number corresponding to the second high-speed signal connection port identifiers is multiple, setting the SSD server identity identifier bit code of the second top-level I2CIO identification chip to modify the code of the second high-speed signal connection port identifiers;

when the number of the second high-speed signal connection port identifiers is multiple, that is, multiple second high-speed signal connection ports are connected in parallel under the same I2C, it is necessary to further determine the second high-speed signal connection port identifier corresponding to the second high-speed signal connection port actually connected among the second high-speed signal connection port identifiers. For this purpose, the SSD server id bit code of the second primary I2CIO identification chip may be set, and the IO server id bit code of the code corresponding to the first secondary I2CIO identification chip under the SSD server I2C may be modified accordingly by setting the SSD server id bit code of the second primary I2CIO identification chip.

And a substep S5025, determining that the second high-speed signal connection port corresponding to the modified second high-speed signal connection port identifier is the second high-speed signal connection port connected with the IO server when the modified code of the second high-speed signal connection port identifier includes the SSD server identification bit code.

And determining that the code of the modified first high-speed signal connection port identifier contains the code of the IO server identity identification bit code, and determining that the first high-speed signal connection port corresponding to the modified first high-speed signal connection port identifier of the code is the first high-speed signal connection port connected with the SSD server.

The method can judge the code of the second high-speed signal connection port identifier, gradually determine that a matching code exists between the second high-speed signal connection port identifier and a preset second high-speed signal connection code, and when the code of the second high-speed signal connection port identifier is determined to be matched with the preset second high-speed signal connection code, determine that the second high-speed signal connection port corresponding to the code of the second high-speed signal connection port identifier is the second high-speed signal connection port connected with the IO server.

In the embodiment of the invention, when the first primary I2CIO identification chip is in the operable state, the identifier of the second high-speed signal connection port is read; the operable state is determined by the IO server setting the first primary I2CIO identification chip; and determining a second high-speed signal connection port connected with the IO server based on the second high-speed signal connection port identification. When the first-level I2CIO identification chip is in an operable state, the second high-speed signal connection port identification is directly read, and the second high-speed signal connection port is determined, so that the I2C signal transmission port of the SSD server is identified.

In order to enable those skilled in the art to better understand the embodiments of the present application, the following description is given by way of an example:

referring to fig. 6, there is shown a schematic diagram of an identification circuit of an example of the identification method of the identification circuit based on multi-server identification of the present invention; the identification circuit is applied to a server cabinet, the server cabinet comprises an IO server and an SSD server, and the identification circuit is connected with the IO server and the SSD server respectively. Each port in the IO server is hung on the first branch I2CIO identification chip; each first I2CIO identification chip is connected with the corresponding first I2C expansion chip, and the first I2CIO identification chips under the same I2C signal line are connected with one first-level I2CIO identification chip. Each port in the SSD server is hung on a second sub I2CIO identification chip; each second I2CIO identification chip is connected with the corresponding second I2C expansion chip, and the second I2CIO identification chips under the same I2C signal line are connected with one second primary I2CIO identification chip. And the three ports in each SSD server are connected with the ports of the IO servers.

Referring to fig. 7, a schematic diagram illustrating steps of an example of the identification method of the identification circuit based on multi-server identification according to the present invention is shown;

when the IO server is interconnected with the CDFP port of the SSD server, the I2C of the IO server can enter the SSD server through the CDFP port, and after the server is powered on, the BMC (baseboard management controller) can read data based on the CDFP port of the SSD server and the CDFP port of the IO server; and further, I2C link communication between the IO server and the SSD server is realized.

When the ID identification process is started, the IO server pulls up the operable bit of the first-level I2CIO identification chip, the IO server starts to identify the CDFP ID of the SSD server from the CDFP port, and when the code of the second I2CIO identification chip (PCA 9554) is scanned to contain 010000, the SSD server in the current system can be confirmed to exist, and no additional data processing is needed.

Then, judging that the code of the second I2CIO identification chip contains 010000 number; and when only one is available, directly configuring the CDFP interface corresponding to the second I2CIO identification chip, and determining the connection relation between the CDFP interface and the IO server. When two I2CIO identification chips exist, determining the I2C channels and the sequence of the two second I2CIO identification chips; and setting a server identity identification bit of a second primary I2C identification chip (primary PCA9554 of the SSD server), determining a CDFP interface corresponding to a second secondary I2CIO identification chip containing the server identity identification bit, configuring the CDFP interface, and determining the connection relation between the CDFP interface and the IO server. When three I2CIO identification chips exist, determining the I2C channels and the sequence of the three second I2CIO identification chips; and setting the server identity identification position of the second primary I2C identification chip for the first time, and determining two second sub I2CIO identification chips containing the server identity identification position. And then, the server identity identification bits of the two second-level first-level I2C identification chips are set for the second time to determine a second sub I2CIO identification chip containing the server identity identification bit of this time, determine a CDFP interface corresponding to the second sub I2CIO identification chip, configure the CDFP interface and determine the connection relation between the CDFP interface and the IO server.

After the codes of the CDFP connected with the SSD server and the IO server are identified, a complete mapping relation can be established after the subsequent IO server is scanned, and the data instruction can be accurately sent to a specific port of a specific SSD server.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

Referring to fig. 8, a block diagram of an embodiment of an identification apparatus of an identification circuit based on multi-server identity according to the present invention is shown, where the identification circuit includes the identification circuit described above, and the apparatus is applied to the IO server, and the identification apparatus of the identification circuit based on multi-server identity may specifically include the following modules:

a setting module 801, configured to set the first level I2CIO identification chip in the operable state;

a first reading module 802, configured to read the first high-speed signal connection port identifier;

a first identifying module 803, configured to determine, based on the first high-speed signal connection port identifier, a first high-speed signal connection port connected to the SSD server.

In an optional embodiment of the present invention, the setting module 801 includes:

and the setting submodule is used for setting the operable bit of the first-level I2CIO identification chip to be a preset high level.

In an optional embodiment of the present invention, the first identifying module 803 includes:

the first reading submodule is used for reading the first high-speed signal connection port identification;

the first determining submodule is used for determining the number of the first high-speed signal connection port identifications matched with a preset first high-speed signal connection code;

the first identification submodule is used for determining that a first high-speed signal connection port corresponding to the first high-speed signal connection port identifier is a first high-speed signal connection port connected with the SSD server when the number corresponding to the first high-speed signal connection port identifier is single;

the first setting submodule is used for setting the IO server identity identification bit code of the first primary I2CIO identification chip to modify the code of the first high-speed signal connection port identification when the number corresponding to the first high-speed signal connection port identification is multiple;

and the second identification submodule is used for determining that the first high-speed signal connection port corresponding to the modified first high-speed signal connection port identifier is the first high-speed signal connection port connected with the SSD server when the modified code of the first high-speed signal connection port identifier contains the IO server identity identification bit code.

Referring to fig. 9, a block diagram of another embodiment of the identification apparatus of an identification circuit based on multi-server identifier according to the present invention is shown, where the identification circuit includes the identification circuit as described above, and the apparatus is applied to the SSD server, and the identification apparatus of the identification circuit based on multi-server identifier may specifically include the following modules:

a second reading module 901, configured to read the second high-speed signal connection port identifier when the first primary I2CIO identification chip is in the operable state; the operable state is determined by the IO server setting the first primary I2CIO identification chip;

a second identifying module 902, configured to determine, based on the second high-speed signal connection port identifier, a second high-speed signal connection port connected to the IO server.

In an optional embodiment of the present invention, when the IO server sets the operable bit of the first top level I2CIO identification chip to a preset high level, it is determined that the first top level I2CIO identification chip is in the operable state.

In an optional embodiment of the present invention, the second identifying module 902 includes:

the second reading submodule is used for reading the identifier of the second high-speed signal connection port;

the second determining submodule is used for determining the number of the second high-speed signal connection port identifications, which are matched with the preset second high-speed signal connection codes, corresponding to the second high-speed signal connection port identifications;

the third identification submodule is used for determining that the second high-speed signal connection port corresponding to the second high-speed signal connection port identifier is the second high-speed signal connection port connected with the IO server when the number corresponding to the second high-speed signal connection port identifier is single;

the second setting submodule is used for setting the SSD server identity identification bit code of the second first-level I2CIO identification chip to modify the code of the second high-speed signal connection port identification when the number corresponding to the second high-speed signal connection port identification is multiple;

and the fourth identification submodule is used for determining that the second high-speed signal connection port corresponding to the modified second high-speed signal connection port identifier is the second high-speed signal connection port connected with the IO server when the modified code of the second high-speed signal connection port identifier contains the SSD server identity identification bit code.

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

Referring to fig. 10, an embodiment of the present invention further provides an electronic device, including:

a processor 1001 and a storage medium 1002, wherein the storage medium 1002 stores a computer program executable by the processor 1001, and when the electronic device runs, the processor 1001 executes the computer program to perform the method for identifying a circuit based on identification of multiple servers according to any one of the embodiments of the present invention. The specific implementation manner and technical effects are similar to those of the method embodiment, and are not described herein again.

The Memory may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.

Referring to fig. 11, an embodiment of the present invention further provides a computer-readable storage medium 1101, where the storage medium 1101 stores a computer program, and the computer program is executed by a processor to perform the identification method of the identification circuit based on multi-server identification according to any one of the embodiments of the present invention. The specific implementation manner and technical effects are similar to those of the method embodiment, and are not described herein again.

Referring to fig. 12, an embodiment of the present invention further discloses a server enclosure, which includes an IO server 1201, an SSD server 1202, and the identification circuit 1203 for multiple server identifiers as described above. One end of the identification circuit 1203 is connected to the IO server 1201, and the other end of the identification circuit 1203 is connected to the SSD server 1202. The IO server 1201 and the SSD server 1202 are in the same resource pooling system.

The embodiments in the present specification are all described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same and similar between the embodiments may be referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the true scope of the embodiments of the present invention.

Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrases "comprising one of \ ...does not exclude the presence of additional like elements in a process, method, article, or terminal device that comprises the element.

The identification circuit, the identification method, the electronic device, and the storage medium of the multi-server identifier provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. The identification circuit of the multi-server identifier is characterized in that the multi-server comprises at least one input/output (IO) server and a Solid State Disk (SSD) server; the IO server comprises a plurality of first high-speed signal connection ports; the SSD server comprises a plurality of second high-speed signal connection ports; the identification circuit includes:

the first sub-I2 CIO identification chip is connected with any one first high-speed signal connection port and is used for generating and storing a first high-speed signal connection port identifier;

the second branch I2CIO identification chip is connected with any second high-speed signal connection port and is used for generating and storing a second high-speed signal connection port identifier;

and when the first primary I2CIO identification chip is in an operable state, identifying the first high-speed signal connection port identification and the second high-speed signal connection port identification to determine a first high-speed signal connection port and a second high-speed signal connection port which are connected with each other.

2. The identification circuit of claim 1, wherein the first top-level I2CIO identification chip comprises an operability bit; and when the operability bit is in a high bit, determining that the first primary I2CIO identification chip is in the operable state.

3. The identification circuit of claim 1, further comprising:

and the first I2C expansion chip and the first primary I2CIO identification chip are positioned under the I2C of the same IO server, and are used for expanding the I2C of the IO server to any first I2CIO identification chip and storing a first I2C expansion identifier.

4. The identification circuit of claim 1, further comprising:

and the second I2C expansion chip is connected with the plurality of second I2CIO identification chips and is used for expanding the I2C of the SSD server to any one of the second I2CIO identification chips and storing a second I2C expansion identifier.

5. The identification circuit of claim 4, further comprising:

6. The identification circuit of claim 1, wherein the first high-speed signal connection port identification comprises a wideband number and a first high-speed signal connection port code;

7. The identification circuit of claim 6 wherein the first high speed signal connection port identification is eight bit encoded; the first bit code to the third bit code are the first high-speed signal connection port code, the fourth bit code to the fifth bit code are the preset pending code, and the sixth bit code to the eighth bit code are the wideband number.

8. The identification circuit of claim 1, wherein the second high-speed signal connection port identification comprises an SSD server number, an SSD server identity, and a second high-speed signal connection port code;

9. The identification circuit of claim 8, wherein the second high speed signal connection port identification is eight bit encoded; the first bit code to the fourth bit code are used for coding the second high-speed signal connection port, the fifth bit code to the sixth bit code are used for coding the SSD server identity, and the seventh bit code to the eighth bit code are used for coding the SSD server number.

10. A method of identification of an identification circuit based on multi-server identification, the identification circuit comprising an identification circuit according to any of claims 1 to 9; the method is applied to the IO server and comprises the following steps:

setting the first primary I2CIO identification chip in the operable state;

reading the first high-speed signal connection port identification;

11. The method of claim 10, wherein setting the first primary I2CIO identification chip in the operable state comprises:

12. The method of claim 10, wherein determining a first high speed signal connection port to connect with the SSD server based on the first high speed signal connection port identification comprises:

reading the first high-speed signal connection port identification;

13. A method for identification of an identification circuit based on multi-server identification, characterized in that the identification circuit comprises an identification circuit according to claim 5; the method is applied to the SSD server, and comprises the following steps:

14. The method of claim 13, wherein the first top-level I2CIO identification chip is determined to be in the operable state when the IO server sets an operable bit of the first top-level I2CIO identification chip to a preset high level.

15. The method of claim 13, wherein the determining a second high-speed signal connection port connected to the IO server based on the second high-speed signal connection port identification comprises:

reading the second high-speed signal connection port identification;

when the number corresponding to the second high-speed signal connection port identifiers is multiple, setting SSD server identity identification bit codes of the second first-level I2CIO identification chip to modify the codes of the second high-speed signal connection port identifiers;

16. An identification arrangement for an identification circuit based on multi-server identification, characterized in that the identification circuit comprises an identification circuit according to any of claims 1 to 9; the device is applied to the IO server, and the device comprises:

17. An identification arrangement for an identification circuit based on multi-server identification, characterized in that the identification circuit comprises an identification circuit according to any of claims 1 to 9; the device is applied to the SSD server and comprises:

18. An electronic device, comprising a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of the method for identification of an identification circuit based on a multi-server identity of any one of claims 10 to 12 or of any one of claims 13 to 15.

19. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the method for identification of a multi-server identification based identification circuit according to any of the claims 10 to 12 or according to any of the claims 13 to 15.

20. A server rack comprising an IO server, an SSD server and a multi-server identification circuit as claimed in any of claims 1 to 9;