CN115686646A

CN115686646A - Chip starting method and device, storage medium and chip

Info

Publication number: CN115686646A
Application number: CN202211180787.5A
Authority: CN
Inventors: 杨健明; 黄立伟; 刘浩; 张静
Original assignee: Zhuhai Huge Ic Co ltd
Current assignee: Zhuhai Huge Ic Co ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2023-02-03

Abstract

The embodiment of the application discloses a chip starting method and device, a storage medium and a chip, and relates to the field of chips. This application represents the state of chip through setting up chip status register, and the chip does not dispose and starts the bootstrap area when the test is passed, just can start the bootstrap area for the chip configuration when the test is passed, because main code and bootstrap code have the dependency, consequently this application can avoid burning the bootstrap code before the test passes, improves efficiency of software testing.

Description

Chip starting method and device, storage medium and chip

Technical Field

The present disclosure relates to the field of chips, and in particular, to a method and an apparatus for starting a chip, and a storage medium.

Background

Before testing, a boot load area (bootload area) is set at the start address of the chip, and a section of solidified boot code is recorded in the boot load area, and the solidified boot code cannot be modified. When testing the chip, the chip will start running from the initial address when power is on, firstly, the boot code in the boot area is started, and after the boot code is executed, the chip jumps to the main code area (main area) to execute the main code. If the chip fails in the test process, the boot code in the boot start area cannot be configured and updated subsequently, and the flexibility is poor.

Disclosure of Invention

The embodiment of the application provides a chip starting method and device, a storage medium and a chip, and can solve the problem of poor flexibility caused by incapability of changing after burning and curing of a starting guide area in the prior art. The technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a chip starting method, where the method includes:

when power-on is detected, reading the value of a chip state register at an initial address;

if the value of the chip state register is a first preset value, reading a boot code in a boot area, and reading a main code area address in a main code area address register after the boot code is executed;

calling a main code in a main code area indicated by the main code area address, and executing the main code;

when an interrupt request is detected in the process of executing the main code, determining the interrupt type of the interrupt request and reading an interrupt vector table address of an interrupt vector address register;

inquiring an interrupt vector entry address corresponding to the interrupt type in an interrupt vector table according to the interrupt vector table indicated by the interrupt vector table address;

calling an interrupt processing program corresponding to the interrupt vector entry address to process the interrupt request;

if the value of the chip state register is a second preset value, calling the main code in the main code area from the initial address, and executing the main code.

In a second aspect, an embodiment of the present application provides a chip starting apparatus, where the apparatus includes:

the reading unit is used for reading the value of the chip state register at the initial address when power-on is detected;

the reading unit is further used for reading a boot code in a boot area if the value of the chip state register is a first preset value, and reading a main code area address in a main code area address register after the boot code is executed;

an execution unit for calling a main code in a main code area indicated by the main code area address and executing the main code;

the reading unit is further used for determining the interrupt type of the interrupt request and reading the interrupt vector table address of the interrupt vector address register when the interrupt request is detected in the process of executing the main code;

the query unit is used for querying an interrupt vector entry address corresponding to the interrupt type according to the interrupt vector table indicated by the interrupt vector table address;

the calling unit is used for calling an interrupt processing program corresponding to the interrupt vector entry address to process the interrupt request;

and the execution unit is also used for calling the main code in the main code area from the initial address and executing the main code if the value of the chip state register is a second preset value.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-mentioned method steps.

In a fourth aspect, an embodiment of the present application provides a chip, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:

setting a chip state register, when the value of the chip state register is a first preset value, indicating that the chip state is a test pass, wherein the chip is provided with a starting guide area and a main code area, determining the position of the main code area according to the value of an address register of the main code area, calling a main code in the main code area to execute, determining the position of an interrupt vector table according to the value of an interrupt vector address register, and calling the interrupt vector table to process various interrupt requests; if the value of the chip state register is the second preset value, the chip state is indicated to be the test failure, and the chip is only provided with a main program area so as to be convenient for the subsequent test of the chip. The chip state register is arranged to represent the state of the chip, the chip is not configured with the starting guide area when the test is failed, the starting guide area is configured for the chip until the test is passed, and the main code and the guide code have a dependency relationship, so that the guide code can be prevented from being burnt before the test is passed, and the test efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a network architecture provided in an embodiment of the present application;

fig. 2 is a schematic flowchart of a chip starting method according to an embodiment of the present application;

fig. 3 is a schematic diagram illustrating a memory space distribution of a chip according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a chip starting apparatus provided in the present application;

fig. 5 is a schematic structural diagram of a chip provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be noted that the chip starting method provided by the present application is generally executed by a chip starting device, and accordingly, the chip starting device is generally disposed in a chip.

Fig. 1 shows an exemplary system architecture that can be applied to the chip start-up method or the chip start-up apparatus of the present application.

As shown in fig. 1, the system architecture may include: a test fixture 101, a computer device 102, a chip (not shown in fig. 1), the test fixture 101 being provided with one or more sockets, the chip being embedded in the socket for communication with the test fixture 101. The test fixture 101 and the computer device 102 may communicate via a network, which is used as a medium for providing communication links between the various units described above. The network may include various types of wired or wireless communication links, such as: the wired communication link includes an optical fiber, a twisted pair wire, or a coaxial cable, etc., and the WIreless communication link includes a bluetooth communication link, a WIreless-FIdelity (Wi-Fi) communication link, or a microwave communication link, etc.

The test fixture 101 is provided with a plurality of sockets, and the chips are inserted into the sockets to be electrically connected with the computer device 102. The computer device 102 communicates with the test fixture 101 based on a serial port, the computer device 102 provides a graphical interface, and a tester performs interaction based on the graphical interface to test the test fixture 101 and configure a chip according to a test result, for example: and dividing the memory space, and configuring the address of the register and the value of the register.

The chip of the application can be a single chip microcomputer, a microcontroller, a processor or other integrated circuits with control functions.

It should be noted that the computer device 102 may be hardware or software. When the computer device 102 is hardware, it may be implemented as a distributed server cluster composed of multiple servers, or may be implemented as a single server. When the computer device 102 is software, it may be implemented as a plurality of software or software modules (for example, for providing distributed services), or may be implemented as a single software or software module, and is not limited in this respect.

Various communication client applications may be installed on the computer device 102 of the present application, such as: video recording application, video playing application, voice interaction application, search application, instant messaging tool, mailbox client, social platform software, etc.

The computer device 102 may be a variety of chip enabled devices with a display screen including, but not limited to, smart phones, tablet computers, laptop portable computers, desktop computers, and the like.

The display device of the computer device 102 may be various devices capable of implementing a display function, and the camera is used for collecting a video stream; for example: the display device may be a cathode ray tube (CR) display, a light-emitting diode (LED) display, an electronic ink screen, a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), or the like. The user can utilize the display equipment on the chip starting device to view information such as displayed characters, pictures, videos and the like.

It should be understood that the number of chips, networks, and computer devices in fig. 1 is merely illustrative. Any number of computer devices, networks, and servers are possible, as desired for an implementation.

The chip start-up method provided by the embodiment of the present application will be described in detail below with reference to fig. 2. The chip starting device in the embodiment of the present application may be the chip starting device shown in fig. 1.

Fig. 2 is a schematic flow chart of a chip starting method according to an embodiment of the present disclosure. As shown in fig. 2, the method of the embodiment of the present application may include the steps of:

s201, when power-on is detected, reading the value of the chip state register at the initial address.

In this embodiment, a plurality of storage units are disposed in a memory space of a chip, where the storage units may be used to store program codes or data, each storage unit is provided with a storage address, a start address indicates a first storage address of the chip, a chip status register is disposed in a storage unit indicated by the start address, the chip status register is used to indicate a status of the chip, and the status of the chip includes a test pass and a test fail, or a streamed chip and an un-streamed chip, and the following example is described with the test pass and the test fail.

In the embodiment of the application, the value of the chip state register can be configured by the chip starting device, the chip starting device establishes communication connection with the chip, and then the chip starting device configures the value of the chip state register according to the test result after testing by using the test case chip.

S202, if the value of the chip state register is a first preset value, reading a boot code in a boot area, and after the boot code is executed, reading a main code area address in a main code area address register.

In this embodiment of the present application, the first preset value indicates that the state of the chip is a test-passed state or a taped-out state, and then the chip is provided with a boot strap region and a main code region, the boot strap region is provided with a boot code, the boot strap region is provided with a chip state register in S201 and a main code region address register in S202, a value of the main code region address register indicates a main code region address, and the main code region address indicates a storage address of at least one storage unit included in the main code region. The address register of the main code area is set in the boot area.

In the embodiment of the application, when the chip starting device passes the test, the address of the main code area is configured in the address register of the main code area, and the address of the main code area is related to the size of the starting guide area because the starting guide area is adjacent to the main code area.

Furthermore, the boot strap region is further provided with a soft reset code, after the boot code is executed, the soft reset code is called to perform soft reset, the soft reset range does not include a chip state register, a main code region address register and an interrupt vector address register, namely, the chip does not reset the values of the chip state register, the main code region address register and the interrupt vector address register when executing the soft reset based on the soft reset code, and the soft reset range includes other variable registers except the 3 registers in the boot strap region.

S203, calling the main code in the main code area indicated by the main code area address, and executing the main code.

The chip calls the main code and executes the main code.

S204, when the interrupt request is detected in the process of executing the main code, determining the interrupt type of the interrupt request and reading the interrupt vector table address of the interrupt vector address register.

When an interrupt request sent by an interrupt source is detected in the process of executing the main code, determining the interrupt type of the interrupt request, wherein the interrupt type includes but is not limited to: the method comprises the steps of external Interrupt (INT), timer interrupt (T) and serial port interrupt (RXD), wherein the value in an interrupt vector address register represents an interrupt vector table address, the interrupt vector table address represents the address of an interrupt vector table stored in a main code area, and the mapping relation between an interrupt vector entry address and an interrupt type is stored in the interrupt vector table.

S205, inquiring an interrupt vector entry address corresponding to the interrupt type in the interrupt vector table according to the interrupt vector table address.

S206, calling an interrupt processing program corresponding to the interrupt vector entry address to process the interrupt request.

And S207, if the value of the chip state register is the second preset value, calling the main code in the main code area from the initial address, and executing the main code.

The chip starting device carries out function test on the chip in the execution process of the main code, modifies the main code when the test result is that the test does not pass, then burns the modified main code into the main code area, and sets the value of the chip state register as a second preset value. In the embodiment of the application, an interrupt vector table is arranged in a main code area, when an interrupt request is detected, a corresponding interrupt vector entry address is inquired in the interrupt vector table according to the interrupt type of the interrupt request, and then a corresponding interrupt processing program is called according to the inquired interrupt vector entry address. Wherein, the test failure comprises two conditions of test failure and test failure.

Further, when the chip passes the test or is subjected to the tape-out, the chip starting device configures a starting boot area and a main code area for the chip, the starting boot area is set from the initial address of the chip, a chip state register, a main code area address register and an interrupt vector address register are arranged in the starting boot area, and the value of the chip state register is set to be a first preset value. When the chip test is not passed or the chip is not subjected to tape-out, the chip starting device configures a main code area for the chip, the main code area is set from the initial address of the chip, a chip state register is arranged in the main code area, the value of the chip state register is set to be a second preset value, and the chip starting device tests the chip at the moment.

For example: referring to the distribution diagram of the memory space of the chip shown in fig. 3, the chip is provided with a boot region and a main code region, the boot region and the main code region are continuously distributed, and a chip state register (register 1), a main code region address register (register 2), and an interrupt vector address register (register 3) are arranged in the boot region.

In some embodiments of the present application, S201 further includes before:

when the chip state is a test pass or a tape-out state, receiving a first configuration instruction from a chip starting device;

and configuring a starting guide area and a main code area for the chip according to the first configuration instruction, and burning a guide code in the starting guide area.

The first configuration instruction configures addresses of a chip state register, a main code area address register and an interrupt vector address register, configures a value of the chip state register to be a first preset value, and configures values of the main code address register and the interrupt vector address register according to actual requirements. Furthermore, in order to improve the utilization rate of the chip memory, the interrupt vector table address is adjacent to the end address of the start boot sector, i.e. in a continuous distribution. Then, a boot code is burned in the boot start area, and the chip is started according to the process from S201 to S206 after burning is completed and the chip is powered on next time.

In some embodiments of the present application, S201 further includes before:

and when the chip state is a test failure, receiving a second configuration instruction from a chip starting device, configuring a main code area for the chip according to the second configuration instruction, and burning the modified main code in the main code area.

And the second configuration instruction configures a main code area at the initial address of the chip, then sets the address of the chip state register in the main code area, and configures the value of the chip state register to be a second preset value. And after the test is failed, the tester can check and modify the main code, the second configuration instruction is also used for burning the modified main code into the main code area, then testing the chip again, and executing a corresponding configuration process according to a test result.

The method comprises the steps that a chip state register is set, when the value of the chip state register is a first preset value, the chip state is indicated to be passed through testing, a starting guide area and a main code area are arranged on the chip, the position of the main code area is determined according to the value of an address register of the main code area, the main code in the main code area is called to execute, the position of an interrupt vector table is determined according to the value of an interrupt vector address register, and the interrupt vector table is called to process various types of interrupt requests; if the value of the chip state register is a second preset value, the chip state is indicated as that the test is not passed, and the chip is only provided with a main program area so as to test the chip in the following. The chip state register is arranged to represent the state of the chip, the chip is not configured with the starting guide area when the test is failed, the starting guide area is configured for the chip until the test is passed, and the main code and the guide code have a dependency relationship, so that the guide code can be prevented from being burnt before the test is passed, and the test efficiency is improved.

The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.

Referring to fig. 4, a schematic structural diagram of a chip start device provided in an exemplary embodiment of the present application is shown, which is hereinafter referred to as device 4. The means 4 may be implemented as all or part of a chip by software, hardware or a combination of both. The device 4 comprises: reading unit 401, executing unit 402, querying unit 403, and calling unit 404.

A reading unit 401, configured to read a value of a chip status register at an initial address when power-on is detected;

the reading unit 401 is further configured to read a boot code in a boot area if the value of the chip status register is a first preset value, and read a main code area address in a main code area address register after the boot code is executed;

an execution unit 402, configured to call a main code in a main code area indicated by the main code area address, and execute the main code;

the reading unit 401 is further configured to, when an interrupt request is detected during execution of the main code, determine an interrupt type of the interrupt request and read an interrupt vector table address of an interrupt vector address register;

a query unit 403, configured to query, according to the interrupt vector table indicated by the interrupt vector table address, an interrupt vector entry address corresponding to the interrupt type;

a calling unit 404, configured to call an interrupt handler corresponding to the interrupt vector entry address to process the interrupt request;

the execution unit 401 is further configured to call a main code in the main code area from the start address and execute the main code if the value of the chip status register is the second preset value.

In one or more possible embodiments, the method further comprises:

the configuration unit is used for receiving a first configuration instruction from the chip starting device when the chip state is the test passing state;

configuring a starting guide area and a main code area for the chip according to the first configuration instruction, and burning a guide code in the starting guide area; the starting guide area is provided with a chip state register, a main code area address register and an interrupt vector address register, and the value of the chip state register is configured to be a first preset value.

In one or more possible embodiments, the method further comprises:

the configuration unit is used for receiving a second configuration instruction from the chip starting device when the chip state is in a test failure state, configuring a main code area for the chip according to the second configuration instruction, and burning the modified main code in the main code area; and the main code area is provided with a chip state register, and the value of the chip state register is configured to be a second preset value.

In one or more possible embodiments, the boot strap region is further provided with a soft reset code;

further comprising:

and the reset unit is used for calling the soft reset code to perform soft reset after the execution of the boot code is finished, and the soft reset range does not comprise a chip state register, a main code area address register and an interrupt vector address register.

In one or more possible embodiments, the communication with the chip start-up device is via a serial port.

In one or more possible embodiments, the interrupt vector table address is adjacent to an end address of the boot sector.

In one or more possible embodiments, the interrupt types include: external interrupt, timer interrupt, serial port interrupt.

It should be noted that, when the apparatus 4 provided in the foregoing embodiment executes the chip starting method, only the division of each functional module is illustrated as an example, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the chip starting device and the chip starting method provided by the above embodiments belong to the same concept, and the details of the implementation process are referred to as method embodiments, which are not described herein again.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are suitable for being loaded by a processor and executing the method steps in the embodiment shown in fig. 2, and a specific execution process may refer to a specific description of the embodiment shown in fig. 2, which is not described herein again.

The present application further provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the chip starting method according to the above embodiments.

Fig. 5 is a schematic diagram of a chip according to an embodiment of the present disclosure. As shown in fig. 5, the chip 500 may include: at least one processor 501, at least one network interface 504, memory 503, at least one communication bus 502.

Wherein a communication bus 502 is used to enable connective communication between these components.

The network interface 504 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Processor 501 may include one or more processing cores, among other things.

The processor 501 connects various parts within the entire chip 500 using various interfaces and lines, and performs various functions of the chip 500 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 503 and calling data stored in the memory 503. Optionally, the processor 501 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 501 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 501, but may be implemented by a single chip.

The Memory 503 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 503 includes a non-transitory computer-readable medium. The memory 503 may be used to store instructions, programs, code sets or instruction sets. The memory 503 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-mentioned method embodiments, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 503 may optionally be at least one storage device located remotely from the processor 501. As shown in fig. 5, the memory 503, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and an application program.

In the chip 500 shown in fig. 5, the processor 501 may be configured to call an application program stored in the memory 503 and specifically execute the method shown in fig. 2, and the specific process may refer to fig. 2 and is not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, an optical disk, a read-only memory or a random access memory.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.

Claims

1. A method for starting up a chip, comprising:

inquiring an interrupt vector entry address corresponding to the interrupt type according to an interrupt vector table indicated by the interrupt vector table address;

2. The method of claim 1, wherein upon detecting power-up, prior to reading a value of a chip status register at a start address, further comprising:

when the chip state is passed through the test, receiving a first configuration instruction from a chip starting device;

3. The method of claim 1, wherein upon detecting power-up, prior to reading a value of a chip status register at a start address, further comprising:

when the chip state is in a test failure state, receiving a second configuration instruction from a chip starting device, configuring a main code area for the chip according to the second configuration instruction, and burning the modified main code in the main code area; and the main code area is provided with a chip state register, and the value of the chip state register is configured to be a second preset value.

4. A method according to claim 2 or 3, characterized in that the boot strap is further provided with a soft reset code;

the method further comprises the following steps:

and after the execution of the boot code is finished, calling the soft reset code to perform soft reset, wherein the soft reset range does not comprise a chip state register, a main code area address register and an interrupt vector address register.

5. A method according to claim 2 or 3, characterized in that the communication with the chip start-up device is performed via a serial port.

6. A method according to claim 1, 2 or 3, wherein the interrupt vector table address is adjacent to the end address of the boot sector.

7. The method of claim 6, wherein the interrupt type comprises: external interrupt, timer interrupt, serial port interrupt.

8. A chip startup device, comprising:

the reading unit is further configured to read a boot code in a boot area if the value of the chip status register is a first preset value, and read a main code area address in a main code area address register after the boot code is executed;

9. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any one of claims 1 to 7.

10. A chip, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 7.