CN113972989B

CN113972989B - Data verification method, storage medium and electronic equipment

Info

Publication number: CN113972989B
Application number: CN202010641808.3A
Authority: CN
Inventors: 虎跃
Original assignee: Yulong Computer Telecommunication Scientific Shenzhen Co Ltd
Current assignee: Yulong Computer Telecommunication Scientific Shenzhen Co Ltd
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2023-09-15
Anticipated expiration: 2040-07-06
Also published as: CN113972989A

Abstract

The embodiment of the application discloses a data verification method, a device, a storage medium and electronic equipment, wherein the method comprises the following steps: and acquiring mirror image data transmitted by a server, acquiring a target data block in at least one data block included in the mirror image data, controlling a second processor to perform data verification on the target data block when the first processor is in a verification state, and controlling a third processor to perform data writing on the target data block after the target data block passes verification. By adopting the embodiment of the application, the data verification efficiency can be improved.

Description

Data verification method, storage medium and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data verification method, a data verification device, a storage medium, and an electronic device.

Background

With the development of communication technology, data verification is particularly important, and the technology of verifying input data by ensuring the integrity, the correctness and the safety of data is an important means for system and user data security in the internet technology.

At present, in the process of checking data, a terminal can allocate a target processor in the contained processor and then adopt a serial execution mode, the target processor acquires mirror image data of data check, then performs data check on the mirror image data, and writes the mirror image data after the data check, for example, when an operating system of the terminal is upgraded, the terminal can firstly acquire the mirror image data of the operating system upgrade in a fast boot (fastboot) mode by designating one processor in a serial execution mode, then performs data check through the processor, and writes the mirror image data after the data check, thereby completing the whole data check flow of the mirror image data.

Disclosure of Invention

The embodiment of the application provides a data verification method, a data verification device, a storage medium and electronic equipment, which can improve the data verification efficiency. The technical scheme of the embodiment of the application is as follows:

in a first aspect, an embodiment of the present application provides a data verification method, where the method includes:

obtaining mirror image data transmitted by a server side, and obtaining a target data block in at least one data block included in the mirror image data;

when the first processor is in a verification state, controlling the second processor to perform data verification on the target data block;

and after the verification of the target data block is passed, controlling a third processor to write data into the target data block.

In a second aspect, an embodiment of the present application provides a data verification apparatus, including:

the system comprises a target data block determining module, a target data block determining module and a data processing module, wherein the target data block determining module is used for acquiring mirror image data transmitted by a server and acquiring a target data block in at least one data block included in the mirror image data;

the data verification module is used for controlling the second processor to carry out data verification on the target data block when the first processor is in a verification state;

and the data writing module is used for controlling the third processor to write data into the target data block after the verification of the target data block is passed.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-described method steps.

In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

The technical scheme provided by the embodiments of the application has the beneficial effects that at least:

in one or more embodiments of the present application, a terminal obtains mirror image data transmitted by a server, obtains a target data block in at least one data block included in the mirror image data, and when a first processor is in a verification state, controls a second processor to perform data verification on the target data block, and after the target data block passes the verification, controls a third processor to perform data writing on the target data block. The method has the advantages that the target data block corresponding to the mirror image data is obtained by adopting a block transmission mode for the mirror image data, when the first processor for data verification is in a verification state, the parallel execution mode of the data verification can be adopted, the second processor is controlled to carry out the verification on the target data block in parallel, and the third processor is controlled to carry out the data writing on the data block after the verification, so that the problem of low data verification efficiency in the serial execution of the data verification in the related art can be avoided, the efficiency in the data verification process is improved, and the flow of the data verification is carried out through the parallel execution of a plurality of processors (such as the first processor, the second processor and the third processor), so that the time of the data verification is saved.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a data verification method according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating another data verification method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a data verification device according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a data verification module according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another data verification device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an operating system and user space provided by an embodiment of the present application;

FIG. 8 is an architecture diagram of the android operating system of FIG. 6;

FIG. 9 is an architecture diagram of the IOS operating system of FIG. 6.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it should be noted that, unless expressly specified and limited otherwise, "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

In the related art, during the data verification process, the terminal may allocate a target processor to the included processor, obtain complete mirror image data, obtain mirror image data of the data verification by the target processor, perform data verification on the mirror image data, and write the mirror image data after the data verification, however, by adopting such a data verification serial execution mode, the efficiency is generally lower, and when the file of the mirror image data is larger, it takes more time to perform the processes of data verification such as data downloading, data verification, data writing, and the like.

The present application will be described in detail with reference to specific examples.

In one embodiment, as shown in fig. 1, a data verification method is specifically proposed, which may be implemented in dependence on a computer program, and may be run on a data verification device based on von neumann system. The computer program may be integrated in the application or may run as a stand-alone tool class application.

Specifically, the data verification method comprises the following steps:

the data verification device in the embodiment of the present application may be a terminal, where the terminal may be an electronic device with a network experience state determining function, and the electronic device includes but is not limited to: wearable devices, handheld devices, personal computers, tablet computers, vehicle-mounted devices, smart phones, computing devices, or other processing devices connected to a wireless modem, etc. Terminal devices in different networks may be called different names, for example: a user equipment, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent or user equipment, a cellular telephone, a cordless telephone, a personal digital assistant (personal digital assistant, PDA), a terminal device in a 5G network or a future evolution network, and the like.

The server may be an electronic device, which may be a personal computer, a tablet computer, or the like, and may also be a server, which may be a separate server device, for example: the rack-mounted, blade, tower-type or cabinet-type server equipment can also adopt a workstation, a mainframe computer, or other hardware equipment with relatively high computing capacity, or can also adopt a server cluster formed by a plurality of servers, wherein each server in the server cluster can be formed in a symmetrical mode, each service is functionally equivalent and functionally equivalent in a service link, each server can independently provide services to the outside or the inside, such as a service platform for providing mirror image data, and the independent service providing can be understood as not needing the assistance of another server.

Step S101: and acquiring mirror image data transmitted by a server side, and acquiring a target data block in at least one data block included in the mirror image data.

The mirror image data is understood to be a form of storing data in a mirror image, and in practical application, a specific series of files are usually manufactured into single file data according to a certain format to be characterized, so as to facilitate downloading and using of the terminal, such as an operating system, a game, an application program and the like.

In some scenarios, the image data may be image data of a Basic Input/output system (Basic Input OutputSystem, BIOS), and may provide a bottom layer, direct hardware setting or control interface for an operating system of the terminal, where the operating system of the terminal may control the hardware system through the BIOS, and taking the operating system of the terminal as an Android system (Android system) as an example, a common method for writing BIOS image data may be to write BIOS image data through a fastboot brush mode.

Specifically, the server may be a service providing device that provides a service for obtaining mirror image data, where the server may be capable of generating mirror image data (such as BIOS mirror image data) or obtaining mirror image data (such as BIOS mirror image data provided) and sending the mirror image data to the terminal, and when receiving the mirror image data, the terminal may write data into a target data block that is currently checked by the mirror image data while checking each data block included in the mirror image data.

In practical applications, after receiving the mirror data of the server, the terminal may generally include at least one data block, and the server may send the at least one data block included in the mirror data to the terminal in real time or periodically in the form of a "data block" stream, for example, the terminal may acquire the data block 1 of the server at a time point T1, acquire the data block 2 of the server at a time point T2, acquire the data block 3 of the server and the data block 4 of the server at a time point T3.

The target data block may be understood as a current data block to be checked, which is determined by the terminal, and the determining rule of the target data block may be that a receiving time rule of the data block is followed, that is, a data block with an earlier receiving time is determined as the target data block based on a time dimension; the determining rule of the target data block may be determined based on a block sequence of the data blocks, for example, before the server transmits the plurality of data blocks included in the mirror image data, that is, determining the block sequence of each data block, the terminal may determine the current target data block to be verified based on a fast sequence of the data blocks; the determining rule of the target data block may be based on the priority of the currently received data block, for example, the service side has previously determined the priority of each data block (the priority may be determined according to the corresponding functional attribute of each data block); the determining rule of the target data block may be based on the memory size of the data block, for example, the terminal may check the data block with a relatively large memory of the data block as the target data block, for example, check the data block with a relatively small memory of the data block as the target data block, and for example, the terminal may combine the current remaining memory space and the memory size of each data block, and select the data block matched with the remaining memory space as the target data block for checking.

It should be noted that the number of the target data blocks may be one or more, that is, the terminal may determine a plurality of target data blocks in the above manner, and perform data verification and data writing on the plurality of target data blocks.

Further, in practical applications, the terminal may preset a central processor (or may be a main processor), where the central processor may be one or may be a processor cluster formed by multiple processors, and in the embodiment of the present application, the central processor is only used to distinguish from other processors (such as a first processor and a second processor) in the embodiment of the present application, it is to be understood that the terms "central", "first", "second", and the like are only used for describing purposes, and are not to be construed as indicating or implying relative importance. The central processor may also be equivalent to other processors in terms of functions, performance, etc., as determined by the implementation environment and is not specifically limited herein.

The terminal can control the central processor to acquire mirror image data transmitted by the server, and further acquire a target data block in at least one data block included in the mirror image data. On the one hand: the central processor may be controlled to determine the state of other processors (e.g., first processor, second processor), such as whether the first processor is in a check state; on the one hand: the central processor can be controlled to put the target data block into a check pool to be checked by a processor (such as a first processor) to be used for checking the data block; on the one hand: when the control center processor determines that the first processor is in the checking state, the second processor can be triggered (e.g. wake up the second processor) to check the target data block. Thereby improving the efficiency of verifying the data block of the mirror image data.

When the data communication is performed between the server and the terminal, a communication network between the two ends can be pre-established, the communication network can be a wired network or a wireless network, the wired network can be connected with a data interface on the terminal in a universal serial/parallel bus manner, and the data interface comprises but is not limited to a 3.5mm earphone jack, a USB interface, a Type-C interface, a Lightning interface and the like. The wireless network may be the internet, but may also be any other network including, but not limited to, a local area network (Local Area Network, LAN), metropolitan area network (Metropolitan Area Network, MAN), wide area network (Wide Area Network, WAN), a mobile, wired or wireless network, a private network, or any combination of virtual private networks.

In the embodiment of the application, when the server and the terminal exchange data via a communication network (for example, the server sends mirror image data to the terminal), technologies and/or formats including hypertext markup Language (HTML) and extensible markup Language (Extensible Markup Language, XML) may be used to represent the data exchanged via the network. All or some of the communication network links may also be encrypted using conventional encryption techniques such as secure socket layer (Secure Socket Layer, SSL), transport layer security (Transport Layer Security, TLS), virtual private network (Virtual Private Network, VPN), internet protocol security (Internet Protocol Security, IPsec), and the like. Custom and/or dedicated data communication techniques may also be used in place of or in addition to the data communication techniques described above.

Step S102: and when the first processor is in a verification state, controlling the second processor to perform data verification on the target data block.

The first processor may be understood as a processor of the terminal for performing data verification on a data block corresponding to the mirror data.

The verification state may be understood as that the first processor is performing data verification on a data block, and in practical application, on the one hand: when the first processor is performing data verification on a last data block or a historical data block corresponding to the target data block, in terms of the processing capacity dimension of the processor, the data verification on the target data block is generally difficult, at the moment, the terminal can determine that the first processor is in a verification state, and the data verification on the target data block is difficult in real time; on the one hand: when the resource surplus of the first processor is difficult to support data verification on the target data block, in terms of the processing capability dimension of the processor, it is generally difficult to perform data verification on the target data block at this time, and the terminal can determine that the first processor is in a verification state.

In a specific implementation scenario, the terminal may detect whether the first processor is performing data verification on a previous data block or a historical data block corresponding to the target data block, when the first processor is performing data verification on the previous data block or the historical data block corresponding to the target data block, the terminal may determine that the first processor is in a verification state, based on timeliness consideration of data verification, the terminal may control the second processor to perform data verification, that is, trigger the second processor to perform data verification on the target data block, thereby implementing quick verification on the target data block, and meanwhile, when the first processor of the terminal is in a verification state, adopting a mode of performing data verification by using multiple processors, so that the efficiency of data verification can be greatly improved. Further, in practical application, when the second processor does not perform data verification on the data block, the terminal may control the second processor to be in a low power consumption state or a sleep state, so as to save power consumption of the terminal, and when the second processor needs to be invoked to perform data verification, the terminal may wake up and online the second processor by sending a computer executable instruction to the second processor.

In a specific implementation scenario, the first processor may have the capability of performing data verification on multiple data blocks at the same time, and at this time, the terminal may acquire a resource surplus of the first processor, and then determine, based on the resource surplus and a requirement for processing a current target data block, whether the first processor is in a verification state, so that data verification processing cannot be performed on the target data block.

The resource surplus may be understood as an amount of resources left by a processor to meet the resource requirements of a currently running service thread (e.g. a service thread that processes data checking of a data block), where the resources are mainly computing resources of the processor (CPU, GPU), and the definition of the resources may be a memory size, a number of I/O ports, a computing unit, a control unit, etc. associated through the I/O ports. In the embodiment of the application, the terminal can acquire the preset current resource surplus of the first processor, in the specific implementation, a process for monitoring the current resource surplus of the first processor can be created in advance, and the computing resources of the resource pool are allocated for the process and used for monitoring the current resource surplus of the first processor in real time or periodically, and the terminal can acquire the current resource surplus of the first processor through the process.

Further, the required amount of the target data block may be determined based on the memory size of the target data block, the terminal may preset a corresponding relation between the memory size and the required amount, determine the required amount of the target data block based on the corresponding relation, and determine that the first processor is in a non-verification state when the current resource surplus of the first processor is greater than or equal to the required amount of the target data block; when the current resource surplus of the first processor is smaller than the required amount of the target data block, determining that the first processor is in a verification state, and in the first processor in the verification state, generally, the data verification of the target data block is difficult in the aspect of the processing capacity dimension of the processor; based on timeliness consideration of data verification, the terminal can control the second processor to perform data verification, namely, the second processor is triggered to perform data verification on the target data block, so that quick verification on the target data block is realized.

Specifically, the terminal may perform the checking on the target data block based on a set checking algorithm, such as a parity checking algorithm, bcc exclusive-or checking method (block check character), CRC cyclic redundancy check (Cyclic Redundancy Check), MD checking algorithm, and the like.

Taking CRC cyclic redundancy check as an example, in practical application, a transmitting end (e.g. a server end) generates an r-bit supervisory code (CRC code) for checking according to a rule corresponding to the CRC cyclic redundancy check according to mirror data (e.g. k-bit binary code sequence) contained in a data block to be transmitted, and the r-bit supervisory code (CRC code) is attached to the data block (e.g. the rear edge of the contained mirror data) to form a new data block (usually at least k+r bits of binary code sequence number) and then transmits the new data block. At the receiving end (such as a terminal), checking calculation is performed according to rules followed between the information code (such as the contained mirror image data) and the CRC code, comparison is performed according to the checking calculation result and the CRC code carried in the data block, if the checking calculation result is consistent with the CRC code, the data of the received data block is complete, and if the checking calculation result is inconsistent with the CRC code, the data of the data block is in error.

In practical application, the specifically adopted data verification algorithm may be determined according to a predetermined data verification rule of the transmitting end and/or the receiving end, and may be one or more of the above mentioned fitting, or may be an algorithm related to data verification in a related technology, which is not specifically limited herein, and typically, the service end at least includes an algorithm identifier and a verification value corresponding to the verifiable algorithm in a data block sent to the terminal, so that the terminal may receive the data block and perform corresponding data verification.

Step S103: and after the verification of the target data block is passed, controlling a third processor to write data into the target data block.

The third processor may be understood as a processor that performs data writing on the data block data after the data of the data block corresponding to the mirror image data passes the verification of the terminal. It can be understood that in the embodiment of the present application, data verification and data writing are performed by different processors, so that efficiency of data block writing and data block verification in a data verification process can be greatly improved, and further, when a terminal receives multiple data blocks corresponding to mirror image data transmitted by a server side at the same time, the terminal can use the multiple data blocks as target data blocks, and parallel processing, such as parallel data verification, parallel data writing, etc., of the mirror image data is implemented by executing the method of the embodiment of the present application.

The third processor may be a processor for processing data writing, which is determined in advance by the terminal based on the processing speeds of the plurality of processors included, for example, the terminal may be a specified number (e.g., 1) of processors for which the data writing speed is the fastest as the third processor.

Specifically, after the target data block in at least one data block included in the mirror image data is acquired by the terminal, and the target data block is verified, a target thread for writing the data block to the target data block is established, and computing resources of a resource pool included in the terminal are called for the target thread, so that data writing after the target data block is verified is realized. Further, the terminal can acquire a data writing state of the third processor, and when the data writing state meets the requirement of writing the data of the target data block, the third processor is controlled to write the data of the target data block; when the data writing state does not meet the requirement of writing the target data block data, the terminal may trigger a fourth processor in an idle state to write the data to the target data block, where the fourth processor may be understood as a processor on the terminal except for the first processor and the third processor, and in some implementation scenarios, when the second processor is in an idle state (or a sleep state), the fourth processor and the second processor may be the same processor.

Further, the data writing state of the third processor may be represented by a resource margin of the third processor, the requirement of writing the target data block data may be represented by a resource demand of writing the target data block data, and when the resource margin is greater than or equal to the resource demand, the terminal controls the third processor to write the data into the target data block; and when the resource surplus is smaller than the resource demand, the terminal triggers a fourth processor in an idle state to write data into the target data block.

Specifically, the terminal may control the third processor to write the data into the target data block, which may be directly written into the original data corresponding to the mirror image data, where the original data may be understood as the data to be covered on the terminal (such as files corresponding to some applications). When the terminal determines that the data verification of the target data block passes, the terminal may determine the original data to be covered corresponding to the mirror image data represented by the target data block (i.e., determine the original data to be covered corresponding to the target data block), and then cover the original data based on the data in the target data block.

Specifically, the terminal checks the target data block by controlling the second processor, and under the condition that the check value carried by the target data block is consistent with the check value carried by the target data block, the terminal can determine that the target data block passes the check, and then can control the third processor to perform data analysis processing on the target data block, and then determine a mapping path when the data in the target data block is updated, wherein the mapping path generally corresponds to a storage address to which original data to be covered on the terminal belongs, such as determining a file name of a directory file to be covered, and then the terminal controls the third processor to write the data in the target data block into the storage address indicated by the mapping path, so as to complete data coverage of the original data on the storage address, thereby realizing data writing of the target data block.

In the embodiment of the application, a terminal acquires mirror image data transmitted by a server, acquires a target data block in at least one data block included in the mirror image data, and controls a second processor to perform data verification on the target data block when a first processor is in a verification state, and controls a third processor to perform data writing on the target data block after the target data block passes verification. The method has the advantages that the target data block corresponding to the mirror image data is obtained by adopting a block transmission mode for the mirror image data, when the first processor for data verification is in a verification state, the parallel execution mode of the data verification can be adopted, the second processor is controlled to carry out the verification on the target data block in parallel, and the third processor is controlled to carry out the data writing on the data block after the verification, so that the problem of low data verification efficiency in the serial execution of the data verification in the related art can be avoided, the efficiency in the data verification process is improved, and the flow of the data verification is carried out through the parallel execution of a plurality of processors (such as the first processor, the second processor and the third processor), so that the time of the data verification is saved.

Referring to fig. 2, fig. 2 is a flowchart illustrating another embodiment of a data verification method according to the present application. Specific:

step S201: and detecting the performance of all the contained processors, and determining the corresponding processing speed of each processor.

Specifically, before data verification is performed, the terminal can perform performance detection on all the contained processors in an actual application environment, and detect hardware performance parameters of the terminal; the hardware performance parameters include the processor's overall operational speed, single-thread Cheng Zhengshu operational speed, single-thread floating-point number operational speed, multi-thread Cheng Zhengshu operational speed, multi-thread floating-point number operational speed, and so forth. In an actual test scenario, at least one of single-thread Cheng Zhengshu operation, single-thread floating point operation, multi-thread Cheng Zhengshu operation and multi-thread floating point operation is adopted to respectively execute a preset test operation task, wherein the test operation task can be understood as a data verification task, a data writing task, a data analysis task and the like. And determining the corresponding processing speed of the processor according to the operation result and the operation completion time length respectively corresponding to each test operation task.

In practical application, the processing speed may include a processing speed (such as a data verification speed, a data writing speed, a data analysis speed) under a plurality of test operation scenarios, and a comprehensive processing speed, where the comprehensive processing speed calculates a determined speed value based on the processing speed weighting under each test operation scenario.

In practical applications, the processor operation speed itself is floating, i.e. the processor frequency, and can be understood as the total amount of binary computations in a single cycle. The logical operation can be understood as an entirety of a large number of binary computations. Testing integer and floating point number calculation through single thread and multiple threads, quantifying the tested result, and testing the efficiency of the processor by calculating the time length of the processor for completing quantitative logic operation. For example, the performance of the processor can be judged according to the time of completion of the operation, and the shorter the time is, the better the performance, i.e. the faster the operation speed is. Preferably, the single-thread Cheng Zhengshu operation, the single-thread floating-point operation, the multi-thread Cheng Zhengshu operation, and the multi-thread floating-point operation execute logic operations with the same priority.

Furthermore, by adopting the method, the terminal can determine the corresponding processing speed of each processor through performance detection of all the contained processors.

Step S202: among the processors, the processor with the highest processing speed is taken as a third processor, and the processors except the third processor are taken as first processors.

The third processor is used for writing data into the data block in the data checking process, and the first processor is used for checking the data block in the data checking process.

Specifically, the terminal may use the processor with the highest processing speed as the third processor for writing data into the data block, and then use the processor with the highest processing speed except for the third processor as the first processor for performing data verification on the data block. Further, when the number of the third processors or the first processors is plural, the terminal may determine a specified number of the first processors or the third processors based on the processing speeds of the respective processors, for example, the first 2 processors having the highest processing speed are taken as the third processors.

Alternatively, the terminal may determine the corresponding processor based on the processing type (such as data verification type, data writing type), for example, the processor with the fastest data writing is used as the third processor, and the processor with the fastest data verification speed except for the third processor is used as the first processor.

Step S203: and acquiring mirror image data transmitted by a server side, and acquiring a target data block in at least one data block included in the mirror image data.

See step S101, and will not be described here.

Step S204: and obtaining a processor running log, and determining that the processor running log does not have an abnormal processing identifier.

The processor running log is used for recording relevant running information of at least one processor contained in the terminal in the running process, such as recording a processed target data block at a certain time point, processor resource overhead for processing the target data block, processor slicing time, context switching time, abnormal processing identification when the target data block is abnormally processed, and the like.

The exception handling identifier is used for representing records when the data block is subjected to exception handling (such as data verification failure and data writing failure), and is usually an id or a name which uniquely represents the data block when the data block is subjected to exception handling, for example, numbers representing ids such as 1, 2 and 3; may be key characters, such as a, b, c, etc., that uniquely characterize the exception handling of the data block; may be a key string that uniquely characterizes the exception handling of the data block, such as pth_a, pth_b, pth_c; etc.

Specifically, before starting data verification on the target data block, the terminal traverses the running log of the processor to determine whether at least one data block corresponding to the mirror image data is abnormally processed, such as failure in data block verification, failure in writing into the data block, and the like.

When determining that the processor running log does not have the abnormal processing identifier, the terminal executes the step of step S205;

when determining that the running log has the abnormal processing identifier, the terminal can determine that the mirror image data fails to be checked, and the current target data block is not required to be checked at the moment.

In a specific implementation scenario, when the terminal controls the first processor (or the second processor) to fail to check the data of the target data block, if the check value of the target data block is inconsistent with the check value carried by the target data block, that is, the data check fails, the terminal may generate an exception handling identifier for the mirror image data, record the current data check condition, and then store the exception handling identifier in the processor operation log. Or alternatively, the first and second heat exchangers may be,

when the terminal controls the third processor to fail to write the target data block data, if the data block data is inconsistent with the supportable data types of the local terminal, that is, the data writing fails, the terminal can generate an exception handling identifier for the mirror image data, record the current data writing condition, and then store the exception handling identifier in the processor operation log

Step S205: and when the first processor is in the check state, acquiring the working state of at least one check processor.

The specific determination that the first processor is in the check state may refer to step S102, which is not described herein.

Specifically, when the first processor is in the checking state, the terminal may acquire the working state of at least one included checking processor, and determine the second processor based on the working state of each checking processor.

Wherein the operating states include at least an idle state and a check state.

The check processor may be understood as a processor included in the terminal except the first processor and the third processor, which may be used as a check processor, or a standby processor pre-designated by the terminal for data check.

In practical application, the terminal traverses at least one check processor contained in the data processing system to determine the working state of each check processor, and in practical application, the terminal can obtain the working information of the check processor operated based on the processor, such as the type of the memory space operated by the processor: the memory space type comprises a user space, a kernel space, whether a user process is executed, whether the user process is in a process context state and whether the user process is in a terminal context state; further, when the test processor runs in the kernel space and the process corresponding to the idle state is executed normally, it can be judged that the test processor is in the idle state; when the check processor runs in the user space and is in the process context, it is executed on behalf of a certain process, for example: the application layer interacts with the kernel, requiring the kernel or the driver layer to run specific tasks, such as writing files, etc.

Step S206: and taking the check processor with the working state in the idle state as a second processor, and controlling the second processor to perform data check on the target data block.

Specifically, after the terminal obtains the working state of at least one included verification processor, the verification processor with the working state being in an idle state may be used as a second processor, and further, when the number of verification processors in the idle state is multiple, the terminal may determine the second processor based on the processing speed of the verification processor, for example, the processor with the highest processing speed and the working state being in the idle state is used as the second processor.

The step S102 may be referred to for controlling the second processor to perform data verification on the target data block, which is not described herein.

Step S207: and determining that the second processor finishes data verification of the target data block, and controlling the second processor to enter a dormant state.

Specifically, when the terminal controls the second processor to complete the data verification of the target data block, the second processor may be controlled to enter a sleep state, so as to reduce the power consumption of the terminal.

After the terminal controls the second processor to perform data verification on the target data block, the data verification result is that verification passes or fails, and at this time, the data verification on the target data block is usually completed.

Step S208: and after the verification of the target data block is passed, controlling a third processor to write data into the target data block.

See step S103, and will not be described here.

Step S209: and acquiring a next data block of the target data block, and executing step S204 by taking the next data block as the target data block.

Specifically, after determining that the target data block passes the verification and writing the data successfully into the target data block, the terminal determines the next data block of the target data block based on the "determination rule of the target data block", for example, the data block received after the corresponding time point of the target data block is used as the next data block of the target data block based on the time dimension, for example, the terminal obtains the next data block indicated by the next block sequence corresponding to the target data block if the determination is performed based on the block sequence of the data block, and the like, after determining the next data block of the target data block, the terminal takes the next data block of the target data block as the target data block, and then step S204 is performed.

Step S210: and when the next data block does not exist, determining that the mirror data check is successful.

Specifically, when the terminal determines that the target data block is the last data block corresponding to the mirror image data, the next data block does not exist at this time, and the terminal can determine that the mirror image data passes the verification.

In the embodiment of the application, a terminal acquires mirror image data transmitted by a server, acquires a target data block in at least one data block included in the mirror image data, and controls a second processor to perform data verification on the target data block when a first processor is in a verification state, and controls a third processor to perform data writing on the target data block after the target data block passes verification. The method has the advantages that the target data block corresponding to the mirror image data is obtained by adopting a block transmission mode, when the first processor for data verification is in a verification state, a data verification parallel execution mode can be adopted, the second processor is controlled to carry out verification on the target data block in parallel, and the third processor is controlled to carry out data writing on the data block after the verification, so that the problem of low data verification efficiency in the serial execution of the data verification in the related art can be avoided, the efficiency in the data verification process is improved, and the flow of the data verification is carried out in parallel through a plurality of processors (such as the first processor, the second processor and the third processor), so that the time for data verification is saved; and in the data verification process, when the data verification fails or the data writing fails, the exception handling identification can be saved to the processor running log, so that the mechanism for verifying the mirrored data block data is optimized.

The following are examples of the apparatus of the present application that may be used to perform the method embodiments of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method of the present application.

Referring to fig. 3, a schematic structural diagram of a data verification device according to an exemplary embodiment of the present application is shown. The data verification means may be implemented as all or part of the device by software, hardware or a combination of both. The apparatus 1 comprises a target data block determination module 11, a data verification module 12 and a data writing module 13.

The target data block determining module 11 is configured to obtain mirror image data transmitted by a server, and obtain a target data block in at least one data block included in the mirror image data;

a data verification module 12, configured to control the second processor to perform data verification on the target data block when the first processor is in a verification state;

and the data writing module 13 is used for controlling the third processor to write data into the target data block after the verification of the target data block is passed.

Alternatively, as shown in fig. 5, the apparatus 1 includes:

the running log checking module 14 is configured to obtain a running log of a processor, determine that the running log of the processor does not have an abnormal processing identifier, and call the data checking module 12 to control the second processor to perform data checking on the target data block when the first processor is in a checking state.

Optionally, the log verification module 14 is specifically configured to:

and when the running log has an abnormal processing identifier, determining that the mirror image data check fails.

Alternatively, as shown in fig. 5, the apparatus 1 includes:

a next data block obtaining module 15, configured to obtain a next data block of the target data block, and execute the step of controlling a second processor to perform data verification on the target data block when the first processor is in a verification state with the next data block serving as the target data block;

the data verification module 12 is further configured to determine that the mirror data verification is successful when the next data block does not exist.

Optionally, as shown in fig. 4, the data verification module 12 includes:

an operating state obtaining unit 121, configured to obtain an operating state of at least one verification processor included when the first processor is in the verification state;

a second processor determining unit 122, configured to take, as a second processor, a check processor whose working state is an idle state;

and the data verification unit 123 is configured to control the second processor to perform data verification on the target data block.

Optionally, the data verification module 12 is specifically configured to:

And determining that the second processor completes the data checking of the target data block, and controlling the second processor to enter a dormant state.

Alternatively, as shown in fig. 5, the apparatus 1 includes:

a processing speed determining module 16, configured to perform performance detection on all the included processors, and determine a processing speed corresponding to each of the processors;

the processor determining module 17 is configured to take, as a third processor, the processor with the highest processing speed, and take, as a first processor, the processors with the highest processing speed except for the third processor, among the processors.

Optionally, the device 1 is specifically configured to:

and when the data inspection of the target data block fails or the data writing fails, generating an exception handling identifier aiming at the mirror image data, and storing the exception handling identifier into the processor running log.

It should be noted that, in the data verification apparatus provided in the foregoing embodiment, only the division of the foregoing functional modules is used for illustration when the data verification method is executed, and in practical application, the foregoing functional allocation may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the data verification device and the data verification method provided in the foregoing embodiments belong to the same concept, which embody the detailed implementation process in the method embodiment, and are not described herein again.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

In this embodiment, the terminal obtains mirror image data transmitted by the server, obtains a target data block in at least one data block included in the mirror image data, and when the first processor is in a verification state, controls the second processor to perform data verification on the target data block, and after the target data block passes the verification, controls the third processor to perform data writing on the target data block. The method has the advantages that the target data block corresponding to the mirror image data is obtained by adopting a block transmission mode, when the first processor for data verification is in a verification state, a data verification parallel execution mode can be adopted, the second processor is controlled to carry out verification on the target data block in parallel, and the third processor is controlled to carry out data writing on the data block after the verification, so that the problem of low data verification efficiency in the serial execution of the data verification in the related art can be avoided, the efficiency in the data verification process is improved, and the flow of the data verification is carried out in parallel through a plurality of processors (such as the first processor, the second processor and the third processor), so that the time for data verification is saved; and in the data verification process, when the data verification fails or the data writing fails, the exception handling identification can be saved to the processor running log, so that the mechanism for verifying the mirrored data block data is optimized.

The embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are adapted to be loaded by a processor and execute the data verification method according to the embodiment shown in fig. 1-2, and the specific execution process may refer to the specific description of the embodiment shown in fig. 1-2, which is not repeated herein.

The present application further provides a computer program product, where at least one instruction is stored, where the at least one instruction is loaded by the processor and executed by the processor to perform the data verification method according to the embodiment shown in fig. 1-2, and the specific execution process may refer to the specific description of the embodiment shown in fig. 1-2, which is not repeated herein.

Referring to fig. 6, a block diagram of an electronic device according to an exemplary embodiment of the present application is shown. The electronic device of the present application may include one or more of the following components: processor 110, memory 120, input device 130, output device 140, and bus 150. The processor 110, the memory 120, the input device 130, and the output device 140 may be connected by a bus 150.

Processor 110 may include one or more processing cores. The processor 110 utilizes various interfaces and lines to connect various portions of the overall electronic device, perform various functions of the electronic device 100, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 120, and invoking data stored in the memory 120. Alternatively, the processor 110 may be implemented in at least one hardware form of digital signal processing (digital signal processing, DSP), field-programmable gate array (field-programmable gate array, FPGA), programmable logic array (programmable logic Array, PLA). The processor 110 may integrate one or a combination of several of a central processing unit (central processing unit, CPU), an image processor (graphics processing unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for being responsible for rendering and drawing of display content; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 110 and may be implemented solely by a single communication chip.

The memory 120 may include a random access memory (random Access Memory, RAM) or a read-only memory (ROM). Optionally, the memory 120 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 120 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 120 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, which may be an Android (Android) system, including an Android system-based deep development system, an IOS system developed by apple corporation, including an IOS system-based deep development system, or other systems, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The storage data area may also store data created by the electronic device in use, such as phonebooks, audiovisual data, chat log data, and the like.

Referring to FIG. 7, the memory 120 may be divided into an operating system space in which the operating system is running and a user space in which native and third party applications are running. In order to ensure that different third party application programs can achieve better operation effects, the operating system allocates corresponding system resources for the different third party application programs. However, the requirements of different application scenarios in the same third party application program on system resources are different, for example, under the local resource loading scenario, the third party application program has higher requirement on the disk reading speed; in the animation rendering scene, the third party application program has higher requirements on the GPU performance. The operating system and the third party application program are mutually independent, and the operating system often cannot timely sense the current application scene of the third party application program, so that the operating system cannot perform targeted system resource adaptation according to the specific application scene of the third party application program.

In order to enable the operating system to distinguish specific application scenes of the third-party application program, data communication between the third-party application program and the operating system needs to be communicated, so that the operating system can acquire current scene information of the third-party application program at any time, and targeted system resource adaptation is performed based on the current scene.

Taking an operating system as an Android system as an example, as shown in fig. 8, a program and data stored in the memory 120 may be stored in the memory 120 with a Linux kernel layer 320, a system runtime library layer 340, an application framework layer 360 and an application layer 380, where the Linux kernel layer 320, the system runtime library layer 340 and the application framework layer 360 belong to an operating system space, and the application layer 380 belongs to a user space. The Linux kernel layer 320 provides the underlying drivers for various hardware of the electronic device, such as display drivers, audio drivers, camera drivers, bluetooth drivers, wi-Fi drivers, power management, and the like. The system runtime layer 340 provides the main feature support for the Android system through some C/c++ libraries. For example, the SQLite library provides support for databases, the OpenGL/ES library provides support for 3D graphics, the Webkit library provides support for browser kernels, and the like. Also provided in the system runtime library layer 340 is a An Zhuoyun runtime library (Android run) which provides mainly some core libraries that can allow developers to write Android applications using the Java language. The application framework layer 360 provides various APIs that may be used in building applications, which developers can also build their own applications by using, for example, campaign management, window management, view management, notification management, content provider, package management, call management, resource management, data check management. At least one application program is running in the application layer 380, and these application programs may be native application programs of the operating system, such as a contact program, a short message program, a clock program, a camera application, etc.; and can also be a third party application program developed by a third party developer, such as a game application program, an instant messaging program, a photo beautification program, a data verification program and the like.

Taking an operating system as an IOS system as an example, the program and data stored in the memory 120 are shown in fig. 9, the IOS system includes: core operating system layer 420 (Core OS layer), core service layer 440 (Core Services layer), media layer 460 (Media layer), and touchable layer 480 (Cocoa Touch Layer). The core operating system layer 420 includes an operating system kernel, drivers, and underlying program frameworks that provide more hardware-like functionality for use by the program frameworks at the core services layer 440. The core services layer 440 provides system services and/or program frameworks required by the application, such as a Foundation (Foundation) framework, an account framework, an advertisement framework, a data storage framework, a network connection framework, a geographic location framework, a sports framework, and the like. The media layer 460 provides an interface for applications related to audiovisual aspects, such as a graphics-image related interface, an audio technology related interface, a video technology related interface, an audio video transmission technology wireless play (AirPlay) interface, and so forth. The touchable layer 480 provides various commonly used interface-related frameworks for application development, with the touchable layer 480 being responsible for user touch interactions on the electronic device. Such as a local notification service, a remote push service, an advertisement framework, a game tool framework, a message User Interface (UI) framework, a User Interface UIKit framework, a map framework, and so forth.

Among the frameworks illustrated in fig. 9, frameworks related to most applications include, but are not limited to: the infrastructure in core services layer 440 and the UIKit framework in touchable layer 480. The infrastructure provides many basic object classes and data types, providing the most basic system services for all applications, independent of the UI. While the class provided by the UIKit framework is a basic UI class library for creating touch-based user interfaces, iOS applications can provide UIs based on the UIKit framework, so it provides the infrastructure for applications to build user interfaces, draw, process and user interaction events, respond to gestures, and so on.

The manner and principle of implementing data communication between the third party application program and the operating system in the IOS system can refer to the Android system, and the application is not described herein.

The input device 130 is configured to receive input instructions or data, and the input device 130 includes, but is not limited to, a keyboard, a mouse, a camera, a microphone, or a touch device. The output device 140 is used to output instructions or data, and the output device 140 includes, but is not limited to, a display device, a speaker, and the like. In one example, the input device 130 and the output device 140 may be combined, and the input device 130 and the output device 140 are a touch display screen for receiving a touch operation thereon or thereabout by a user using a finger, a touch pen, or any other suitable object, and displaying a user interface of each application program. Touch display screens are typically provided on the front panel of an electronic device. The touch display screen may be designed as a full screen, a curved screen, or a contoured screen. The touch display screen may also be designed as a combination of a full screen and a curved screen, and the combination of a special-shaped screen and a curved screen, which is not limited in the embodiment of the present application.

In addition, those skilled in the art will appreciate that the configuration of the electronic device shown in the above-described figures does not constitute a limitation of the electronic device, and the electronic device may include more or less components than illustrated, or may combine certain components, or may have a different arrangement of components. For example, the electronic device further includes components such as a radio frequency circuit, an input unit, a sensor, an audio circuit, a wireless fidelity (wireless fidelity, wiFi) module, a power supply, and a bluetooth module, which are not described herein.

In the embodiment of the present application, the execution subject of each step may be the electronic device described above. Optionally, the execution subject of each step is an operating system of the electronic device. The operating system may be an android system, an IOS system, or other operating systems, which is not limited by the embodiments of the present application.

The electronic device of the embodiment of the application can be further provided with a display device, and the display device can be various devices capable of realizing display functions, such as: cathode ray tube displays (cathode ray tubedisplay, CR), light-emitting diode displays (light-emitting diode display, LED), electronic ink screens, liquid crystal displays (liquid crystal display, LCD), plasma display panels (plasma display panel, PDP), and the like. A user may utilize a display device on electronic device 101 to view displayed text, images, video, etc. The electronic device may be a smart phone, a tablet computer, a gaming device, an AR (Augmented Reality ) device, an automobile, a data storage device, an audio playing device, a video playing device, a notebook, a desktop computing device, a wearable device such as an electronic watch, electronic glasses, an electronic helmet, an electronic bracelet, an electronic necklace, an electronic article of clothing, etc.

In the electronic device shown in fig. 6, where the electronic device may be a terminal, the processor 110 may be configured to invoke the data verification application stored in the memory 120 and specifically perform the following operations:

In one embodiment, after executing the target data block of the at least one data block included in the acquiring the mirror data, the processor 110 further executes the following operations:

acquiring a processor running log;

and when the processor running log does not have the abnormal processing identifier, executing the step of controlling the second processor to perform data verification on the target data block when the first processor is in the verification state.

In one embodiment, after executing the obtaining the processor log, the processor 110 further performs the following operations:

Acquiring a next data block of the target data block, and taking the next data block as the target data block to execute the step of controlling a second processor to perform data verification on the target data block when the first processor is in a verification state;

and when the next data block does not exist, determining that the mirror data check is successful.

In one embodiment, the processor 110, when executing the data verification on the target data block by controlling the second processor when the first processor is in the verification state, specifically executes the following operations:

when the first processor is in a verification state, acquiring the working state of at least one verification processor;

and taking the check processor with the working state in the idle state as a second processor, and controlling the second processor to perform data check on the target data block.

In one embodiment, the processor 110, when executing the data verification method, further performs the following operations:

Detecting the performance of all the contained processors, and determining the corresponding processing speed of each processor;

among the processors, the processor with the highest processing speed is taken as a third processor, and the processors except the third processor are taken as first processors.

It will be clear to a person skilled in the art that the solution according to the application can be implemented by means of software and/or hardware. "Unit" and "module" in this specification refer to software and/or hardware capable of performing a specific function, either alone or in combination with other components, such as Field programmable gate arrays (Field-ProgrammaBLE Gate Array, FPGAs), integrated circuits (Integrated Circuit, ICs), etc.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, such as the division of the units, merely a logical function division, and there may be additional manners of dividing the actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on this understanding, the technical solution of the present application may be embodied essentially or partly in the form of a software product, or all or part of the technical solution, which is stored in a memory, and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be performed by hardware associated with a program that is stored in a computer readable memory, which may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic or optical disk, and the like.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure. That is, equivalent changes and modifications are contemplated by the teachings of this disclosure, which fall within the scope of the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a scope and spirit of the disclosure being indicated by the claims.

Claims

1. A method of data verification, the method comprising:

after the target data block passes the verification, controlling a third processor to write data into the target data block;

when the current resource surplus of the first processor is larger than or equal to the required amount for verifying the target data block, determining that the first processor is in a non-verification state; and when the current resource surplus of the first processor is smaller than the required amount for checking the target data block, determining that the first processor is in a checking state.

2. The method of claim 1, wherein after the obtaining the target data block of the at least one data block included in the mirror data, further comprising:

acquiring a processor running log;

and determining that the processor running log does not have an abnormal processing identifier, and executing the step of controlling the second processor to perform data verification on the target data block when the first processor is in a verification state.

3. The method of claim 2, wherein after the obtaining the processor running log, further comprising:

4. The method of claim 1, wherein said controlling the third processor after writing data to the target data block further comprises:

5. The method of claim 1, wherein controlling the second processor to perform data verification on the target data block when the first processor is in the verification state comprises:

6. The method of claim 5, wherein the method further comprises:

and determining that the second processor finishes data verification of the target data block, and controlling the second processor to enter a dormant state.

7. The method of claim 1, further comprising, before the step of obtaining the mirrored data transmitted by the server:

8. The method according to claim 2, wherein the method further comprises:

and when the data verification of the target data block fails or the data writing fails, generating an exception handling identifier aiming at the mirror image data, and storing the exception handling identifier into the processor running log.

9. A computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the method steps of any one of claims 1 to 8.

10. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1-8.