CN115686877A

CN115686877A - Data interaction method and device, storage medium and computing equipment

Info

Publication number: CN115686877A
Application number: CN202110852698.XA
Authority: CN
Inventors: 李小龙; 李志高
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2023-02-03

Abstract

The embodiment of the application relates to the technical field of computers, in particular to a data interaction method, a data interaction device, a storage medium and computing equipment, wherein the method comprises the following steps: when the BMC system is in a power-on state and a processor in the computing device is not started, acquiring hardware state information, and writing the hardware state information into a shared memory space of the computing device, so that when the BIOS system is in a power-on self-test of the processor, the hardware state information stored in the shared memory space is acquired, and after the hardware state information is detected, configuration information is written into the shared memory space; and the BMC system reads the configuration information when the processor starts an operating system, wherein the configuration information is used for configuring the operating system. By adopting the method, the BMC system and the BIOS system perform data reading and writing at different stages in the starting process of the computing device, so that the data exchange efficiency of the BMC and the BIOS system can be effectively improved, and the starting time of the computing device is reduced.

Description

Data interaction method and device, storage medium and computing equipment

Technical Field

The present application relates to the field of block chain technologies, and in particular, to a data interaction method, apparatus, storage medium, and computing device.

Background

With the application and development of big data and cloud computing technologies, people have higher and higher requirements on computing devices (such as servers, computers, and the like), and therefore people pay more and more attention to the operating state of the computing devices.

In the computing device, a BMC (Board Management Controller) may be set to monitor a hardware state of the server, and manage the server. The BMC monitors and manages the hardware state of the server through interaction with a Basic Input Output System (BIOS) on a mainboard of the server. The BIOS is a small system solidified in a BIOS chip on a computing device (such as a personal computer and a server), and can implement detection and control of the computing device on the bottommost hardware.

At present, when data interaction is performed between the BMC and the BIOS, information interaction between the BMC and the BIOS is usually realized based on a single or mixed hardware channel such as an eSPI (LPC)/SMBUS/USB, but an existing information interaction method has low interaction efficiency, and thus, a long time is spent in a starting process of a computing device.

Disclosure of Invention

In view of this, embodiments of the present application provide a data interaction method, an apparatus, a storage medium, and a computing device, which can effectively alleviate the problem in the prior art that the interaction efficiency between the BMC and the BIOS is low, and further effectively reduce the duration of the computing device in the starting process.

In a first aspect, an embodiment of the present application provides a data interaction method, which is applied to a BMC system of a computing device, where the computing device further includes a BIOS system, and the method includes: when the BMC system is in a power-on state and a processor in the computing device is not started, acquiring hardware state information, and writing the hardware state information into a shared memory space of the computing device, so that when the BIOS system is in a power-on self-test on the processor, the hardware state information stored in the shared memory space is acquired, and after the hardware state information is detected, configuration information is written into the shared memory space; and the BMC system reads the configuration information when the processor starts an operating system, wherein the configuration information is used for configuring the operating system.

In a second aspect, an embodiment of the present application provides a data interaction method, which is applied to a BIOS system of a computing device, where the computing device further includes a BMC system, and the method includes: when a processor in computing equipment is subjected to power-on self-test, the BIOS system acquires hardware state information stored in a shared memory space, and the hardware state information is written into the shared memory space when the BMC system is in a power-on state and the processor in the computing equipment is not started; after the BIOS system completes the detection of the hardware state information, writing configuration information into the shared memory space, so that the BMC system reads the configuration information when the processor starts an operating system.

In a third aspect, the embodiment of the present application returns to a data interaction device, which is applied to a BMC system of a computing device, where the computing device further includes a BIOS system, and the device includes a first obtaining module and an information reading module. The first obtaining module is configured to obtain hardware state information when the BMC system is in a power-on state and a processor in the computing device is not started, and write the hardware state information into a shared memory space of the computing device, so that the BIOS system obtains the hardware state information stored in the shared memory space when the processor is subjected to power-on self-test, and writes configuration information into the shared memory space after the hardware state information is detected; and the information reading module is used for reading the configuration information when the processor starts an operating system, and the configuration information is used for configuring the operating system.

In an optional implementation manner, the data interaction device further includes a first setting module, where the first setting module is configured to set a BMC system flag bit in a register to a first specified value, where the first specified value represents that the BMC system has completed writing of hardware state information, so that the BIOS system obtains the hardware state information stored in the shared memory space when the BMC system flag bit in the register is set to the first specified value and the processor is powered on and performs self-test.

In an optional implementation manner, the information reading module is further configured to read the configuration information when detecting that a flag bit of the BIOS system in the register is a second specified value and when the computing device starts the operating system, the second specified value being used to indicate that the BIOS system has completed writing the configuration information.

In an optional implementation manner, the data interaction device further includes a channel closing module, where the channel closing module is configured to close a data transmission channel between the BIOS system and the shared memory space.

In an optional implementation manner, the information reading module is further configured to access the shared memory space in a file mapping reading manner when the processor starts an operating system, so as to read the configuration information.

In an optional implementation manner, the shared memory space includes a first memory space and a second memory space, the first memory space is used to store the hardware state information, the second memory space is used to store the configuration information, and the first obtaining module is further used to write the hardware state information into the first memory space.

In an optional implementation manner, the first obtaining module is further configured to write the hardware state information into a shared memory space of the computing device through a memory channel.

In an alternative embodiment, the hardware status information includes motherboard FRU information and the configuration information includes asset information.

In a fourth aspect, an embodiment of the present application provides a data interaction device, which is applied to a BIOS system of a computing device, where the computing device further includes a BMC system, and the device includes a second obtaining module and an information writing module. A second obtaining module, configured to obtain hardware state information stored in a shared memory space when a processor in a computing device is powered on for self-test, where the hardware state information is written into the shared memory space by the BMC system when the BMC system is in a powered on state and the processor in the computing device is not started; and the information writing module is used for writing configuration information into the shared memory space after the hardware state information is detected, so that the BMC system reads the configuration information when the processor starts an operating system.

In an optional implementation manner, the data interaction apparatus further includes a second setting module, where the second setting module is configured to set a BIOS system flag bit in a register to a second specified value, and the second specified value is used to indicate that the BIOS system has completed writing the configuration information, so that the BMC system reads the configuration information when detecting that the BIOS system flag bit in the register is the second specified value and when the computing device starts the operating system.

In an optional implementation manner, the second obtaining module is further configured to, when the processor is subjected to power-on self-test, access a shared memory space in a multiple-input multiple-output manner, so as to obtain hardware state information stored in the shared memory space.

In an optional implementation, the data interaction apparatus further includes: and the verification module is used for verifying the hardware state information by using cyclic redundancy check, and if the verification is successful, the detection of the hardware state information is completed.

In an optional implementation manner, the second obtaining module is further configured to obtain, through the PCIE channel, hardware state information stored in the shared memory space when the processor is subjected to power on self test; and the information writing module is further used for writing configuration information into the shared memory space through the PCIE channel.

In an optional implementation manner, the shared memory space includes a first memory space and a second memory space, where the first memory space is used to store the hardware state information, and the second memory space is used to store the configuration information. And the information writing module is also used for writing configuration information into the second memory space.

In a fifth aspect, an embodiment of the present application provides a computing device, which includes a BIOS system, a BMC system, a processor, and a shared memory space. The BMC system is used for acquiring hardware state information when the power is on and a processor in the computing device is not started, and writing the hardware state information into a shared memory space of the computing device; the BIOS system is used for acquiring hardware state information stored in the shared memory space when the processor is subjected to power-on self-test, and writing configuration information into the shared memory space after the hardware state information is detected; the BMC system is configured to read the configuration information when the processor starts an operating system, where the configuration information is used to configure the operating system.

In a sixth aspect, embodiments of the present application provide a computer program product or a computer program comprising computer instructions stored in a computer-readable storage medium. The processor of the computer device obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the method described above.

In the method, when a BMC system is in a power-on state and a processor in the computing device is not started, hardware state information is acquired and written into a shared memory space of the computing device, so that when a BIOS system performs power-on self-test on the processor, the hardware state information stored in the shared memory space is acquired, and configuration information is written into the shared memory space after the hardware state information is detected; when the operating system is started by the processor, the BMC system reads the configuration information, and the configuration information is used for configuring the operating system. By adopting the method, the BMC system and the BIOS system perform data reading and writing at different stages in the starting process of the computing device, so that the purpose of asynchronous interaction between the BMC system and the BIOS system is achieved, mutual blocking and dependence between the BMC system and the BIOS system are avoided in the interaction process, the data exchange efficiency of the BMC and the BIOS system can be effectively improved, the starting time of the computing device is shortened, and the fault recovery of the computing device is faster.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a computing device according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating data interaction of a computing device at different boot stages according to an embodiment of the present application;

fig. 3 is a schematic flowchart illustrating a data interaction method provided in an embodiment of the present application;

fig. 4 is a schematic diagram illustrating a partition of a shared memory space according to an embodiment of the present application;

FIG. 5 is a schematic flow chart illustrating a data interaction method according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating another embodiment of a computing device;

FIG. 7 is a schematic flow chart illustrating a data interaction method according to an embodiment of the present application;

FIG. 8 is a schematic flow chart illustrating a data interaction method according to an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating another data interaction of a computing device at different boot-up stages according to an embodiment of the present application;

FIG. 10 is a block diagram illustrating a data interaction apparatus according to an embodiment of the present disclosure;

fig. 11 shows another structural block diagram of a data interaction apparatus provided in an embodiment of the present application;

fig. 12 shows a further structural schematic diagram of a computing device provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Hereinafter, terms related to the present application are explained.

The computing device may be a device such as a server or a computer having a BIOS system and a BMC system, where the BMC system and the BIOS system may run on different processors of the computing device, for example, the BIOS system may run in a processor in a motherboard of the computing device, and the BMC system may run on a baseboard management controller.

The BIOS System (Basic Input Output System), i.e., the Basic Input Output System, is a non-tampered boot program engraved On a ROM chip of a motherboard, and the BIOS is responsible for a computing System Self-Test (POST) and a System Self-boot program, so that the BIOS is a first program after the computer System is started and can be run by a processor (e.g., a central processing unit) in the computing device. Due to the tamper-proof nature, the program is stored in the ROM chip of the computing device and after power down the original settings can still be maintained.

The POST refers to power-on self-test, which refers to that when a computing device is powered on, the states of a CPU (central processing unit), a memory, various processors and peripherals need to be checked, the normality of the devices is ensured, and a stable environment is provided for the running of a bootloader and a kernel (real-time operating system). In a specific power-on self-test process, the following test processes may be performed: (1) checking a CPU register; (2) checking the integrity of the BIOS code; (3) A DMA (Direct Memory Access) processor, a timer, a terminal processor, etc. are checked, wherein DMA is a data exchange mode in which data is directly accessed from a Memory without passing through a CPU. (4) checking a system memory; (5) checking the system bus and the external device; (6) initializing the BIOS; (7) Jump to next level BIOS (e.g., VGA-BIOS) execution and return, VGA (Video graphics Array). Wherein, the VGA supports 16 colors or 256 gray scales to be simultaneously displayed at the higher resolution of 640X 480, and simultaneously can display 256 colors at the resolution of 320X 240; (8) Identify devices that can be powered up (e.g., read-only optical disks, universal serial bus, hard disk drive, etc.).

The BMC system is a small operating system independent of the server system, and can be run by a baseboard management controller, which can be inserted into a motherboard in a PCIE (PCI Express bus) form or the like, and the external representation form is only a standard RJ45 network port, and has an independent IP firmware system. The BMC is mainly used for collecting various information on a single computing device (such as a server) and providing the information to upper-layer operation and maintenance network management software. The first BMC can provide various interfaces for upper layer network management inquiry, such as human-machine interfaces of web, command lines and the like, machine-machine interfaces of SNMP, IPMI, restful and the like; and the second is active reporting, when a fault is detected, the BMC can report the fault to a server of upper-layer network management software through means of SNMP trap message, SMTP mail message, redfish http json message and the like, so that operation and maintenance personnel can identify and process the fault in time. In general, the message reported by the BMC software will explicitly indicate which component has failed, what the processing proposal is, and so on.

The shared memory space refers to a memory space that can be accessed by the BMC system and the BIOS system at the same time, and the memory space may be a VGA shared memory space (VGA: video Graphics Array Video image Array shared memory space), may also be a memory on the monitor board, and may also be a memory set on the motherboard. The monitoring board is used for monitoring and managing the computing equipment, and the main board is a core device of the computing equipment and is provided with main circuit systems of the computing equipment, such as a processor, a memory, a bus and other structures.

The processor, referred to as a Central Processing Unit (CPU) in the computing device in this application, is a final execution unit for information processing and program operation as an operation and control core of the computer system. The operations of all software layers in the computer system, as well as the startup and running of the operating system, will eventually be mapped to the operations of the CPU through the instruction set.

An Operating System (OS) is a computer program that manages computer hardware and software resources. The operating system needs to handle basic transactions such as managing and configuring memory, prioritizing system resources, controlling input devices and output devices, operating the network, and managing the file system. The operating system also provides an operator interface for the user to interact with the system. The operating system may include embedded systems (e.g., vxWorks operating system, eCos operating system, symbian OS operating system, palm OS operating system, etc.), unix-like operating systems, microsoft Windows operating system, macOS X operating system, and Google Chrome OS operating system, among others.

With the development of computer technologies, such as the development of cloud computing technologies, medical cloud, cloud internet of things, cloud security, cloud social interaction, cloud conference, artificial intelligence cloud services, and the like are increasingly applied, and the reliability and serviceability of computing devices for performing cloud computing are also increasingly concerned by users.

The inventor finds that, at present, computing devices (such as servers and terminals and the like) are more and more competitive with cloud markets, and cloud customers have higher requirements on SLA (service level agreement, which is an agreement or contract that is agreed by both parties with respect to quality, level, performance and the like of services between enterprises providing services and customers) of cloud services, so that the requirements on serviceability and reliability of computing device hardware are higher. And the computing equipment is started more quickly, the starting time is shorter, the fault recovery time can be greatly reduced, and the cloud service is supported to better meet the SLA requirements of cloud customers. However, most of the existing computing devices implement information interaction between the BMC and the BIOS based on a single or mixed hardware channel such as an eSPI (LPC)/SMBUS/USB, and mainly perform information interaction during a system POST process (during a power-on self-test process), so that when information interaction is performed, the interaction efficiency is low, and once an abnormality occurs in the BMC system or the BIOS system, the function of the other party may be affected, and even the system cannot be started.

Based on this, the inventor provides a data interaction method, which is applied to a computing device comprising a BMC system and a BIOS system, and the data interaction method comprises: when the BMC system is in a power-on state and a processor in the computing device is not started, acquiring hardware state information and writing the hardware state information into a shared memory space of the computing device; when the BIOS system is electrified and self-checked on a processor, acquiring hardware state information stored in a shared memory space, and after the hardware state information is detected, writing configuration information into the shared memory space; when the operating system is started by the processor, the BMC system reads the configuration information, and the configuration information is used for configuring the operating system. The shared memory space is used in the process that the computing equipment executes the startup and the startup after being powered on (from the processor not being started to the power-on self-test stage of the processor and to the process that the processor starts the operating system), so that the data needing to be interacted in the startup process of the BMC system and the BIOS system is accessed in time sharing by utilizing the shared memory space, and the purpose of mutual exclusion access in stages is achieved, so that the BMC system and the BIOS system are independent and independent from each other in the startup process of the computing equipment, the system startup time is shortened, and the system reliability is improved.

A schematic structural diagram of a computing device 100 according to an embodiment of the present invention is described below with reference to fig. 1.

Fig. 1 is a schematic structural diagram of a computing device 100, where the computing device 100 may be a server or a terminal.

The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server providing basic cloud computing services such as cloud service, a cloud database, cloud computing, cloud functions, cloud storage, network service, cloud communication, middleware service, domain name service, security service, CDN, and a big data and artificial intelligence platform.

The terminal can be any device with a BMS system and a BIOS system, such as a smart phone, a tablet computer and a desktop computer.

The computing device 100 includes a BMC system 110, a BIOS system 120, a shared memory space 130, and a processor 140, and the BMC system 110, the BIOS system 120, the shared memory space 130, and the processor 140 are directly or indirectly connected to each other for data interaction.

The computing device 100 may go through three phases during the booting process, which are a power-off phase (when the BMC system 110 is powered on but the processor 140 is not powered on, i.e., is not booted), a post phase (when the processor 140 is powered on and self-test), and an OS phase (when the processor 140 boots the operating system).

Specifically, before the computing device 100 performs the data interaction, the computing device 100 is first powered on to power up the BMC system 110, where the processor 140 in the computing device 100 is not started, and when a user performs a boot operation on the computing device 100, the BMC system 110 detects that it is in a powered-on state and the processor 140 in the computing device 100 is in an un-started state. When the BMC system 110 is in a power-on state and the processor 140 in the computing device 100 is not started, acquiring hardware state information and writing the hardware state information into the shared memory space 130 of the computing device 100; when the BIOS system 120 performs power-on self-test on the processor 140, acquiring hardware state information stored in the shared memory space 130, and after completing detection of the hardware state information, writing configuration information into the shared memory space 130; the BMC system 110 reads configuration information for configuring the operating system when the processor 140 starts the operating system.

By adopting the above arrangement, in the starting process of the computing device 100, the BMC system 110 and the BIOS system 120 perform data reading and writing at different stages, that is, the BMC system 110 performs data reading and writing at the power off stage and the OS stage, and the BIOS system 120 performs data reading and writing at the post stage, so that the purpose of asynchronous interaction between the BMC system 110 and the BIOS system 120 is achieved, and therefore, mutual blocking and dependence between the BMC system 110 and the BIOS system 120 are avoided in the interaction process, information can be interacted without waiting until the BMC system 110 and the BIOS system 120 are both in the starting state, and compared with current synchronous real-time interaction, decoupling is more flexible, so that the efficiency of data exchange between the BMC and the BIOS can be effectively improved, the starting time of the computing device 100 is reduced, and further, the fault recovery of the computing device 100 is faster.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 2 and fig. 3 in combination, fig. 2 is a timing diagram illustrating a data interaction between the BMC system 110 and the BIOS system 120, and fig. 3 is a flowchart illustrating a data interaction method applicable to the BMC system 110 in the computing device shown in fig. 1 according to an embodiment of the present disclosure, where the method includes:

step S110: when the BMC system 110 is in the power-on state and the processor 140 in the computing device is not started, the hardware state information is obtained and written into the shared memory space 130 of the computing device, so that when the BIOS system 120 is powered on for self-test on the processor 140, the hardware state information stored in the shared memory space 130 is obtained, and after the detection of the hardware state information is completed, the configuration information is written into the shared memory space 130.

The processor 140 in the computing device 100 refers to a Central Processing Unit (CPU) 140 of the computing device 100, which is a final execution unit for information processing and program operation, and serves as an operation and control core of a computer system.

The BMC system 110 is powered up and the processor 140 in the computing device 100 is not started meaning that: after the computing device 100 is powered on and the BMC system 110 is in a boot state, but the computing device 100 has not yet performed a boot operation and the processor 140 has not yet been woken up.

The hardware state information refers to device information of devices disposed on a motherboard of the computing device 100, where the devices disposed on the motherboard of the computing device 100 include the processor 140, the memory, the bus, and the like. Other devices can be disposed on the main board, and the devices can be one or more of a temperature sensor, a memory, a fan, an indicator light and the like. Correspondingly, the hardware status information may include motherboard FRU information (information of the field replaceable unit), BIOS menu item information to be validated, and motherboard configuration item information such as device information of devices deployed on the motherboard, where the device information of the devices deployed on the motherboard may include the model and dominant frequency of the processor 140, the capacity of the memory, the rotation speed of the fan, and the flashing condition of the indicator light.

The configuration information may be one or more of asset information of the computing device 100, an SMBIOS, a current BIOS menu item, etc. that is a unified specification that a motherboard or System manufacturer needs to follow to display product Management information in a standard format to configure the operating System of the computing device 100.

The shared memory space 130 of the computing device 100 may be a VGA shared memory space 130 (VGA: video Graphics Array Video image Array), a memory on a monitor board, or a memory provided on a motherboard.

In an alternative embodiment of the present application, the shared memory space 130 of the computing device 100 is a Video Graphics Array (VGA) shared memory space 130.

It should be understood that the shared memory space 130 may store both data that the BMC system 110 needs to send to the BIOS system 120 and data that the BIOS system 120 needs to send to the BMC system 110, and accordingly, the shared memory space 130 may store the data that the BMC needs to store and the data that the BIOS needs to store in a partitioned manner (for example, the shared memory space 130 may be divided into fixed regions according to information classification, and each region stores data according to a defined format), or may store the data in the same region at different times.

The memory size of the shared memory space 130 may be 1MB, 2MB, or 5MB, and is not limited specifically here, and may be set according to actual requirements.

The hardware state information written by the BMC system 110 to the shared memory space 130 and the configuration information written by the BIOS to the shared memory space 130 may be stored in the same storage area of the shared memory space 130, or may be stored in different storage areas of the shared memory space 130.

In an alternative embodiment, the shared memory space 130 includes a first memory space and a second memory space, the first memory space is used for storing the hardware status information, the second memory space is used for storing the configuration information, and the BMC system 110 writes the hardware status information into the shared memory space 130 of the computing device 100, including: the BMC system 110 writes the hardware state information to the first memory space.

The access space sizes corresponding to the first memory space and the second memory space may be different, and the base addresses of the first memory space and the second memory space in the shared memory space 130 are different.

It should be understood that the shared memory space 130 may include other memory spaces besides the first memory space for storing hardware status information and the second memory space for storing configuration information, such as a memory space for storing BIOS version numbers, output log levels, password modification flags, BIOS configuration reset flags, BIOS default configuration load flags, BIOS set restore flags, BIOS set modification flags, password restore flags, function retention information, administrator passwords, user passwords, and the like.

As shown in fig. 4, the shared memory space 130 is divided into a plurality of fixed areas for storing data, taking 1MB as an example and the base address of the shared memory space 130 is 0X00000 as an example.

Wherein, the base address is 0X00000, and the storage content occupying the storage space of 4 bytes (bytes) is characters (such as "' B ' I" O "S '"4 characters), which can be written when the BMC system 110 is started; the base address is 0X00004, the stored content occupying the storage space of 2 bytes is a version number, the version number is divided into two parts, one byte is a main version number, the other byte is a minor version number, and the version number can be written by the BIOS; the base address is 0X00006, and the storage space occupying (2K-6) bytes is used for storing data and flag information (such as a BMC system flag bit or a BIOS system flag bit can be stored); the base address is 0X00800, a storage space of 1K bytes is occupied for information (motherboard FRU) of the field replaceable unit in the hardware status information, wherein the first two 2 bytes in the 1K bytes are used for storing reserved words, the next two bytes are used for storing the size of a file, the next 4 bytes are used for storing a cyclic check code of the file, the remaining bytes are used for storing file contents corresponding to the information of the field replaceable unit, the data is written by the BMC system 110 when the storage space is in a power-on state and the processor 140 in the computing device 100 is not started, and the data is read by the BIOS system 120 in a post stage; the base address is 0X00C00, the storage space occupying 200K bytes is used for storing asset information in the configuration information, wherein the first two 2 bytes in 200K are used for storing reserved words, the next two bytes are used for storing file sizes, the next 4 bytes are used for storing cyclic check codes of files, and the remaining bytes are used for storing file contents corresponding to the latest setting information, and the configuration information can be written by the BIOS system 120 in the POST stage and read by the BMC system 110 in the OS stage; the base address is 0X32C00, the storage space occupying 250K bytes is used for storing BIOS menu items to be validated in the configuration information, wherein the first two 2 bytes in 250K are used for storing reserved words, the next two bytes are used for storing the size of a file, the next 4 bytes are used for storing cyclic check codes of the file, and the remaining bytes are used for storing file contents corresponding to the BIOS menu items to be validated, wherein the BIOS menu items to be validated are written by the BIOS in the POST stage and read by the BMC system 110 in the OS stage; the base address is 0X71000, the storage space occupying 250K bytes is used for storing the current BIOS menu item in the configuration information, wherein the first two 2 bytes in 250K are used for storing the reserved word, the next two bytes are used for storing the file size, the next 4 bytes are used for storing the cyclic check code of the file, the remaining bytes are used for storing the file content corresponding to the current BIOS menu item, and the current BIOS menu item is only written by the BIOS at the POST stage and read by the BMC system 110 at the OS stage; the base address is 0XAFC00, the storage space occupying 1K bytes is used for storing the setting result, wherein the first two 2 bytes in 1K are used for storing reserved words, the next two bytes are used for storing the size of the file, the next 4 bytes are used for storing the cyclic check code of the file, and the rest bytes are used for storing the file content corresponding to the setting result; the base address is 0XB0000, and the storage space occupying 320K bytes is used for storing the reserved information.

When the BMC system 110 accesses the shared memory space 130, the BMC system 110 may be connected to the shared memory space 130 through an AHB Bus (advanced High Performance Bus) to access the shared memory space 130; may also be connected to the shared memory space 130 via an ASB Bus (Advanced System Bus) to access the shared memory space 130; the BMC system 110 may also be connected to the shared memory space 130 through an Advanced Microcontroller Bus Architecture (AMBA) to access the shared memory space 130, and it should be understood that when accessing the shared memory space 130, the BMC system 110 may also be connected to the shared memory space 130 through another Bus to perform access, which is not described herein.

Since the bus essentially refers to the memory channel between the BMC system 110 and the shared memory space 130. Thus, the BMC system 110 writes hardware state information to the shared memory space 130 of the computing device 100, including: the BMC system 110 writes the hardware state information to the shared memory space 130 of the computing device 100 through the memory channel.

When writing the hardware state information into the shared memory space 130 of the computing device 100, the BMC system 110 may write in a file mapping (mmap) manner, may write in a shared storage (shm) manner, or may write in a direct read/write (IO) manner.

In an alternative embodiment, the BMC system 110 accesses the shared memory space 130 by a file mapping read method to read the configuration information when the processor 140 starts the operating system.

The file mapping is a memory management method, provides a uniform memory management characteristic, and enables an application program to access files on a disk through a memory pointer in the same process as accessing a memory loaded with files. By the ability of file mapping to make all or part of the contents of the disk file establish mapping association with a certain region of the process virtual address space, the mapped file can be directly accessed without executing file I/O operation and buffering the file contents.

Step S120: the BMC system 110 reads configuration information for configuring the operating system when the processor 140 starts the operating system.

The configuration information can be read by the BMC system 110 in a Single Input Single Output (SISO) reading manner, or in a Single Input Multiple Output (SIMO) reading manner; or reading the configuration information by adopting a Multiple Input Single Output (MISO) reading mode; the configuration information may also be read by a Multiple Input Multiple Output (MIMO) reading method.

In an alternative embodiment, the BMC system 110 accesses the shared memory space 130 by a mimo read method to read the configuration information when the processor 140 starts the operating system.

The BMC system 110 may then save the configuration information in a memory associated with the BMC system 110 by reading the configuration information. Thus, even if the BIOS system 120 is updated or the BIOS system 120 is restarted, the configuration information about the BIOS system 120 is retained, so that the configuration information can be used when the computing device 100 fails or needs to be restarted, thereby improving the security and the startup efficiency of the computing device 100.

It should be appreciated that after the configuration information is obtained by the BMC system 110, the BMC system 110 may also perform a cyclic redundancy check on the configuration information to detect whether the configuration information is correct. When the cyclic redundancy detection is performed on the configuration information, the configuration information is correct if the preset cyclic redundancy code is compared with the cyclic redundancy code obtained by performing the cyclic redundancy detection on the configuration information, and the comparison result is that the comparison is consistent.

By adopting the data interaction method of the embodiment of the present application, when the BMC system 110 is in a power-on state and the processor 140 in the computing device 100 is not started, the hardware state information is acquired, and the hardware state information is written into the shared memory space 130 of the computing device 100; when the BIOS system 120 performs power-on self-test on the processor 140, acquiring hardware state information stored in the shared memory space 130, and after completing detection of the hardware state information, writing configuration information into the shared memory space 130; the BMC system 110 reads the configuration information when the processor 140 starts the operating system. The data needing to be interacted between the BMC system 110 and the BIOS system 120 can be accessed in a time sharing mode by using the shared memory space 130 in the starting process of the computing device 100 (from the processor 140 not being started to the power-on self-test stage of the processor 140 and to the process of starting the operating system of the processor 140), so that the BMC system 110 and the BIOS system 120 are independent and independent of each other in the starting process of the computing device 100, the starting time of the system is shortened, and the reliability of the system is improved.

Referring to fig. 5 in combination, fig. 5 shows a data interaction method provided by an embodiment of the present application, which can be applied to the computing device 100 shown in fig. 1. The method comprises the following steps:

step S210: when the BMC system 110 is in a power-up state and the processor 140 in the computing device 100 is not started, hardware state information is obtained and written to the shared memory space 130 of the computing device 100.

Step S220: the BMC system 110 sets the BMC system flag bit in the register 150 to a first specified value, so that the BIOS system 120 obtains the hardware state information stored in the shared memory space 130 when obtaining that the BMC system flag bit in the register 150 is set to the first specified value and the processor 140 is powered on for self-test, and writes configuration information into the shared memory space 130 after completing the detection of the hardware state information.

The first designated value indicates that the BMC system 110 has completed writing the hardware status information, and the register 150 functions to store a binary code, which is formed by combining flip-flops having a storage function. Since one flip-flop can store 1-bit binary code, the register 150 for storing n-bit binary code needs to be formed by n flip-flops. In this embodiment, the BMC system flag is set in the register 150.

The first specified value stored in the BMC system flag may be 0 or 1. That is, when the BMC system 110 sets the BMC system flag bit in the register 150 to 1, it indicates that the BMC system 110 has completed writing the hardware status information. That is, the shared memory space 130 stores the hardware status information written by the BMC system 110.

The register 150 may be connected to the BIOS system 120 and the BMC system 110 via a Serial Peripheral Interface (SPI), or via I ² The C interface is connected to the BIOS system 120 and the BMC system 110, respectively, andthe BIOS system 120 and the BMC system 110 may be connected via serial ports.

Referring to FIG. 6, in one possible embodiment, the register 150 may be connected to the BIOS system 120 and the BMC system 110 via a Serial Peripheral Interface (SPI).

When the BMC system flag in the register 150 is set to the first specified value and the processor 140 is powered on for self-test, the BIOS system 120 obtains the hardware status information stored in the shared memory space 130.

Step S230: the BMC system 110 reads the configuration information when detecting that the BIOS flag bit in the register 150 is set to the second specified value, and when the computing device starts the operating system, the second specified value indicates that the BIOS system 120 has completed writing the configuration information.

The second designated value is identification information for indicating that the BIOS system 120 has completed writing the configuration information, and the BIOS system flag bit in the register 150 is set after the BIOS system 120 has completed writing the configuration information.

By adopting the above setting of the present application, the BMC system flag bit and the BIOS system flag bit are set in the register 150, when the BMC system 110 is in the power-on state and the processor 140 in the computing device 100 is not started, the hardware state information is acquired, the hardware state information is written into the shared memory space 130 of the computing device 100, and the BMC system flag bit in the register 150 is set to the first specified value; when the BIOS system 120 performs power-on self-test on the processor 140 and detects that the BMC system flag bit in the register 150 is set to a first specified value, acquiring hardware state information stored in the shared memory space 130, after the hardware state information is detected, writing configuration information into the shared memory space 130, and setting the BIOS system flag bit in the register 150 to a second specified value; the BMC system 110 reads the configuration information when the processor 140 starts the operating system and detects that the BIOS flag bit in the register 150 is set to the second specified value. When the computing device 100 uses the shared memory space 130 to access the data to be interacted between the BMC system 110 and the BIOS system 120 in a time-sharing manner during the starting process, whether the data to be interacted is stored in the shared memory space 130 or not needs to be confirmed according to the value of the system flag bit (the BIOS system flag bit and the BMC system flag bit), and data interaction can be performed after the data to be interacted is confirmed to be stored, so that the accuracy of data interaction is improved, and meanwhile, the BMC system 110 and the BIOS system 120 are independent and independent from each other during the starting process of the computing device 100, so that the system starting time is shortened, and the system reliability is improved.

To further ensure that the BMC system 110 and the BIOS system 120 do not depend on each other during data interaction, after the BMC system 110 detects that the BIOS system flag in the register 150 is the second specified value, the method further includes:

the BMC system 110 closes the data transmission channel between the BIOS system 120 and the shared memory space 130.

In this case, the BIOS system 120 can be connected to an AHB bus on the BMC module through a PCH (Platform Controller Hub) via a PCIE to AHB (PCIE to AHB) bridge. In this embodiment, in order to close the data transmission channel between the BIOS system 120 and the shared memory space 130, the BMC system 110 may close the PCIE channel between the BIOS system 120 and the shared memory space 130.

It should be understood that after the BMC system 110 completes writing the hardware state information into the shared memory space 130 of the computing device 100, in addition to storing the specified value in the BMC system flag bit of the register 150 to indicate that the BMC system 110 has completed writing the hardware state information, the BMC system flag bit may be set directly in the shared memory space 130 to store the specified value in the BMC system flag bit to indicate that the BMC system 110 has completed writing the hardware state information.

Similarly, after the BIOS system 120 completes writing the configuration information into the shared memory space 130 of the computing device 100, in addition to storing the specified value in the BIOS system flag bit of the register 150 to indicate that the BIOS system 120 has completed writing the hardware status information, the BIOS system flag bit may be set directly in the shared memory space 130 to store the specified value in the BIOS system flag bit to indicate that the BIOS system 120 has completed writing the hardware status information.

Referring to fig. 2 and fig. 7 in combination, the embodiment of the present application further provides a data interaction method applied to a BIOS system 120 in a computing device, where the computing device further includes a BMC system 110, and the method includes:

step S310: when the processor 140 in the computing device is powered on for self-test, the BIOS system 120 obtains the hardware state information stored in the shared memory space 130, and the hardware state information is written into the shared memory space 130 by the BMC system 110 when the power is on and the processor 140 in the computing device is not started.

As shown in fig. 6, both the processor 140 and the BIOS system 120 on the motherboard can be connected to the AHB bus on the BMC module through a P2A (PCIE to AHB) bridge through a PCH (Platform Controller Hub) to access the shared memory space 130 through the P2A. The PCIE (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, and belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices allocate an independent channel bandwidth, do not share a bus bandwidth, and mainly support end-to-end reliable transmission.

Therefore, when the processor 140 is powered on for self-test, the BIOS system 120 obtains the hardware state information stored in the shared memory space 130, and after completing the detection of the hardware state information, writes configuration information into the shared memory space 130, including: when the BIOS system 120 performs power-on self-test on the processor 140, the hardware state information stored in the shared memory space 130 is acquired through the PCIE channel, and after the hardware state information is detected, the configuration information is written into the shared memory space 130 through the PCIE channel.

The hardware state information read by the BIOS system 120 may be read by using a Single Input Single Output (SISO) reading method, or may be read by using a Single Input Multiple Output (SIMO) reading method; or reading the hardware state information by adopting a Multiple Input Single Output (MISO) reading mode; the hardware state information may also be read by a Multiple Input Multiple Output (MIMO) reading method.

As an optional implementation, when the processor 140 is powered on for self-test, the BIOS system 120 accesses the shared memory space 130 in a multi-input multi-output manner to obtain the hardware state information stored in the shared memory space 130.

The mimo read/write method is to use multiple antennas between two data transmission terminals (BIOS system 120 and shared memory space 130) for data interaction to form an antenna system with multiple channels, and has very high spectrum utilization efficiency, so as to greatly improve channel capacity, and thus, the mimo read/write method has very high read/write efficiency.

Step S320: after the BIOS system 120 completes detecting the hardware status information, it writes the configuration information into the shared memory space 130, so that the BMC system 110 reads the configuration information when the processor 140 starts the operating system.

The manner in which the BIOS system 120 detects the hardware state information may be various.

In one possible implementation, the detecting of the hardware state information may include: and performing cyclic redundancy detection on the hardware state information to detect whether the hardware state information is correct, and when the hardware state information is detected to be correct, completing the detection on the hardware state information.

In this way, when the cyclic redundancy detection is performed on the hardware state information, the preset cyclic redundancy code carried in the hardware state information is correct if the preset cyclic redundancy code is compared with the cyclic redundancy code obtained by performing the cyclic redundancy detection on the hardware state information, and the comparison result is that the comparison is consistent.

In another possible implementation, the detecting of the hardware state information may further include: and matching the hardware state information with preset state information, and if the hardware state information is consistent with the preset state information, finishing the detection of the hardware state information.

It should be understood that when the BIOS system 120 writes the configuration information into the shared memory space 130 after completing the detection of the hardware status information, the configuration information may also be written in a single-input single-output, single-input multiple-output, multiple-input single-output, or multiple-input multiple-output writing manner.

In an alternative embodiment, the BIOS system 120 accesses the shared memory space 130 in a mimo mode to store the configuration information in the shared memory space 130 when the processor 140 is powered on for self-test.

The shared memory space 130 may be a VGA shared memory space (VGA: video Graphics Array), a memory on the monitor board, or a memory configured on the motherboard.

In an optional implementation, the shared memory space 130 includes a first memory space and a second memory space, the first memory space is used for storing hardware state information, the second memory space is used for storing configuration information, and the BIOS system 120 writes the configuration information into the shared memory space 130, including: the BIOS system 120 writes configuration information into the second memory space.

For a detailed description of the shared memory space 130, reference may be made to the foregoing detailed description of step S120, and details are not repeated here.

By adopting the data interaction method, when the processor 140 in the computing device is powered on for self-checking, the BIOS system 120 obtains the hardware state information stored in the shared memory space 130, and the hardware state information is written into the shared memory space 130 when the BMC system 110 is in a powered-on state and the processor 140 in the computing device is not started; after the BIOS system 120 completes detecting the hardware status information, it writes the configuration information into the shared memory space 130, so that the BMC system 110 reads the configuration information when the processor 140 starts the operating system. The data needing to be interacted between the BMC system 110 and the BIOS system 120 can be accessed in a time-sharing mode by using the shared memory space 130 in the starting process of the computing device 100 (from the process that the processor 140 is not started to the process that the processor 140 is powered on for self-checking and the process that the processor 140 starts the operating system), so that the BMC system 110 and the BIOS system 120 are independent and independent from each other in the starting process of the computing device 100, the starting time of the system is shortened, and the reliability of the system is improved.

Referring to fig. 8, an embodiment of the present application further provides a data interaction method applied to a BIOS system 120 of a computing device, where the computing device further includes a BMC system 110, and the method includes:

step S410: when the processor 140 in the computing device is powered on for self-test, the BIOS system 120 obtains the hardware state information stored in the shared memory space 130, and the hardware state information is written into the shared memory space 130 by the BMC system 110 when the power is on and the processor 140 in the computing device is not started.

Step S420: after completing the detection of the hardware status information, the BIOS system 120 writes the configuration information into the shared memory space 130.

Step S430: the BIOS system 120 sets the BIOS flag bit in the register 150 to a second specified value, where the second specified value is used to indicate that the BIOS system 120 has completed writing the configuration information, so that the BMC system 110 detects that the BIOS flag bit in the register 150 is set to the second specified value, and reads the configuration information when the computing device starts the operating system.

The first designated value stored in the flag bit of the BIOS system may be 0 or 1. That is, when the BIOS system 120 sets the BIOS system flag bit in the register 150 to 1, it indicates that the BIOS system 120 has completed writing the configuration information. I.e. the shared memory space 130 stores the configuration information written by the BIOS system 120.

It should be understood that the BIOS system flag bit and the BMC system flag bit should be located in different storage locations of register 150. The first specified value and the second specified value may be the same, e.g., both the first specified value and the second specified value are 1.

By adopting the above setting of the present application, the BMC system flag bit and the BIOS system flag bit are set in the register 150, the BIOS system 120 obtains the hardware state information stored in the shared memory space 130 when the processor 140 is powered on for self-test and it is detected that the BMC system flag bit in the register 150 is set to the first specified value, writes the configuration information into the shared memory space 130 after completing the detection of the hardware state information, and sets the BIOS system flag bit in the register 150 to the second specified value, so that the BMC system 110 reads the configuration information when the processor 140 starts the operating system and it is detected that the BIOS system flag bit in the register 150 is set to the second specified value. When the computing device 100 uses the shared memory space 130 to access the data to be interacted between the BMC system 110 and the BIOS system 120 in a time-sharing manner during the starting process, whether the data to be interacted is stored in the shared memory space 130 or not needs to be confirmed according to the value of the system flag bit (the BIOS system flag bit and the BMC system flag bit), and data interaction can be performed after the data to be interacted is confirmed to be stored, so that the accuracy of data interaction is improved, and meanwhile, the BMC system 110 and the BIOS system 120 are independent and independent from each other during the starting process of the computing device 100, so that the system starting time is shortened, and the system reliability is improved.

Referring to fig. 9, fig. 9 shows a data interaction method provided by the embodiment of the present application, which is applied to the computing device 100 shown in fig. 1, and the method includes:

when the BMC system 110 is in the power-up state and the processor 140 in the computing device 100 is not started, the method proceeds to step S510: hardware state information is obtained.

After the BMC system 110 acquires the hardware state information, step S520 is executed: the hardware state information is written to the shared memory space 130 of the computing device 100.

After the BMC system completes writing the hardware information, step S530 is executed: the BMC system flag bit in register 150 is set to a first specified value.

Wherein the first specified value indicates that the BMC system 110 has completed writing the hardware status information.

When the BIOS system 120 acquires that the BMC system flag bit in the register 150 is set to the first specified value and the processor 140 is powered on for self-test, step S540 is executed: the hardware state information stored in the shared memory space 130 is obtained.

After the BIOS system 120 acquires the hardware information, the hardware information may be detected, and after the BIOS system 120 completes detecting the hardware status information, the step S550 is executed: configuration information is written into the shared memory space 130.

After completing writing the configuration information, the BIOS system 120 performs step S560: the BIOS system flag bit in register 150 is set to a second specified value.

Wherein the second specified value is used to indicate that the BIOS system 120 has completed writing the configuration information.

When the BMC system 110 detects that the BIOS system flag bit in the register 150 is set to the second designated value and the computing device 100 starts the operating system, the step S570 is executed: and reading the configuration information.

By adopting the above setting of the present application, the setting of the BMC system flag bit and the BIOS system flag bit in the register 150 may be implemented to confirm whether the shared memory space 130 stores the data to be interacted according to the value of the system flag bit (the BIOS system flag bit and the BMC system flag bit) when the computing device 100 uses the shared memory space 130 to access the data to be interacted between the BMC system 110 and the BIOS system 120 in a time-sharing manner during the starting process, and may perform data interaction after confirming that the data to be interacted is stored, so as to improve the accuracy of data interaction, and at the same time, the BMC system 110 and the BIOS system 120 are independent from each other and independent from each other during the starting process of the computing device 100, thereby shortening the system starting time and improving the system reliability.

Referring to fig. 10, an embodiment of the present application further provides an interactive apparatus 600, which is applied to a BMC system 110 of a computing device, where the computing device further includes a BIOS system 120, and the apparatus 600 includes: a first acquisition module 610 and an information reading module 620.

The first obtaining module 610 is configured to obtain hardware state information when the BMC system 110 is in a power-on state and the processor 140 in the computing device is not started, and write the hardware state information into the shared memory space 130 of the computing device, so that the BIOS system 120 obtains the hardware state information stored in the shared memory space 130 when the processor 140 is powered on for self-test, and writes configuration information into the shared memory space 130 after completing detection of the hardware state information.

In an implementation manner, the shared memory space 130 includes a first memory space and a second memory space, the first memory space is used for storing the hardware state information, the second memory space is used for storing the configuration information, and the first obtaining module 610 is further used for writing the hardware state information into the first memory space.

In one possible implementation, the first obtaining module 610 is further configured to write the hardware state information to the shared memory space 130 of the computing device through the memory channel.

In one implementation, the hardware status information includes motherboard FRU information and the configuration information includes asset information.

The information reading module 620 is configured to read configuration information when the processor 140 starts the operating system, where the configuration information is used to configure the operating system.

In an implementation manner, the data interaction device 600 further includes a first setting module, where the first setting module is configured to set the BMC system flag in the register 150 to a first specified value, and the first specified value indicates that the BMC system 110 has completed writing the hardware state information, so that the BIOS system 120 acquires the hardware state information stored in the shared memory space 130 when the BMC system flag in the register 150 is set to the first specified value and the processor 140 is powered on for self-test.

In one possible implementation, the information reading module 620 is further configured to read the configuration information when detecting that the BIOS system flag bit in the register 150 is set to a second specified value, and when the computing device starts the operating system, the second specified value is used to indicate that the BIOS system 120 has completed writing the configuration information.

In one embodiment, the data interaction device 600 further includes a channel closing module, which is configured to close a data transmission channel between the BIOS system 120 and the shared memory space 130.

In an implementation manner, the information reading module 620 is further configured to access the shared memory space 130 in a file mapping reading manner to read the configuration information when the processor 140 starts the operating system.

Referring to fig. 11, an embodiment of the present application further provides a data interaction apparatus 700 applied to a BIOS system 120 of a computing device, where the computing device further includes a BMC system 110, and the apparatus 700 includes: a second obtaining module 710 and an information writing module 720.

The second obtaining module 710 is configured to obtain the hardware state information stored in the shared memory space 130 when the processor 140 in the computing device is powered on for self-test, where the hardware state information is written into the shared memory space 130 by the BMC system 110 when the processor 140 in the computing device is in a powered on state and is not started.

In an implementation manner, the second obtaining module 710 is further configured to access the shared memory space 130 in a multi-input multi-output manner when the processor 140 is powered on for self-test, so as to obtain the hardware state information stored in the shared memory space 130.

The information writing module 720 is configured to write the configuration information into the shared memory space 130 after the hardware status information is detected, so that the BMC system 110 reads the configuration information when the processor 140 starts the operating system.

In an implementation manner, the second obtaining module 710 is further configured to obtain, when the processor 140 is powered on for self-test, hardware state information stored in the shared memory space 130 through the PCIE channel; the information writing module 720 is further configured to write configuration information into the shared memory space 130 through the PCIE channel.

In one embodiment, the shared memory space 130 includes a first memory space for storing hardware status information and a second memory space for storing configuration information. The information writing module 720 is further configured to write the configuration information into the second memory space.

In one possible implementation, the data interaction apparatus 700 further includes a second setting module, which is configured to set the BIOS system flag bit in the register 150 to a second specific value, and the second specific value is configured to indicate that the BIOS system 120 has completed writing the configuration information, so that the BMC system 110 reads the configuration information when detecting that the BIOS system flag bit in the register 150 is set to the second specific value and when the computing device starts the operating system.

In one possible implementation, the data interaction device 700 further includes: and the verification module is used for verifying the hardware state information by using cyclic redundancy check, and if the verification is successful, the detection of the hardware state information is finished.

Referring to fig. 5 and fig. 12, a computing device 100 provided in the present application is described, where the computing device 100 may be a server or a terminal device, and the terminal device may be a device such as a smart phone, a tablet computer, a computer, or a portable computer.

The computing device 100 includes a BMC system 110, a baseboard management controller 115, a BIOS system 120, a processor 140, and a shared memory space 130.

The BMC system 110 is configured to, when the power is turned on and the processor 140 in the computing device 100 is not started, obtain hardware state information, and write the hardware state information into the shared memory space 130 of the computing device 100; the BIOS system 120 is configured to, when the processor 140 is powered on for self-test, obtain hardware state information stored in the shared memory space 130, and write configuration information into the shared memory space 130 after completing detection of the hardware state information; the BMC system 110 is configured to read configuration information when the processor 140 starts an operating system, where the configuration information is used to configure the operating system.

In one embodiment, the computing device 100 further includes a register, the BMC system 110, further configured to set a BMC system flag bit in the register to a first specified value, where the first specified value indicates that the BMC system 110 has completed writing the hardware status information; the BIOS system 120 is further configured to obtain the hardware state information stored in the shared memory space 130 when the BMC system flag bit in the obtained register is set to the first specified value and the processor 140 is powered on for self-test.

In an optional embodiment, the BIOS system 120 is further configured to set a BIOS system flag bit in a register to a second specified value, where the second specified value is used to indicate that the BIOS system 120 has completed writing the configuration information; the BMC system 110 is further configured to read the configuration information when detecting that the BIOS system flag bit in the register is set to the second specific value and when the computing device 100 starts the operating system.

In an alternative embodiment, the BMC system 110 is further configured to close the data transmission channel between the BIOS system 120 and the shared memory space 130 after detecting that the BIOS system flag bit in the register is the second specified value.

In an optional embodiment, the BIOS system 120 is further configured to access the shared memory space 130 in a multi-input multi-output manner to obtain the hardware state information stored in the shared memory space 130 when the processor 140 is powered on for self-test.

In an alternative embodiment, the BMC system 110 is further configured to access the shared memory space 130 in a file-mapped reading manner to read the configuration information when the processor 140 starts the operating system.

In an optional implementation manner, the BIOS system 120 is further configured to verify the hardware status information by using a cyclic redundancy check after the hardware status information stored in the shared memory space 130 is obtained during power-on self-test of the processor 140, and if the verification is successful, complete detection of the hardware status information.

In an alternative embodiment, the shared memory space 130 includes a first memory space and a second memory space; the BMC system 110 is further configured to, in a power-on state and when the processor 140 in the computing device 100 is not started, obtain hardware state information, and write the hardware state information into the first memory space; when the BIOS system 120 performs power-on self-test on the processor 140, the hardware state information stored in the shared memory space 130 is acquired, and after the hardware state information is detected, the configuration information is written into the second memory space.

In an alternative embodiment, the shared memory space 130 is a video image array shared memory space 130.

In an optional embodiment, the BMC system 110 is further configured to, in a power-on state and when the processor 140 in the computing device 100 is not started, obtain hardware state information, and write the hardware state information into the shared memory space 130 of the computing device 100 through the memory channel; the BIOS system 120 is further configured to, when the processor 140 is powered on for self-test, obtain hardware state information stored in the shared memory space 130 through the PCIE channel, and write configuration information into the shared memory space 130 through the PCIE channel after completing detection of the hardware state information.

The baseboard management controller 115 is used to run the BMC system 110, which may be a system that includes one or more cores for processing data and a message matrix unit. The substrate management controller 115 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

Computing device 100 also includes memory 160. The memory 160 stores programs (programs of method steps executed by the BIOS system 120 and programs of method steps executed by the BMC system 110) capable of executing the contents of the foregoing embodiments, and the processor 140 executes programs of method steps executed by the BIOS system 120 stored in the memory 160. The processor 140 (e.g., baseboard management controller 115) associated with the BMC system 110 may be configured to execute the program of method steps executed by the BMC system 110 stored in the memory 160.

The Memory 160 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 160 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 160 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing various method embodiments described below, and the like. The storage data area may also store data (e.g., hardware state information and configuration information) obtained by the computing device 100 during use, and the like.

The computing device 100 may further include a network module for receiving and transmitting electromagnetic waves, and implementing interconversion between the electromagnetic waves and the electrical signals, so as to communicate with a communication network or other devices, such as an audio player. The network module may include various existing circuit elements for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor 140, an encryption/decryption chip, a Subscriber Identity Module (SIM) card, a memory 160, and so forth. The network module may communicate with various networks such as the internet, an intranet, a wireless network, or with other devices via a wireless network. The wireless network may comprise a cellular telephone network, a wireless local area network, or a metropolitan area network. The screen can display the interface content and perform data interaction.

In some embodiments, the computing device 100 may further include: a peripheral interface 170 and at least one peripheral device. The processor 140, memory 160, and peripheral interface 170 may be connected by bus or signal lines. Various peripheral devices may be connected to the peripheral interface 170 by buses, signal lines, or circuit boards. Specifically, the peripheral device includes: at least one of the radio frequency assembly 180, the positioning assembly 190, the camera 210, the audio assembly 220, the display screen 230, the power supply and the like

Peripheral interface 170 may be used to connect at least one peripheral associated with an I/O (Input/Output) to processor 140 and memory 160. In some embodiments, processor 140, memory 160, and peripheral interface 170 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 140, the memory 160, and the peripheral interface 170 may be implemented on a single chip or circuit board, which is not limited in this application.

The Radio Frequency assembly 180 is used for receiving and transmitting RF (Radio Frequency) signals, also called electromagnetic signals. The radio frequency assembly 180 communicates with communication networks and other communication devices via electromagnetic signals. The radio frequency module 180 converts an electrical signal into an electromagnetic signal to be transmitted, or converts a received electromagnetic signal into an electrical signal. Optionally, the radio frequency assembly 180 comprises: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor 140, a codec chipset, a subscriber identity module card, and so forth. The radio frequency assembly 180 may communicate with other terminals through at least one wireless communication protocol. The wireless communication protocols include, but are not limited to: the world wide web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and/or WiFi (Wireless Fidelity) networks. In some embodiments, the radio frequency component 180 may further include NFC (Near Field Communication) related circuits, which are not limited in this application.

The positioning component 190 is used to locate the current geographic location of the computing device 100 to implement navigation or LBS (location based Service). The positioning component 190 may be a positioning component based on the GPS (global positioning System) in the united states, the beidou System in china, or the galileo System in russia.

The camera 210 is used to capture images or video. Optionally, the camera 210 includes a front camera and a rear camera. Typically, the front facing camera is disposed on the front panel of the computing device 100 and the rear facing camera is disposed on the back of the computing device 100. In some embodiments, the number of the rear cameras is at least two, and each rear camera is any one of a main camera, a depth-of-field camera, a wide-angle camera and a telephoto camera, so that the main camera and the depth-of-field camera are fused to realize a background blurring function, and the main camera and the wide-angle camera are fused to realize panoramic shooting and VR (Virtual Reality) shooting functions or other fusion shooting functions. In some embodiments, camera 210 may also include a flash. The flash lamp can be a monochrome temperature flash lamp or a bicolor temperature flash lamp. The double-color-temperature flash lamp is a combination of a warm-light flash lamp and a cold-light flash lamp and can be used for light compensation under different color temperatures.

Audio component 220 may include a microphone and a speaker. The microphone is used for collecting sound waves of a user and the environment, converting the sound waves into electric signals, and inputting the electric signals into the processor 140 for processing or inputting the electric signals into the radio frequency assembly 180 to realize voice communication. The microphones may be multiple, each located in a different portion of the computing device 100 for stereo capture or noise reduction purposes. The microphone may also be an array microphone or an omni-directional pick-up microphone. The speaker is used to convert electrical signals from the processor 140 or the radio frequency components 180 into sound waves. The loudspeaker can be a traditional film loudspeaker and can also be a piezoelectric ceramic loudspeaker. When the speaker is a piezoelectric ceramic speaker, the speaker can be used for purposes such as converting an electric signal into a sound wave audible to a human being, or converting an electric signal into a sound wave inaudible to a human being to measure a distance. In some embodiments, audio component 220 may also include a headphone jack.

The display screen 230 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof. When the display screen 230 is a touch display screen 230, the display screen 230 also has the ability to capture touch signals on or over the surface of the display screen 230. The touch signal may be input to the processor 140 as a control signal for processing. At this point, the display screen 230 may also be used to provide virtual buttons and/or a virtual keyboard, also referred to as soft buttons and/or a soft keyboard. In some embodiments, the display screen 230 may be one, providing the front panel of the computing device 100; in other embodiments, the display screens 230 may be at least two, each disposed on a different surface of the computing device 100 or in a folded design; in still other embodiments, the display screen 230 may be a flexible display screen 230 disposed on a curved surface or on a folded surface of the computing device 100. Even more, the display screen 230 may be arranged in a non-rectangular irregular pattern, i.e., a shaped screen. The Display screen 230 may be made of LCD (Liquid Crystal Display, LCD 230), OLED (Organic Light-Emitting Diode), and the like.

The power supply is used to power various components in the computing device 100. The power source may be alternating current, direct current, disposable or rechargeable. When the power source includes a rechargeable battery, the rechargeable battery may be a wired rechargeable battery or a wireless rechargeable battery. The wired rechargeable battery is a battery charged through a wired line, and the wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery can also be used to support fast charge technology.

In summary, according to the data interaction method, the data interaction apparatus, the storage medium, and the computing device 100 provided in the present application, the data interaction method is applied to the computing device 100 including the BMC system 110 and the BIOS system 120, and the method includes: when the BMC system 110 is in a power-on state and the processor 140 in the computing device 100 is not started, acquiring hardware state information, and writing the hardware state information into the shared memory space 130 of the computing device 100, so that the BIOS system 120 can acquire the hardware state information stored in the shared memory space 130 when the processor 140 is in a power-on self-test, and after the hardware state information is detected, write configuration information into the shared memory space 130; the BMC system 110 reads the configuration information when the processor 140 starts the operating system, the configuration information being used to configure the operating system. By adopting the method of the present application, it is possible to use the shared memory space 130 in the process of executing boot startup after the computing device 100 is powered on (from the processor 140 not being started to the power-on self-test stage of the processor 140 and to the process of starting the operating system by the processor 140), so as to access the data that needs to be interacted in the boot process of the BMC system 110 and the BIOS system 120 in time sharing by using the shared memory space 130, and the purpose of mutual exclusion access in stages is achieved, so that the BMC system 110 and the BIOS system 120 are mutually independent and independent in the boot process of the computing device 100, thereby shortening the system boot time and improving the system reliability.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A data interaction method is applied to a BMC system of a computing device, the computing device further comprises a BIOS system, and the method comprises the following steps:

when the BMC system is in a power-on state and a processor in the computing device is not started, acquiring hardware state information, and writing the hardware state information into a shared memory space of the computing device, so that when the BIOS system is in a power-on self-test on the processor, the hardware state information stored in the shared memory space is acquired, and after the hardware state information is detected, configuration information is written into the shared memory space;

and the BMC system reads the configuration information when the processor starts an operating system, wherein the configuration information is used for configuring the operating system.

2. The data interaction method of claim 1, wherein after the BMC system writes the hardware state information to the shared memory space of the computing device, the method further comprises:

the BMC system sets a BMC system flag bit in a register to be a first designated value, the first designated value represents that the BMC system finishes writing in hardware state information, so that the BIOS system obtains that the BMC system flag bit in the register is set to be the first designated value, and when the processor is powered on and performs self-test, the hardware state information stored in the shared memory space is obtained.

3. The data interaction method of claim 1, wherein the BMC system reads the configuration information when the computing device starts the operating system, and comprises:

the BMC system reads the configuration information when detecting that the BIOS system flag bit in the register is a second designated value and when the computing device starts the operating system, the second designated value is used for indicating that the BIOS system finishes writing the configuration information.

4. The data interaction method of claim 3, wherein after the BMC system detects that the BIOS system flag bit in the register is a second specified value, the method further comprises:

and the BMC system closes a data transmission channel between the BIOS system and the shared memory space.

5. The data interaction method of claim 1, wherein the reading of the configuration information by the BMC system when the processor starts the operating system comprises:

and when the processor starts the operating system, the BMC system accesses the shared memory space in a file mapping reading mode to read the configuration information.

6. The data interaction method of claim 1, wherein the shared memory space comprises a first memory space and a second memory space, the first memory space is used for storing the hardware state information, the second memory space is used for storing the configuration information, and the BMC system writes the hardware state information into the shared memory space of the computing device, including:

and the BMC system writes the hardware state information into the first memory space.

7. The data interaction method of any one of claims 1 to 6, wherein writing the hardware state information to the shared memory space of the computing device by the BMC system comprises:

and the BMC system writes the hardware state information into a shared memory space of the computing equipment through a memory channel.

8. A data interaction method is applied to a BIOS system of a computing device, the computing device further comprises a BMC system, and the method comprises the following steps:

when a processor in computing equipment is subjected to power-on self-test, the BIOS system acquires hardware state information stored in a shared memory space, and the hardware state information is written into the shared memory space when the BMC system is in a power-on state and the processor in the computing equipment is not started;

after the BIOS system completes the detection of the hardware state information, writing configuration information into the shared memory space, so that the BMC system reads the configuration information when the processor starts an operating system.

9. The data interaction method of claim 8, wherein after the BIOS system writes configuration information into the shared memory space, the method further comprises:

the BIOS system sets a BIOS system flag bit in a register to a second specified value, wherein the second specified value is used for indicating that the BIOS system finishes writing in configuration information, so that the BMC system detects that the BIOS system flag bit in the register is the second specified value, and reads the configuration information when the computing device starts the operating system.

10. The data interaction method according to claim 8, wherein the obtaining, by the BIOS system, the hardware state information stored in the shared memory space when the processor is subjected to power-on self-test comprises:

and when the BIOS system is subjected to power-on self-test on the processor, accessing a shared memory space in a multi-input multi-output mode to acquire hardware state information stored in the shared memory space.

11. The data interaction method according to claim 8, wherein after the BIOS system obtains the hardware state information stored in the shared memory space when the processor is subjected to power-on self-test, the method further comprises:

and the BIOS system verifies the hardware state information by using cyclic redundancy check, and if the verification is successful, the detection of the hardware state information is finished.

12. A data interaction apparatus, applied to a BMC system of a computing device, wherein the computing device further includes a BIOS system, the apparatus comprising:

the first obtaining module is configured to obtain hardware state information when the BMC system is in a power-on state and a processor in the computing device is not started, and write the hardware state information into a shared memory space of the computing device, so that the BIOS system obtains the hardware state information stored in the shared memory space when the processor is subjected to power-on self-test, and writes configuration information into the shared memory space after the hardware state information is detected;

and the information reading module is used for reading the configuration information when the processor starts an operating system, and the configuration information is used for configuring the operating system.

13. A data interaction apparatus, applied to a BIOS system of a computing device, wherein the computing device further includes a BMC system, the apparatus comprising:

a second obtaining module, configured to obtain hardware state information stored in a shared memory space when a processor in a computing device is powered on for self-test, where the hardware state information is written into the shared memory space by the BMC system when the BMC system is in a powered on state and the processor in the computing device is not started;

and the information writing module is used for writing configuration information into the shared memory space after the hardware state information is detected, so that the BMC system reads the configuration information when the processor starts an operating system.

14. A computing device comprising a BIOS system, a BMC system, a processor, and a shared memory space;

the BMC system is used for acquiring hardware state information when the power is on and a processor in the computing equipment is not started, and writing the hardware state information into a shared memory space of the computing equipment;

the BIOS system is used for acquiring the hardware state information stored in the shared memory space when the processor is subjected to power-on self-test, and writing configuration information into the shared memory space after the hardware state information is detected;

the BMC system is used for reading the configuration information when the processor starts an operating system, and the configuration information is used for configuring the operating system.

15. A computer-readable storage medium, characterized in that the computer-readable storage medium stores program code that can be invoked by a processor to perform the method according to any one of claims 1-7 or 8-11.