CN115684725A - Three-phase intelligent loop resistance tester and testing method - Google Patents
Three-phase intelligent loop resistance tester and testing method Download PDFInfo
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- CN115684725A CN115684725A CN202211279688.2A CN202211279688A CN115684725A CN 115684725 A CN115684725 A CN 115684725A CN 202211279688 A CN202211279688 A CN 202211279688A CN 115684725 A CN115684725 A CN 115684725A
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Abstract
The invention belongs to the technical field of loop resistance testing, and particularly relates to a three-phase intelligent loop resistance tester and a testing method. The current source module is used for providing test current for the test load of three phases; the acquisition circuit acquires the current of the test load; the FPGA main control unit controls the current source module to provide test current for the test load and receives data of the acquisition circuit; and the controller is used for sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit. The invention can continuously output large current for a long time, can simultaneously realize the measurement of three-phase load, improves the measurement efficiency and precision, and reduces the manufacturing cost of detection equipment.
Description
Technical Field
The invention belongs to the technical field of loop resistance testing, and particularly relates to a three-phase intelligent loop resistance tester and a testing method.
Background
With the development of modern industry and the improvement of urban economic level, higher requirements are put on the safety and reliability of switch equipment. Particularly in urban power grids, switching actions are more frequent as the grid systems become more complex. The detection means for the switch equipment is more abundant and perfect, but the loop resistance test project of the switch equipment is always an important means for detecting the equipment defects of the switch equipment.
The existing circuit only measures a single phase but cannot measure three phases simultaneously during measurement, so that a test error is formed, and misjudgment on the switch state is caused.
Disclosure of Invention
The invention aims to provide a three-phase intelligent loop resistance tester which is stable and reliable in operation and greatly reduces the manufacturing cost of detection equipment.
The invention also provides a three-phase intelligent loop resistance testing method,
the present invention has been accomplished in such a manner that,
a three-phase intelligent loop resistance tester, the tester comprising:
the FPGA main control unit is used for controlling the supply of a test current to the test load and receiving the collected current of the test load;
and the controller is used for sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit.
Furthermore, the tester also comprises a current source module, and the controller controls the FPGA main control unit to combine or independently control the current source module to pass the test current to the load and controls the current source module to convert the test current.
Further, the tester also comprises a collecting circuit for collecting the current of the test load; when the FPGA main control unit is combined to open the current source module, different acquisition channels are established corresponding to different acquisition circuits to acquire data, or one acquisition channel is established corresponding to different acquisition circuits to acquire data in a queuing mode; and the FPGA main control unit numbers the data of different receiving channels and transmits the data to the controller.
Further, after the controller sends out a control instruction, whether the test channel of each phase is normal is detected according to the received data of the FPGA main control unit.
Further, the current source module includes: the rectification module is used for AC/DC converting the commercial power into direct-current voltage; the boost circuit boosts and outputs the rectified current information; and the half-bridge conversion circuit carries out DC/AC conversion on the current information, then the current information is isolated and reduced by the high-frequency transformer, and finally the current information is output with direct current voltage by the rectification filter module.
Further, the boost circuit adjusts the power factor to be 1 through the PFC controller, and controls the input current of the boost circuit to enable the input current to reach the phase difference with the input voltage to be 0; the BOOST circuit adopts a topology structure of a BOOST main circuit.
Furthermore, the current source module further comprises a PWM modulator for adjusting a PWM waveform duty ratio according to an instruction of the FPGA main control unit, and further controlling a turn-off frequency of the MOS transistor to stabilize an output current to a set value.
Furthermore, the acquisition circuit comprises a signal conditioning module and an A/D conversion module, wherein the signal conditioning module amplifies and filters the load output current, and transmits the digital signal after the current amount conversion to the FPGA main control unit for data processing after the A/D conversion module converts the load output current.
The invention also provides a three-phase intelligent loop resistance testing method, which comprises the following steps:
sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit;
the FPGA main control unit is used for controlling to provide test current for the test load and receiving the collected current of the test load.
Further, the sending a control instruction to the FPGA main control unit through the controller includes: and controlling the FPGA main control unit to combine or independently control the current source module to pass the test current to the load, and controlling the current source module to convert the test current.
Further, receiving the collected current of the test load comprises: when the current source module is switched on in a combined mode, different acquisition channels are established corresponding to different acquisition circuits to acquire data, or one acquisition channel is established corresponding to different acquisition circuits to acquire data in a queuing mode; and numbering the data of different acquisition circuits for transmission.
And further, detecting whether the test channel of each phase is normal or not according to the received data of the FPGA main control unit.
Compared with the prior art, the invention has the beneficial effects that:
the invention can continuously output large current for a long time, can simultaneously realize the measurement of three-phase load, improves the measurement efficiency and precision, and reduces the manufacturing cost of detection equipment.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 2 is a schematic diagram of a current source module according to an embodiment of the present invention;
fig. 3 is a flowchart of a three-phase intelligent loop resistance testing method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a three-phase intelligent loop resistance tester, which comprises:
the current source module is used for providing test current for the test load of three phases;
the acquisition circuit acquires the current of the test load, and comprises a signal conditioning module and an A/D conversion module, wherein the signal conditioning module amplifies and filters the current output by the load, and transmits the digital signal after current quantity conversion to the FPGA main control unit for data processing after the conversion of the A/D conversion module.
The FPGA main control unit controls the current source module to provide test current for the test load and receives data of the acquisition circuit;
and the controller is used for sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit.
Fig. 1 shows a specific embodiment of the present invention, which specifically includes a first current source module 1, a first signal conditioning module 2, a first a/D conversion module 3, a second current source module 4, a second signal conditioning module 5, a second a/D conversion module 6, a third current source module 7, a third signal conditioning module 8, a third a/D conversion module 9, a bluetooth module 10, a color touch screen 11, a man-machine interface 12, a WiFi communication module 14, and an FPGA main control unit 15, where the first current source module 1, the second current source module 4, and the third current source module 7 are all connected to the FPGA main control unit 15, the first signal conditioning module 2 is connected to the first current source module 1, the first a/D conversion module 3 is connected to the first conditioning signal module 2 and the FPGA main control unit 15, respectively, the second conditioning signal module 5 is connected to the second current source module 4, the second a/D conversion module 6 is connected to the second signal conditioning module 5 and the FPGA main control unit 15, the third conditioning signal module 8 is connected to the third conditioning module 7, the FPGA main control module 9 is connected to the FPGA main control module 15, and the WiFi conversion module 13 is connected to the touch screen module 11, and the FPGA main control unit 15.
The PFC controller adopts a UC3854 chip. The BOOST circuit 20 in the current source module 1 adopts a BOOST main circuit topology.
In this embodiment, the controller controls the FPGA main control unit to combine or individually control the current source module to pass the test current to the load, and controls the current source module to convert the test current. Different task instructions can be input through a color touch screen or a man-machine exchange interface connection keyboard, wherein the task instructions comprise different combinations of three-phase tests, and the magnitude and the test sequence of the test current adopted during each phase of test. The three current source modules can be measured simultaneously, or two current source modules can be combined and one current source module can be used for measuring.
When the FPGA main control unit is combined to open the current source module, the transmission of data is disordered during data transmission, data are acquired by establishing different acquisition channels corresponding to different acquisition circuits, or one acquisition channel is established corresponding to different acquisition circuits, and data are acquired in a queuing mode, wherein the queuing mode refers to dividing different time periods, and data which can only pass one-phase test can pass through one time period.
The FPGA main control unit numbers the data of different receiving channels according to different received data sources and transmits the data to the controller.
In order to avoid the fault of the test circuit, after the controller sends a control instruction, whether the test path of each phase is normal is judged and detected according to the received data of the FPGA main control unit, for example, when the acquisition circuit has a problem, the test circuit cannot acquire current data.
After the instrument is powered on, an operator can perform input, setting and other operations through the color touch screen 11, the STM32 controller processes an operation instruction through the FPGA main control unit 15 and then sends the operation instruction to the three power modules, namely the first current source module 1, the second current source module 4 and/or the third current source module 7, the three power modules respectively output currents to three loads, namely a first load 16, a second load 17 and a third load 18, current magnitude signals of the output currents are amplified, filtered and the like through respective signal conditioning units and then acquired through the first A/D conversion module 3, the second A/D conversion module 6 and the third A/D conversion module 9 respectively, digital signals obtained after current magnitude conversion are transmitted to the FPGA main control unit 15 for data processing, and processed results can be displayed on the man-machine exchange interface 12 or transmitted to a mobile end user application program APP through the WIFI communication module 14 for further data analysis, management, archiving and the like.
Referring to fig. 2, the first current source module 1, the second current source module 4 and the third current source module 7 in the present invention all adopt an AC/DC/AC/DC multi-stage conversion scheme, which includes: the rectification module is used for AC/DC converting the commercial power into direct-current voltage; the boost circuit boosts and outputs the rectified current information; and the half-bridge conversion circuit carries out DC/AC conversion on the current information, then the current information is isolated and reduced by the high-frequency transformer, and finally the current information is output with direct current voltage by the rectification filter module.
The boost circuit adjusts the power factor to 1 or close to 1 as much as possible through the PFC controller, and controls the input current of the boost circuit to enable the input current to be different from the input voltage by 0. The BOOST circuit adopts a BOOST main circuit topological structure.
The current source module also comprises a PWM modulator which is used for adjusting the duty ratio of a PWM waveform according to the instruction of the FPGA main control unit, and further controlling the turn-off frequency of the MOS tube to stabilize the output current to a set value.
The current source module of the invention combines a PFC controller (active power correction controller) and a PWM modulator, can obtain the intelligent direct current power supply with high power factor under high power, and has the working flow as follows: the direct current voltage of the commercial power after being rectified (AC/DC) by the rectifying module in the figure is subjected to the boosting circuit and the active Power Factor Correction (PFC) controller to improve the power factor of the system, is subjected to the inversion (DC/AC) of the half-bridge conversion circuit of the PWM modulator, is isolated and reduced by the high-frequency transformer, and is finally output by the rectifying (AC/DC) filtering module; an UC3854 chip is used as a correction core to realize an active power factor correction controller, the input current of a booster circuit of a BOOST main circuit topological structure is controlled to enable the phase difference between the input current and the input voltage to be 0, power factor correction is not carried out when the load is light, and the power factor correction circuit is automatically put into use when the load is large; the adoption of an active power factor correction controller (PFC) improves the power factor to be more than 0.95; the PWM modulator is used as a core, the duty ratio of the PWM waveform is automatically adjusted according to the set current value of the control port, and then the turn-off frequency of the MOS tube is controlled to stabilize the output current, so that the output current can be stabilized to a set value.
Referring to fig. 3, an embodiment of the present invention provides a three-phase intelligent loop resistance testing method, including:
sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit;
the FPGA main control unit controls to provide test current for the test load and receives the collected current of the test load, wherein the test load is a three-phase test load, the FPGA main control unit can provide the test current for the test load in an independent, any two or three simultaneous mode for the three-phase test load, and the test current is provided for the test load and is realized through the current source module.
Sending a control instruction to the FPGA main control unit, comprising: and controlling the FPGA main control unit to combine or independently control the current source module to pass the test current to the load, and controlling the current source module to convert the test current.
Receiving the collected current of the test load, comprising: when the current source module is switched on in a combined mode, different acquisition channels are established to acquire data corresponding to different acquisition circuits, or one acquisition channel is established to correspond to different acquisition circuits, and data are acquired in a queuing mode; and numbering the data of different acquisition circuits for transmission.
And detecting whether the test channel of each phase is normal or not according to the received data of the FPGA main control unit.
The method described above may be implemented by a controller having a program built therein.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the invention can be realized by adopting various computer languages, such as object-oriented programming language Java and transliteration scripting language JavaScript.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
Claims (12)
1. The utility model provides a three-phase intelligence return circuit resistance tester which characterized in that, this tester includes:
the FPGA main control unit is used for controlling the supply of a test current to the test load and receiving the collected current of the test load;
and the controller is used for sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit.
2. The three-phase intelligent loop resistance tester of claim 1, wherein the tester further comprises a current source module, and the controller controls the FPGA main control unit to either combine with or independently control the current source module to pass the test current to the load and control the current source module to convert the test current.
3. The three-phase smart loop resistance tester of claim 2 further comprising a collection circuit for collecting current of a test load; when the FPGA main control unit is combined to open the current source module, different acquisition channels are established corresponding to different acquisition circuits to acquire data, or one acquisition channel is established corresponding to different acquisition circuits to acquire data in a queuing mode; and the FPGA main control unit numbers the data of different acquisition circuits and transmits the data to the controller.
4. The three-phase intelligent loop resistance tester of claim 1, wherein after the controller sends the control instruction, whether the test path of each phase is normal is detected according to the received data of the FPGA main control unit.
5. The three-phase smart loop resistance tester as recited in claim 2 wherein said current source module comprises: the rectification module is used for AC/DC converting the commercial power into direct-current voltage; the boost circuit boosts and outputs the rectified current information; and the half-bridge conversion circuit is used for carrying out DC/AC conversion on the current information, then carrying out isolation voltage reduction through a high-frequency transformer, and finally outputting direct-current voltage through the rectifying and filtering module.
6. The intelligent three-phase loop resistance tester as claimed in claim 5, wherein the boost circuit regulates the power factor to 1 through the PFC controller, and controls the input current of the boost circuit to reach a phase difference of 0 with the input voltage; the BOOST circuit adopts a BOOST main circuit topological structure.
7. The three-phase intelligent loop resistance tester as recited in claim 5, wherein the current source module further comprises a PWM modulator for adjusting a PWM waveform duty ratio according to an instruction of the FPGA main control unit, and further controlling a turn-off frequency of the MOS transistor to stabilize an output current to a set value.
8. The three-phase intelligent loop resistance tester as claimed in claim 1, wherein the acquisition circuit comprises a signal conditioning module and an a/D conversion module, the signal conditioning module amplifies and filters the load output current, the signal conditioning module converts the load output current through the a/D conversion module, and then the digital signal converted by the current amount is transmitted to the FPGA main control unit for data processing.
9. A three-phase intelligent loop resistance testing method is characterized by comprising the following steps:
sending a control instruction to the FPGA main control unit and receiving data transmitted by the FPGA main control unit;
the FPGA main control unit controls to provide test current for the test load and receives the collected current of the test load.
10. The method for testing the resistance of the three-phase intelligent loop according to claim 9, wherein the step of sending a control instruction to the FPGA main control unit comprises the following steps: and controlling the FPGA main control unit to combine or independently control the current source module to pass the test current to the load, and controlling the current source module to convert the test current.
11. The method of claim 10, wherein receiving the collected current of the test load comprises: when the current source module is switched on in a combined mode, different acquisition channels are established corresponding to different acquisition circuits to acquire data, or one acquisition channel is established corresponding to different acquisition circuits to acquire data in a queuing mode; and numbering the data of different acquisition circuits for transmission.
12. The method for testing the resistance of the three-phase intelligent loop according to claim 10, further comprising detecting whether the test path of each phase is normal according to the received data of the FPGA main control unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211279688.2A CN115684725A (en) | 2022-10-19 | 2022-10-19 | Three-phase intelligent loop resistance tester and testing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211279688.2A CN115684725A (en) | 2022-10-19 | 2022-10-19 | Three-phase intelligent loop resistance tester and testing method |
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| Publication Number | Publication Date |
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| CN115684725A true CN115684725A (en) | 2023-02-03 |
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| CN202211279688.2A Pending CN115684725A (en) | 2022-10-19 | 2022-10-19 | Three-phase intelligent loop resistance tester and testing method |
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