CN115670514A

CN115670514A - Ultrasonic signal sampling circuit, ultrasonic signal sampling method and ultrasonic diagnostic apparatus

Info

Publication number: CN115670514A
Application number: CN202110858141.7A
Authority: CN
Inventors: 亓科; 于海泳; 王�琦
Original assignee: Qingdao Hisense Medical Equipment Co Ltd
Current assignee: Qingdao Hisense Medical Equipment Co Ltd
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2023-02-03

Abstract

The utility model relates to an ultrasonic signal processing technology field discloses an ultrasonic signal sampling circuit, ultrasonic signal sampling method and ultrasonic diagnostic apparatus, carry out signal demodulation to ultrasonic echo signal through signal demodulation module, obtain orthogonal first channel ultrasonic signal and second channel ultrasonic signal, and utilize voltage regulation module output adjustable first voltage for first ADC sampling module, and output adjustable second voltage for second ADC sampling module, make first ADC sampling module based on first voltage, sample first ultrasonic channel signal, obtain the digital signal of first channel ultrasonic signal, and second ADC sampling module is based on the second voltage, sample second ultrasonic channel signal, obtain the digital signal of second channel ultrasonic signal, thereby can solve the problem that the ultrasonic image that generates in the correlation technique has the mirror image.

Description

Ultrasonic signal sampling circuit, ultrasonic signal sampling method and ultrasonic diagnostic apparatus

Technical Field

The present application relates to the field of ultrasonic signal processing technologies, and in particular, to an ultrasonic signal sampling circuit, an ultrasonic signal sampling method, and an ultrasonic diagnostic apparatus.

Background

In the related art, after ultrasonic echo signals are demodulated, I/Q (In-phase/Quadrature) channel signals which represent doppler frequency offset information are obtained, and then the processed digital signals are sent to an upper computer through sampling processing of analog-to-digital conversion of the I/Q channel signals, and are operated In the upper computer to generate corresponding ultrasonic images. The input voltage of the analog-to-digital conversion device is a fixed voltage.

Generally, echo amplitude and frequency offset information of an ultrasonic echo signal are obtained in an upper computer according to an I channel signal and a Q channel signal, for example, when a cardiac blood flow state of a patient is checked by an ultrasonic diagnostic apparatus, a speed and an intensity of blood flow can be determined according to the obtained echo amplitude and frequency offset information. However, the ultrasound image obtained by the related art has a mirror image problem, which further affects the doctor to judge the real blood flow condition of the patient according to the ultrasound image.

Disclosure of Invention

The embodiment of the application provides an ultrasonic signal sampling circuit, an ultrasonic signal sampling method and an ultrasonic diagnostic apparatus, so that the problem that an ultrasonic image generated in the related technology has an image can be solved.

In a first aspect, an embodiment of the present application provides an ultrasound signal sampling circuit, including: the device comprises a signal demodulation module, a first analog-to-digital conversion ADC sampling module, a second analog-to-digital conversion ADC sampling module and a voltage regulation module;

the signal demodulation module is used for demodulating the ultrasonic echo signals to obtain orthogonal first channel ultrasonic signals and second channel ultrasonic signals;

the voltage adjusting module is used for outputting an adjustable first voltage to the first ADC sampling module and outputting an adjustable second voltage to the second ADC sampling module;

the first ADC sampling module is configured to sample the first channel ultrasonic signal based on the first voltage to obtain a digital signal of the first channel ultrasonic signal;

the second ADC sampling module is configured to sample the second channel ultrasonic signal based on the second voltage to obtain a digital signal of the second channel ultrasonic signal.

In some possible embodiments, the voltage regulation module comprises: a first voltage regulating unit and a second voltage regulating unit;

the first voltage regulating unit is used for outputting the adjustable first voltage to the first ADC sampling module;

the second voltage regulating unit is configured to output the adjustable second voltage to the second ADC sampling module.

In some possible embodiments, the first voltage regulating unit includes: the first digital-to-analog conversion DAC unit and the first low-noise operational amplifier unit;

the first DAC unit is used for outputting a first analog signal to the first low-noise operational amplifier unit;

the first low-noise operational amplifier unit is used for outputting the first voltage by utilizing the proportional relation between the first analog signal and the first voltage;

the second voltage regulating unit includes: the second digital-to-analog conversion DAC unit and the second low-noise operational amplifier unit;

the second DAC unit is used for outputting a second analog signal to the second low-noise operational amplifier unit;

and the second low-noise operational amplifier unit is used for outputting the second voltage by utilizing the proportional relation between the second analog signal and the second voltage.

In some possible embodiments, the first DAC cell is a current-type DAC chip or a voltage-type DAC chip, and the second DAC cell is a current-type DAC chip or a voltage-type DAC chip.

In some possible embodiments, the circuit further includes a memory for storing a first preset logic control word corresponding to the first voltage and a second preset logic control word corresponding to the second voltage;

the voltage adjusting module is specifically configured to read the first preset logic control word and the second preset logic control word from the memory, output the first voltage to the first ADC sampling module based on the first preset logic control word, and output the second voltage to the second ADC sampling module based on the second preset logic control word.

In a second aspect, an embodiment of the present application provides an ultrasound signal sampling method, including:

performing signal demodulation on the ultrasonic echo signal to obtain a first channel ultrasonic signal and a second channel ultrasonic signal which are orthogonal;

performing analog-to-digital conversion on the first channel ultrasonic signal based on an adjustable first voltage to obtain a digital signal of the first channel ultrasonic signal; and performing analog-to-digital conversion on the second channel ultrasonic signal based on the adjustable second voltage to obtain a digital signal of the second channel ultrasonic signal.

In some possible embodiments, determining the first voltage comprises:

performing analog-to-digital conversion on the first channel ultrasonic signal by using a first initial voltage to obtain a first test value;

adjusting the first initial voltage until the difference value between the first test value and a first preset digital signal is within a preset threshold range to obtain the first voltage;

determining the second voltage, comprising:

performing analog-to-digital conversion on the second channel ultrasonic signal by using a second initial voltage to obtain a second test value;

and adjusting the second initial voltage until the difference value between the second test value and a second preset digital signal is within the preset threshold range to obtain the second voltage.

In some possible embodiments, the adjusting the first initial voltage includes:

if the first test value is greater than the first preset digital signal, increasing the first initial voltage;

if the first test value is less than the first preset digital signal, reducing the first initial voltage;

the adjusting the second initial voltage includes:

if the second test value is greater than the second preset digital signal, increasing the second initial voltage;

and if the second test value is smaller than the second preset digital signal, reducing the second initial voltage.

In some possible embodiments, the first initial voltage is increased or decreased by:

increasing the first initial voltage by increasing a first preset logic control word bit by bit;

reducing the first initial voltage by reducing a first preset logic control word bit by bit;

increasing or decreasing the second initial voltage by:

increasing the second initial voltage by increasing a second preset logic control word bit by bit;

the second initial voltage is reduced by reducing a second preset logic control word bit by bit.

In some possible embodiments, the adjusting the first initial voltage includes: adjusting the first initial voltage by adopting a bisection method;

the adjusting the second initial voltage includes: and adjusting the second initial voltage by adopting a bisection method.

In a third aspect, an embodiment of the present application provides an ultrasonic diagnostic apparatus, including: a probe, a display unit, a processor and an ultrasound signal sampling circuit as described in any of the first aspects;

the probe is used for emitting ultrasonic beams and receiving ultrasonic echo signals;

the processor is configured to send the digital signals to an upper computer and receive the ultrasonic images sent by the upper computer; the digital signal is obtained through the ultrasonic signal sampling circuit;

the display unit is used for displaying the ultrasonic image.

In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, in which instructions, when executed by a processor of an electronic device, enable the electronic device to perform any one of the methods as provided in the second aspect of the present application.

In a fifth aspect, an embodiment of the present application provides a computer program product comprising computer programs/instructions which, when executed by a processor, implement any of the methods as provided in the second aspect of the present application.

The technical scheme provided by the embodiment of the application at least has the following beneficial effects:

the application provides an ultrasonic signal sampling circuit, carry out signal demodulation to supersound echo signal through signal demodulation module, obtain orthogonal first passageway ultrasonic signal and second passageway ultrasonic signal, and utilize voltage regulation module output adjustable first voltage for first ADC sampling module, and output adjustable second voltage for second ADC sampling module, make first ADC sampling module based on first voltage, sample first supersound passageway signal, obtain the digital signal of first passageway ultrasonic signal, and second ADC sampling module is based on the second voltage, sample second supersound passageway signal, obtain the digital signal of second passageway ultrasonic signal.

This application passes through adjustable first voltage of voltage regulation module output and adjustable second voltage, and then samples first passageway ultrasonic signal and second passageway ultrasonic signal based on first voltage after the regulation and second voltage to can reduce because the not identical problem of supersound echo amplitude that device parameter discreteness leads to, and then can solve the problem that has the mirror image in the ultrasonic image.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of transmitting an ultrasound beam to blood flowing in a blood vessel according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a related art ultrasonic signal sampling circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a related art ultrasonic signal sampling circuit according to an embodiment of the present application;

fig. 4 is a schematic diagram of a composite signal under the conditions that the relative amplitude error of two-channel ultrasonic signals is small and the mirror frequency is not obvious according to an embodiment of the present application;

fig. 5 is a schematic diagram of an ultrasound image under the condition that the relative amplitude error of two-channel ultrasound signals is small and the mirror frequency is not obvious according to an embodiment of the present application;

fig. 6 is a schematic diagram of a composite signal under the condition that the relative amplitude error of two-channel ultrasonic signals is large and the mirror frequency is obvious according to an embodiment of the present application;

fig. 7 is a schematic diagram of an ultrasound image of a two-channel ultrasound signal provided in an embodiment of the present application under the condition that a relative amplitude error is large and a mirror frequency is obvious;

FIG. 8 is a schematic diagram of an ultrasonic signal sampling circuit according to an embodiment of the present application;

fig. 9 is a schematic diagram of an internal structure of a first ADC sampling module according to an embodiment of the present application;

FIG. 10 shows an exemplary analog voltage difference of 2 ^N A corresponding relation schematic diagram of each voltage value;

fig. 11 is a schematic diagram illustrating a connection relationship between a current-mode DAC chip and a low-noise operational amplifier chip according to an embodiment of the disclosure;

FIG. 12 is a flow chart of a first voltage calibration provided by an embodiment of the present application;

fig. 13 is a block diagram of a hardware configuration of an ultrasonic diagnostic apparatus according to an embodiment of the present application;

fig. 14 is a schematic diagram of an application principle provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described in detail and clearly with reference to the accompanying drawings. In the description of the embodiments of the present application, "/" indicates an alternative meaning, for example, a/B may indicate a or B; "and/or" in the text is only an association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: three cases of a alone, a and B both, and B alone exist, and in addition, "a plurality" means two or more than two in the description of the embodiments of the present application.

In the description of the embodiments of the present application, the term "plurality" means two or more unless otherwise specified, and other terms and the like should be understood similarly, and the preferred embodiments described herein are only for the purpose of illustrating and explaining the present application, and are not intended to limit the present application, and features in the embodiments and examples of the present application may be combined with each other without conflict.

All other embodiments, which can be derived by a person skilled in the art from the exemplary embodiments described herein without making any inventive step, are intended to be within the scope of the claims appended hereto. In addition, while the disclosure herein has been presented in terms of one or more exemplary examples, it should be appreciated that aspects of the disclosure may be implemented solely as a complete embodiment.

It should be noted that the brief descriptions of the terms in the present application are only for convenience of understanding of the embodiments described below, and are not intended to limit the embodiments of the present application. These terms should be understood in their ordinary and customary meaning unless otherwise indicated.

The terms "first," "second," "third," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between similar or analogous objects or entities and are not necessarily intended to limit the order or sequence of any particular one, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or device that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such product or device.

To further illustrate the technical solutions provided by the embodiments of the present application, the following detailed description is made with reference to the accompanying drawings and the detailed description. Although the embodiments of the present application provide method steps as shown in the following embodiments or figures, more or fewer steps may be included in the method based on conventional or non-inventive efforts. In steps where no necessary causal relationship exists logically, the order of execution of the steps is not limited to that provided by the embodiments of the present application. The method can be executed in the order of the embodiments or the method shown in the drawings or in parallel in the actual process or the control device.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In a specific practical process, the working principle of examining the state of the blood flow of the heart of a patient by using an ultrasonic diagnostic apparatus is shown in fig. 1, which shows a schematic diagram of a probe emitting ultrasonic beams to the blood flowing in a blood vessel, and the signal frequency of the ultrasonic beams emitted by the probe is assumed to be F ₀ The signal frequency of the ultrasonic echo signal is F ₀ +F _d The blood velocity V flowing in the blood vessel is V, the angle between the ultrasonic beam and the blood velocity is θ, and the blood flow velocity V can be expressed by formula 1 according to the doppler principle.

V＝(C*F _d )(2 F ₀ * cos θ) equation 1

Wherein C represents the transmission of the ultrasonic beam in the human bodyThe transport speed, i.e., 1540 m/sec, and F ₀ For known values, θ can be measured in the ultrasound image, if F is determined _d The blood flow velocity may be calculated according to equation 1.

In the related art, as shown in fig. 2, a signal demodulation module 101 is used to demodulate an ultrasonic echo signal, and a doppler frequency offset signal carrying blood flow velocity information, that is, a first channel ultrasonic signal (I channel signal) and a second channel ultrasonic signal (Q channel signal) orthogonal in a mathematical sense, is demodulated by using a doppler principle in a demodulation process. Then, the first channel ultrasonic signal is output to the first gain module 102, signal filtering and gain amplification processing are performed in the first gain module 102, and the processed first channel ultrasonic signal is output to a first ADC (Analog-to-Digital Converter) sampling module 103. The second channel ultrasonic signal is output to the second gain module 104, signal filtering and gain amplification processing are performed in the second gain module 104, and the processed second channel ultrasonic signal is output to the second ADC sampling module 105.

In the first ADC sampling module 103, the processed first channel ultrasonic signal is sampled based on the input first fixed voltage, so as to obtain a digital signal of the first channel ultrasonic signal. In the second ADC sampling module 105, the processed second channel ultrasonic signal is sampled based on the input second fixed voltage, so as to obtain a digital signal of the second channel ultrasonic signal. Here, the first fixed voltage and the second fixed voltage may or may not be multiplexed with the same voltage source, and are not limited herein.

And outputting the digital signals of the first channel ultrasonic signals and the digital signals of the second channel ultrasonic signals to the upper computer 106, and calculating the blood flow speed and the intensity of the patient according to the digital signals in the upper computer 106.

As shown in fig. 3, the signal demodulation module 101 may further include low noise amplifiers 1, …, a low noise amplifier n, voltage-to-current converters 1, …, a voltage-to-current converter n, a mixer 1, a mixer 2, …, a mixer 2n, a summing amplifier 1, a summing amplifier 2, and a clock distribution circuit 1, where one ultrasonic echo signal corresponds to one low noise amplifier, one voltage-to-current converter, two mixers, and two clock control signals. After the clock 1 passes through the clock distribution circuit 1, the distributed clock 1a is sent to the mixer 1, and the clock 1b is sent to the mixer 2. And mixer 1 is the first channel ultrasonic signal and mixer 2 is the second channel ultrasonic signal.

The first gain module 102 may further include a first signal filtering unit 1021 and a first gain amplifying unit 1022, where the first signal filtering unit 1021 is configured to perform signal filtering on the first channel ultrasonic signal, and output the filtered signal to the first gain amplifying unit 1022; the first gain amplifying unit 1022 is configured to perform gain amplification processing on the filtered first channel ultrasonic signal.

The second gain module 104 may further include a second signal filtering unit 1041 and a second gain amplifying unit 1042, where the second signal filtering unit 1041 is configured to perform signal filtering on the second channel ultrasonic signal, and output the filtered signal to the second gain amplifying unit 1042; the second gain amplifying unit 1042 is configured to perform gain amplification processing on the filtered second channel ultrasonic signal.

In general, the doppler frequency offset signal (i.e. the blood flow velocity and intensity of the patient) is reflected by two parameters, namely, the phase and the relative amplitude (i.e. the difference between the amplitudes of the two ultrasonic signals) of the first channel ultrasonic signal and the second channel ultrasonic signal. Because the actual parameters of the devices adopted in the modules have deviation from the standard parameters of the devices, that is, the problem of parameter discreteness exists, the calculated phases and relative amplitudes of the first channel ultrasonic signals and the second channel ultrasonic signals have errors with the respective corresponding standard values. When the error is large, the problem of mirror image exists in the ultrasonic image generated in the upper computer 106, and the real blood flow condition of the patient is further influenced by a doctor according to the ultrasonic image.

Illustratively, assuming that the relative amplitude error of the first channel ultrasonic signal and the second channel ultrasonic signal is K, the amplitude I (t) of the first channel ultrasonic signal is expressed by equation 2, the amplitude Q (t) of the second channel ultrasonic signal is expressed by equation 3, and the amplitude X (t) of the composite signal of the first channel ultrasonic signal and the second channel ultrasonic signal in the upper computer 106 is expressed by equation 4.

I (t) = cos (ω t) formula 2

Q (t) = (1+K) sin (ω t) equation 3

X(t)＝I(t)+Q(t)＝cos(ωt)+j(1+K)sin(ωt)＝(1+K/2)e ^jωt -(K/2)e ^j(-ω)t Equation 4

Where ω represents angular frequency, t represents time, cos (ω t) represents cosine, sin (ω t) represents sine, j represents complex number, and e represents the base of the natural logarithm.

As can be seen from the above equation 4, since there is an error in the relative amplitude of the first channel ultrasonic signal and the second channel ultrasonic signal, the mirror frequency- ω is generated, and if the relative amplitude error K of the first channel ultrasonic signal and the second channel ultrasonic signal is 0, the mirror frequency is not generated.

As shown in fig. 4, a schematic diagram of a composite signal in the case that the relative amplitude error of the first channel ultrasonic signal and the second channel ultrasonic signal is small and the mirror frequency is not obvious is shown, the ordinate represents the velocity of blood flow in centimeters per second (cm/s), and the positive and negative half axes represent the direction of blood flow. For example, when the probe emits an ultrasonic beam to blood flowing in a blood vessel, a direction toward the probe is defined as a positive half axis, and a direction away from the probe is defined as a negative half axis. This is merely an example and may be adjusted according to the application.

Fig. 5 shows a schematic diagram of an ultrasound image in the case where the relative amplitude error of the first channel ultrasound signal and the second channel ultrasound signal is small and the mirror frequency is not obvious, which is a normal heart mitral valve blood flow ultrasound image. The coordinate meanings in the figure are the same as those in fig. 4, and are not described herein again.

When the mirror frequency is generated, the generated ultrasound image may be distorted. As shown in fig. 6, a schematic diagram of a composite signal when the relative amplitude error of the first channel ultrasonic signal and the second channel ultrasonic signal is large and the mirror frequency is obvious is shown, and it can be known from a comparison of fig. 4 that the closed curve in fig. 6 is an error composite signal generated by the mirror frequency. The meaning of the coordinates in the figure is the same as that in fig. 4, and the description is omitted here.

Fig. 7 shows an ultrasound image diagram of the case where the relative amplitude error of the first channel ultrasound signal and the second channel ultrasound signal is large and the mirror frequency is obvious, and the diagram shows that when the mirror frequency is obvious, the ultrasound image of the blood flow of the mitral valve of the heart shows a symmetrical form with respect to the positive and negative half axes of the ordinate. The coordinate meanings in the figure are the same as those in fig. 4, and are not described herein again.

In summary, due to the parameter discreteness of each device, the phases and the relative amplitudes of the first channel ultrasonic signal and the second channel ultrasonic signal have errors relative to the respective standard values, and then the mirror frequency is generated, so that the ultrasonic image is distorted, and the judgment of the doctor on the real condition of the patient is influenced. However, the phase error is mainly determined by the design of the mixer in the signal demodulation module, which is a problem of circuit performance inside the signal demodulation module, and the currently adopted signal demodulation module can make the phase error within a specified error range.

Because the relative amplitude error is relevant with the link design of the first channel ultrasonic signal and the second channel ultrasonic signal, even if a device with high discreteness precision is selected to reduce the relative amplitude error in the correlation technique, as shown in fig. 6, a composite signal generated by the image frequency still objectively exists, so that the ultrasonic signal sampling circuit provided by the application improves the accuracy of signal sampling by reducing the relative amplitude error, and further solves the problem that the image exists in the ultrasonic image generated in the correlation technique.

As shown in fig. 8, an ultrasonic signal sampling circuit provided by the present application is shown, and based on the circuit structure shown in fig. 3, the circuit further includes a voltage adjusting module 107, configured to output an adjustable first voltage to the first ADC sampling module 103 and output an adjustable second voltage to the second ADC sampling module 105. Then, the first ADC sampling module 103 is configured to sample the first channel ultrasonic signal based on the first voltage to obtain a digital signal of the first channel ultrasonic signal; and the second ADC sampling module 105 is configured to sample the second channel ultrasonic signal based on the second voltage to obtain a digital signal of the second channel ultrasonic signal.

Through increasing voltage regulation module 107 for first ADC sampling module 103 and second ADC sampling module 105 can carry out more accurate sampling to the signal based on the adjustable voltage of voltage regulation module 107 output, and then can obtain more accurate digital signal, make with digital signal output for the host computer after, for in the correlation technique based on fixed voltage sampling generation digital signal and export for the host computer, the image problem is avoided to the ultrasound image that this application generated.

The voltage regulation module 107 may further include: a first voltage adjusting unit 1071 and a second voltage adjusting unit 1072. The first voltage adjusting unit 1071 is configured to output an adjustable first voltage to the first ADC sampling module 103; the second voltage adjusting unit 1072 is configured to output an adjustable second voltage to the second ADC sampling module 105.

Because the first channel ultrasonic signal and the second channel ultrasonic signal are two parallel independent channel signals, the voltage of the two channels is adjusted respectively, and the adjustment is more accurate. That is, the first voltage adjusting unit 1071 determines the adjustable first voltage, and the second voltage adjusting unit 1072 determines the adjustable second voltage, and the first voltage and the second voltage are adjusted respectively to obtain more accurate first voltage and second voltage.

In addition, the first voltage adjusting unit 1071 may further include: a first Digital-to-Analog Converter (DAC) unit 10711 and a first low noise operational amplifier unit 10712. A first DAC unit 10711 for outputting a first analog signal to the first low noise operational amplifier unit 10712; the first low noise operational amplifier 10712 is configured to output a first voltage according to a proportional relationship between the first analog signal and the first voltage.

Likewise, the second voltage adjusting unit 1072 may further include: a second digital-to-analog conversion DAC unit 10721, and a second low noise operational amplifier unit 10722. A second DAC unit 10721 for outputting a second analog signal to the second low noise operational amplifier unit 10722; the second low noise operational amplifier 10722 is configured to output a second voltage according to a proportional relationship between the second analog signal and the second voltage.

The specific device types of the first digital-to-analog converting DAC unit 10711, the first low-noise operational amplifier unit 10712, the second digital-to-analog converting DAC unit 10721, and the second low-noise operational amplifier unit 10722 are not limited herein, and may be adjusted according to practical applications.

The first analog signal is processed by the first digital-to-analog conversion DAC unit 10711 and the first low-noise operational amplifier unit 10712, so that a more accurate first voltage can be obtained; by processing the second analog signal by the second digital-to-analog converting DAC unit 10721 and the second low-noise operational amplifier unit 10722, a more accurate second voltage can be obtained. Also, effective driving of the load can be achieved by the first and second low noise op-amp units 10712 and 10722, and the output first and second voltages are more stable and less electrically noisy.

Here, the first DAC unit 10711 is a current-type DAC chip or a voltage-type DAC chip, and the second DAC unit 10721 is a current-type DAC chip or a voltage-type DAC chip. The specific type of the chip is not limited herein, and can be adjusted according to the actual application. By setting the specific device compositions of the first DAC unit 10711 and the second DAC unit 10721, the signal processing of the first analog signal and the second analog signal can be performed more accurately.

The circuit further comprises a memory 108 for storing a first preset logic control word corresponding to the first voltage and a second preset logic control word corresponding to the second voltage. The voltage adjusting module 107 reads the first preset logic control word and the second preset logic control word from the memory 108, and outputs a first voltage to the first ADC sampling module 103 based on the first preset logic control word and outputs a second voltage to the second ADC sampling module 105 based on the second preset logic control word. Here, the memory 108 may be a rewritable memory.

The first preset logic control word and the second preset logic control word which are adjusted are stored in the memory 108, so that when the ultrasonic echo signal is processed again, the first preset logic control word and the second preset logic control word can be directly obtained, the first voltage and the second voltage do not need to be adjusted again, and the calculated amount is reduced.

After the circuit connection structure of the ultrasonic signal sampling circuit is introduced, an ultrasonic signal sampling method is introduced, which specifically comprises the following steps:

a1, performing signal demodulation on an ultrasonic echo signal to obtain a first channel ultrasonic signal and a second channel ultrasonic signal which are orthogonal;

a2, performing analog-to-digital conversion on the first channel ultrasonic signal based on the adjustable first voltage to obtain a digital signal of the first channel ultrasonic signal; and performing analog-to-digital conversion on the second channel ultrasonic signal based on the adjustable second voltage to obtain a digital signal of the second channel ultrasonic signal.

Through sampling first passageway ultrasonic signal, second passageway ultrasonic signal respectively based on adjustable first voltage and adjustable second voltage, can only sample first passageway ultrasonic signal, second passageway ultrasonic signal respectively through fixed voltage among the prior art, can reduce because the error that the device discreteness leads to, and then can obtain more accurate digital signal.

The ultrasonic signal sampling method is described in three parts, and comprises the following steps: 1. determining a first preset digital signal and a second preset digital signal, determining a first voltage and a second voltage, calibrating the first preset digital signal and a first test value, and calibrating the second preset digital signal and a second test value.

1. Determining a first preset digital signal and a second preset digital signal

The ultrasonic echo signal is described in a frequency domain representation, assuming that the ultrasonic echo signal is represented as A x sin [ (omega) sin ₀ +ω _d )*t]Where A denotes the signal amplitude, ω ₀ Representing angular frequency, ω, of the carrier wave _d Representing the angular frequency of the doppler frequency shift. If (4/pi). Sin (omega) is used respectively ₀ t) and (4/pi) × cos (ω) ₀ t) is multiplied by the expression of the ultrasonic echo signal to obtain the following

formulas

5 and 6.

A*sin[(ω ₀ +ω _d )*t]*(4/π)*sin(ω ₀ t)＝(2/π)A[cos(ω _d t)-cos(2ω ₀ +ω _d )]Equation 5

A*sin[(ω ₀ +ω _d )*t]*(4/π)*cos(ω ₀ t)＝(2/π)A[sin(ω _d t)+sin(2ω ₀ +ω _d )]Equation 6

After the signals in the formula 5 and the formula 6 are input to the low-pass filter, the high-frequency signal part 2 ω in the formula 5 and the formula 6 is filtered ₀ +ω _d Obtaining a frequency offset omega including Doppler frequency offset _d I.e. the first channel ultrasonic signal and the second channel ultrasonic signal. Obtaining Doppler frequency offset omega _d Then, the upper computer 106 passes the above equations 1 and F _d ＝2πω _d The velocity of the blood flow is known.

The first channel ultrasonic signal and the second channel ultrasonic signal are respectively output to the first ADC sampling module 103 and the second ADC sampling module 105, so as to obtain a first preset digital signal output by the first ADC sampling module 103 and a second preset digital signal output by the second ADC sampling module 105.

Taking the process of the first ADC sampling module 103 outputting the first preset digital signal as an example for explanation:

assuming that the internal structure of the first ADC sampling module 103 is as shown in fig. 9, the first channel ultrasonic signal is divided in the first gain amplifying unit 1022 to obtain a third channel ultrasonic signal and a fourth channel ultrasonic signal. One of the third channel ultrasonic signal and the fourth channel ultrasonic signal is input to the pin 9, and the other signal is input to the pin 10. And inputs the corresponding inputtable voltage value of the first ADC sampling module 103 to pin 3. And outputs a corresponding first preset digital signal through

pins

19 and 20.

In fig. 9, pin 1 indicates a conversion start flag bit CONVST, pin 2 indicates a chip register reset signal RST, pin 3 indicates a reference voltage input REFIN, pin 4 indicates a reference voltage "ground" REFM-4, pin 5 indicates a chip internal reference voltage REFBUFOUT, pin 6 indicates a connectionless NC, pin 7 indicates a chip internal reference voltage REFP, pin 8 indicates a reference voltage "ground" REFM-8, pin 9 indicates an analog input signal AINP, pin 10 indicates an analog input signal AINM, pin 11 indicates a chip power supply "ground" GND-11, pin 12 indicates an analog power supply RVDD, pin 13 indicates a chip power supply filter DECAP-13, pin 14 indicates a chip power supply filter DECAP-14, pin 15 indicates a chip power supply "ground" 15, pin 16 indicates a chip digital interface power supply dvrvdd, pin 17 indicates a conversion data output 3SDO-3, pin 18 indicates a chip power supply filter DECAP-14, pin 15 indicates a chip power supply signal SDO-15, pin 16 indicates a chip digital interface power supply output pin 19 indicates a chip power supply, pin 18 indicates a chip serial data output pin 19 indicates a serial data output pin 19-2, pin 21 indicates a serial data output pin 23 indicates a serial data output pin 19, and SDO-2 indicates a serial data output pin 23.

Assuming that the resolution number of bits in the first ADC sampling module 103 is N, N is a positive integer, the analog voltage value difference between the third channel ultrasonic signal and the fourth channel ultrasonic signal is U, and the input voltage value corresponding to the first ADC sampling module 103 is V _ REF, the converted first preset digital signal is obtained by formula 7:

first preset digital signal = U × 2 ^N-1 V _ REF equation 7

Specifically, (-V _ REF, V _ REF) is equally divided into 2 ^N Equal parts, as shown in FIG. 10, the difference between the analog voltage values U and 2 ^N The voltage values are compared, and the closest voltage value is selected as the output digital signal. Ordinate in FIG. 10 indicates 2 ^N A voltage value, i.e., (-2) ^N-1 ，2 ^N-1 ) The abscissa represents the difference U of the analog voltage values in LSB, e.g. -2 ^N-1 Corresponding U is 1-V _ REF,2 ^N-1 The corresponding U is-1 + V \ U REF.

The process of outputting the second preset digital signal by the second ADC sampling module 105 may refer to the process of outputting the first preset digital signal by the first ADC sampling module 103, and is not described herein again.

2. Determining the first voltage and the second voltage

Taking the first DAC unit 10711 as a current-mode DAC chip as an example, the first voltage is determined by the following steps:

b1, performing analog-to-digital conversion on the first channel ultrasonic signal by using a first initial voltage to obtain a first test value;

and B2, adjusting the first initial voltage until the difference value between the first test value and the first preset digital signal is within a preset threshold range to obtain a first voltage.

Illustratively, since the corresponding inputtable voltage value of the first ADC sampling module 103 is a designated voltage value range, a voltage within the designated voltage value range is optionally used as the first initial voltage, as shown in fig. 11, which shows a schematic connection relationship between the current-mode DAC chip and the low-noise op-amp chip. By writing any logic control input bit into the current type DAC chip, the output voltage corresponding to the logic control input bit can be obtained. Therefore, after the first initial voltage is determined, the logic control input bit corresponding to the first initial voltage can be determined through calculation, and then the purpose of adjusting the first initial voltage is achieved by adjusting the logic control input bit.

Specifically, pin 1 to pin 10 in the current-mode DAC chip are logic control input bits, and pin 22 is a current value I output by the current-mode DAC chip _OUT1 When the current value flows through the resistor R1, the voltage V is output _+IN . Simultaneous voltage V _+IN As the input of the pin 4 in the low-noise operational amplifier chip, the low-noise operational amplifier chip forms a same-phase proportional amplifying circuit through the resistors R2 and R3, therefore, the pin 6 of the low-noise operational amplifier chip outputs a first voltage and the voltage V of the pin 4 _+IN The input relationship is represented by equation 8. And, V _+IN ＝I _OUT1* R1, then the first voltage and V _+IN The input relationship can also be expressed by equation 9.

First voltage = ((R2 + R3)/R2) × V _+IN Equation 8

First voltage = ((R2 + R3)/R2) × I _OUT1* R1 formula 9

Pin 1 of the current-mode DAC chip in fig. 11 represents D9, i.e., bit 9 of the logic control input bit, pin 2 represents D8, i.e., bit 8 of the logic control input bit, pin 3 represents D7, i.e., bit 7 of the logic control input bit, pin 4 represents D6, i.e., bit 6 of the logic control input bit, pin 5 represents D5, i.e., bit 5 of the logic control input bit, pin 6 represents D4, i.e., bit 4 of the logic control input bit, pin 7 represents D3, i.e., bit 3 of the logic control input bit, pin 8 represents D2, i.e., bit 2 of the logic control input bit, pin 9 represents D1, i.e., bit 1 of the logic control input bit, pin 10 represents D0, that is, the 0 th bit of the logic control input bit, pin 11 represents no connection NC-11, pin 12 represents no connection NC-12, pin 13 represents no connection NC-13, pin 14 represents no connection NC-14, pin 15 represents chip SLEEP control SLEEP, pin 16 represents chip internal "ground reference" EXTLO, pin 17 represents external reference input EXTIO, pin 18 represents full-scale output current bias BIASJ, pin 19 represents chip internal decoupling COMP1, pin 20 represents chip analog "ground" AGND, pin 21 represents DAC output port 2IOUT2, pin 22 represents DAC output port 1IOUT1, pin 23 represents chip internal decoupling COMP2, pin 24 represents chip analog power supply input AVDD, pin 25 represents timing MODE selection MODE, pin 26 represents chip digital "ground", pin 27 represents chip digital power supply input, and pin 28 represents DVDD.

Pin 1 of the low noise operational amplifier chip represents no connection NC1, pin 2 represents an inverting terminal input-IN, pin 3 represents a non-inverting terminal input, namely + IN, pin 4 represents a chip power supply-, namely V-, pin 5 represents no connection NC5, pin 6 represents a low noise amplifier output OUT, pin 7 represents a chip power supply +, namely V +, and pin 8 represents no connection NC8.

Likewise, the second voltage is determined in particular by:

c1, performing analog-to-digital conversion on the second channel ultrasonic signal by using a second initial voltage to obtain a second test value;

and C2, adjusting the second initial voltage until the difference value between the second test value and the second preset digital signal is within a preset threshold range, and obtaining a second voltage.

The specific execution process of determining the second voltage may refer to the execution process of determining the first voltage, and is not described herein again.

The final first voltage and the final second voltage are determined by adjusting the first initial voltage and the second initial voltage, so that the signals can be more accurately sampled based on the final first voltage and the final second voltage, and more accurate digital signals can be obtained.

3. Calibrating a first preset digital signal and a first test value, and calibrating a second preset digital signal and a second test value

After determining a first preset digital signal, a second preset digital signal, a first voltage and a second voltage, and obtaining a first test value and a second test value by using the first voltage and the second voltage, if the first test value is greater than the first preset digital signal, increasing a first initial voltage; if the first test value is smaller than the first preset digital signal, the first initial voltage is reduced.

Similarly, if the second test value is greater than the second preset digital signal, the second initial voltage is increased; and if the second test value is smaller than the second preset digital signal, reducing the second initial voltage.

The first initial voltage and the second initial voltage are adjusted more accurately by comparing the first preset digital signal with a first test value determined according to the first initial voltage and comparing the second preset digital signal with a second test value determined according to the second initial voltage, and the more accurate first voltage and second voltage are finally obtained.

In an embodiment of the present application, the first initial voltage is increased or decreased by:

increasing a first initial voltage by increasing a first preset logic control word bit by bit; the first initial voltage is reduced by reducing the first preset logic control word bit by bit.

For example, the first preset logic control word corresponding to the current first initial voltage is 0000001000, if the current first initial voltage needs to be increased, the first preset logic control word is increased bit by bit, that is, the first preset logic control word is changed to 0000010000, and if the current first initial voltage needs to be decreased, the first preset logic control word is decreased bit by bit, that is, the first preset logic control word is changed to 0000000100.

In an embodiment of the present application, the second initial voltage is increased or decreased by:

increasing a second initial voltage by increasing a second preset logic control word bit by bit; the second initial voltage is decreased by decreasing the second preset logic control word bit by bit.

The first preset logic control word or the second preset logic control word is accurately adjusted by adopting a method of increasing or decreasing the first preset logic control word or the second preset logic control word bit by bit, so that the first initial voltage and the second initial voltage are more accurately adjusted, and the more accurate first voltage and second voltage are finally obtained.

In an embodiment of the application, the first initial voltage may be adjusted by using a bisection method, and the second initial voltage may be adjusted by using a bisection method.

For example, assuming that the first preset logic control word may be any one of 0000, 0001, 0010, 0100, and 1000, the logic control word is divided into two parts, the first part is 0000, 0001, and 0010, and the second part is 0100 and 1000, when the first test value and the first preset digital signal size are determined for the first time, a maximum or minimum control word may be determined from the first part or the second part as the first preset logic control word, the first initial voltage is generated, and the first test value is generated based on the first initial voltage for adjustment. Taking the example of determining the maximum control word from the first part as the first preset logic control word, that is, 0010 is used as the first preset logic control word, and if the first preset digital signal is smaller than the first test value and the first preset logic control word needs to be increased, the control word is continuously selected from the second part to generate the corresponding first preset digital signal and compare the first preset digital signal with the first test value. If the first preset digital signal is greater than the first test value and the first preset logic control word needs to be reduced, the control word is continuously selected from the first part to generate a corresponding first preset digital signal and compare the first preset digital signal with the first test value. And circularly comparing according to the process to obtain a first initial voltage and a second initial voltage which are finally adjusted.

For example, a logic control word corresponding to the initial voltage a is selected as a first preset logic control word, a first initial voltage is generated according to the logic control word corresponding to the initial voltage a, a first test value is generated based on the first initial voltage, if the first test value is smaller than a first preset digital signal at the moment, it is determined that the input voltage needs to be increased, the logic control word corresponding to the initial voltage a is adjusted to a logic control word corresponding to the voltage B, the first initial voltage is adjusted by using the logic control word corresponding to the voltage B, a first test value is generated based on the adjusted first initial voltage, if the first test value is larger than the first preset digital signal at the moment, it is determined that the input voltage needs to be decreased, and therefore, a reasonable voltage should be between the initial voltage a and the voltage B, and then a logic control word corresponding to a voltage C between the initial voltage a and the voltage B can be selected to control the input voltage.

And continuously adjusting the first initial voltage by using the logic control word corresponding to the voltage C, generating a first test value based on the adjusted first initial voltage, determining that the input voltage needs to be increased if the first test value is smaller than a first preset digital signal, and indicating that the expected voltage is between the voltage C and the voltage B, so that a voltage D can be found between the voltage C and the voltage B, and if the input voltage needs to be decreased again, the expected voltage is between the voltage C and the voltage D, so as to gradually reduce the voltage value range and obtain a reasonable voltage.

By adjusting the first initial voltage and the second initial voltage by using the bisection method, the calculation amount can be reduced, and the searching speed can be increased.

As shown in fig. 12, a flow chart of a first voltage calibration is shown, comprising the steps of:

s1201, performing analog-to-digital conversion on the first channel ultrasonic signal by using a first initial voltage to obtain a first test value; and determining a first preset logic control word corresponding to the first initial voltage.

S1202, determining whether a difference between the first test value and the first preset digital signal is smaller than a preset threshold, if not, performing step S1203, and if so, performing step S1204.

S1203, increasing the first preset logic control word bit by bit to increase the first initial voltage.

S1204, the first preset logic control word is reduced bit by bit to reduce the first initial voltage.

And S1205, storing a first preset logic control word corresponding to the final first voltage.

Fig. 13 shows a schematic structural diagram of an ultrasonic diagnostic apparatus 1300 according to an embodiment of the present application. The following describes an embodiment of the ultrasonic diagnostic apparatus 1300. It should be understood that the ultrasonic diagnostic apparatus 1300 shown in fig. 13 is only an example, and the ultrasonic diagnostic apparatus 1300 may have more or less components than those shown in fig. 13, may combine two or more components, or may have a different component configuration. The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

A hardware configuration block diagram of an ultrasonic diagnostic apparatus 1300 according to an exemplary embodiment is exemplarily shown in fig. 13.

As shown in fig. 13, the ultrasonic diagnostic apparatus 1300 may include: a processor 110, a memory 120, a display unit 130 and a probe 140, and the above-mentioned ultrasonic signal sampling circuit 150; wherein the content of the first and second substances,

a probe 140 for emitting an ultrasonic beam and receiving an ultrasonic echo signal;

a display unit 130 for displaying an ultrasound image;

the memory 120 is configured to store data required for ultrasound imaging, which may include software programs, application interface data, and the like;

the processor 110 is configured to send the digital signals to the upper computer 106 and receive the ultrasonic images sent by the upper computer 106; the digital signal is obtained by the ultrasonic signal sampling circuit 150 described above.

Fig. 14 is a schematic diagram of an application principle according to an embodiment of the present application. The part can be realized by a part of modules or functional components of the ultrasonic diagnostic apparatus shown in fig. 13, and the following description will be made only for main components, and other components, such as a memory, a controller, a control circuit, etc., will not be described herein again.

As shown in fig. 14, a user interface 310, a display unit 320 for displaying the user interface, and a processor 330 may be included in the application environment.

The display unit 320 may include a display panel 321, a backlight assembly 322. Wherein the display panel 321 is configured to display the ultrasound image, the backlight assembly 322 is located at the back of the display panel 321, and the backlight assembly 322 may include a plurality of backlight partitions (not shown), each of which may emit light to illuminate the display panel 321.

The processor 330 may be configured to control the backlight brightness of the various backlight zones in the backlight assembly 322, as well as to control the probe to transmit the wide beam and receive the echo signals.

The processor 330 may include a focusing processing unit 331, a beam synthesizing unit 332, and a spectrum generating unit 333, among others. Wherein the focus processing unit 331 may be configured to perform a focus process on the current frame ultrasound image, the focus process including: taking the designated position in the current frame ultrasonic image as the focusing position of the wide beam, and transmitting the wide beam to the target detection region according to the transmission coefficient of the designated position; and receiving echo signals fed back at the specified position. The beam synthesis unit 332 is configured to perform beam synthesis on the echo signals fed back from the specified position after the focusing process is completed on the target detection region, resulting in scanning information. The spectrum generation unit 333 is configured to perform doppler imaging based on the scan information of each specified position.

As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

In an exemplary embodiment, the aspects of an ultrasound signal sampling method provided herein may also be embodied in the form of a program product comprising program code for causing a computer device to perform the steps of the ultrasound signal sampling method according to various exemplary embodiments of the present application described above in this specification when the program product is run on the computer device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The program product for ultrasound signal sampling of embodiments of the present application may employ a portable compact disk read only memory (CD-ROM) and include program code and may be run on an ultrasound device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's ultrasound device, partly on the user's device, as a stand-alone software package, partly on the user's ultrasound diagnostic apparatus, partly on the remote ultrasound diagnostic apparatus, or entirely on the remote ultrasound diagnostic apparatus or server. In the case of remote ultrasound diagnostic instruments, the remote ultrasound diagnostic instruments may be connected to the user ultrasound diagnostic instrument through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to external ultrasound diagnostic instruments (e.g., through the internet using an internet service provider).

It should be noted that although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, the features and functions of two or more of the units described above may be embodied in one unit, according to embodiments of the application. Conversely, the features and functions of one unit described above may be further divided into embodiments by a plurality of units.

Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable image scaling device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable ultrasound signal sampling device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable ultrasound signal sampling apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable ultrasound signal sampling apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. An ultrasonic signal sampling circuit, comprising: the device comprises a signal demodulation module, a first analog-to-digital conversion ADC sampling module, a second analog-to-digital conversion ADC sampling module and a voltage regulation module;

2. The circuit of claim 1, wherein the voltage regulation module comprises: a first voltage regulating unit and a second voltage regulating unit;

and the second voltage regulating unit is used for outputting the adjustable second voltage to the second ADC sampling module.

3. The circuit of claim 2, wherein the first voltage regulating unit comprises: the first digital-to-analog conversion DAC unit and the first low-noise operational amplifier unit;

the second voltage adjusting unit includes: the second digital-to-analog conversion DAC unit and the second low-noise operational amplifier unit;

4. The circuit of claim 3, wherein the first DAC unit is a current-mode DAC chip or a voltage-mode DAC chip, and wherein the second DAC unit is a current-mode DAC chip or a voltage-mode DAC chip.

5. The circuit of claim 1, further comprising a memory for storing a first preset logic control word corresponding to the first voltage and a second preset logic control word corresponding to the second voltage;

6. A method of ultrasound signal sampling, the method comprising:

performing signal demodulation on the ultrasonic echo signals to obtain orthogonal first channel ultrasonic signals and second channel ultrasonic signals;

7. The method of claim 6,

determining the first voltage, including:

determining the second voltage, comprising:

8. The method of claim 7, wherein said adjusting said first initial voltage comprises:

the adjusting the second initial voltage includes:

9. The method of claim 8, wherein the first initial voltage is increased or decreased by:

increasing or decreasing the second initial voltage by:

10. An ultrasonic diagnostic apparatus characterized by comprising: a probe, a display unit, a processor and an ultrasound signal sampling circuit as claimed in any one of claims 1 to 5;

the display unit is used for displaying the ultrasonic image.