CN210514457U - Digital double-channel frequency response analyzer - Google Patents
Digital double-channel frequency response analyzer Download PDFInfo
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- CN210514457U CN210514457U CN201920817221.6U CN201920817221U CN210514457U CN 210514457 U CN210514457 U CN 210514457U CN 201920817221 U CN201920817221 U CN 201920817221U CN 210514457 U CN210514457 U CN 210514457U
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Abstract
The utility model discloses a digital binary channels frequency response analysis appearance belongs to test instrument technical field. The utility model discloses a digital signal processor, RS232 interface, serial ports touch-sensitive screen, frequency sweep signal source, amplitude control, input amplification/decay, AD synchronous converter, power. The serial port touch screen is connected with the digital signal processor through an RS232 interface, the sweep frequency signal source is connected with the digital signal processor, the amplitude control and the A/D synchronous converter, the amplitude control is connected with the digital signal processor and the A/D synchronous converter, the input amplification/attenuation and the A/D synchronous converter are connected with the digital signal processor, the A/D synchronous converter is connected with the digital signal processor, and the power supply is connected with each module needing direct-current voltage. The utility model discloses a tester simple structure, the cost of manufacture is low, and convenient operation is particularly suitable for using in teaching experiment.
Description
Technical Field
The utility model relates to a frequency response testing arrangement belongs to test instrument technical field, especially relates to a digital binary channels frequency response analysis appearance.
Background
The frequency response analyzer is an important instrument for testing the frequency characteristic of a circuit system, and can test the amplitude gain and phase angle gain of the circuit system along with the change of frequency. However, the conventional frequency response analyzer has the problems of large volume, high price, low testing precision, inconvenient use and the like caused by complex circuit structure, low digitalization degree and the like. Especially in the teaching experiment, because traditional frequency response analysis appearance can not show multiunit test data and the characteristic curve that constitutes by test data, the student need record a large amount of experimental data and draw characteristic curve, and the teaching experiment is very inconvenient.
Disclosure of Invention
To solve the above problems, the present invention provides a digital dual-channel frequency response analyzer.
The technical scheme of the utility model: a digital dual-channel frequency response analyzer comprises a digital signal processor 1, an RS232 interface 2, a sweep frequency signal source 4, an amplitude control 5, an input amplification/attenuation 6 and a power supply 8, and further comprises a serial port touch screen 3 and an A/D synchronous converter 7; the serial port touch screen 3 is connected with the digital signal processor 1 through an RS232 interface 2 for data exchange; the digital control input end of the frequency sweeping signal source 4 is connected with an I/O pin of the digital signal processor 1, the digital signal processor 1 controls the frequency sweeping signal source 4 to generate sine and cosine signals, the sine signal output end of the frequency sweeping signal source 4 is simultaneously connected with the analog signal input end of the amplitude control 5 and the sine signal input end of the A/D synchronous converter 7, and the cosine signal output end of the frequency sweeping signal source 4 is connected with the cosine signal input end of the A/D synchronous converter 7; the digital control input end of the amplitude control 5 is connected with a data bus of the digital signal processor 1, the amplitude of a sinusoidal excitation signal output by the amplitude control 5 is controlled by the digital signal processor 1, and the sinusoidal excitation signal is applied to a system to be tested; the two input ends of the input amplification/attenuation 6 are used for inputting two response signals of a tested system, the two amplified or attenuated response signals are output to two analog signal input ends of an A/D synchronous converter 7, the input amplification/attenuation 6 is also connected with the digital signal processor 1, and the digital signal processor 1 controls the amplification factor or the attenuation factor; the A/D synchronous converter 7 is connected with the digital signal processor 1 and is controlled by the digital signal processor 1, and the A/D synchronous converter 7 synchronously converts input sine signals, input cosine signals, amplified or attenuated response signals input by two analog signal input ends into digital values and transmits the digital values to the digital signal processor 1; the output of the power supply 8 is connected to a corresponding circuit requiring a dc voltage.
The utility model has the advantages that: a digital dual-channel frequency response analyzer is provided, an A/D synchronous converter is adopted to synchronously convert sine and cosine signals output by a sweep frequency signal source and a response signal of a tested system after input amplification/attenuation, and converted numerical values are sent to a digital signal processor to carry out numerical value calculation according to a sine correlation analysis principle, so that the test precision is improved; the serial port touch screen is used as a man-machine interface device, test environment parameters such as amplitude, frequency sweep mode and the like of an excitation signal can be set through an interface on the serial port touch screen, a plurality of groups of data can be displayed in a table form, a characteristic curve formed by the test data can be displayed, and the data can also be sent to a PC (personal computer) for further processing; the tester has simple structure, low cost and convenient use, and is particularly suitable for teaching experiments.
Drawings
Fig. 1 is a general circuit block diagram of the present invention.
Fig. 2 is a block diagram of the digital signal processor of the present invention.
Fig. 3 is a block diagram of the frequency-sweep signal source of the present invention.
Fig. 4 is a block diagram of the amplitude control of the present invention.
Fig. 5 is an input amplification/attenuation block diagram of the present invention.
Fig. 6 is a schematic diagram of an a/D synchronous converter according to the present invention.
Fig. 7 is a block diagram of a power supply of the present invention.
Fig. 8 is the interface switching relationship on the serial port touch screen of the present invention.
Detailed Description
The invention will be further explained with reference to the drawings and the specific embodiments.
Example 1: as shown in fig. 1, a digital dual-channel frequency response analyzer includes a digital signal processor 1, an RS232 interface 2, a sweep frequency signal source 4, an amplitude control 5, an input amplification/attenuation 6, a power supply 8, a serial port touch screen 3, and an a/D synchronous converter 7; the serial port touch screen 3 is connected with the digital signal processor 1 through an RS232 interface 2 for data exchange; the digital control input end of the frequency sweeping signal source 4 is connected with an I/O pin of the digital signal processor 1, the digital signal processor 1 controls the frequency sweeping signal source 4 to generate sine and cosine signals, the sine signal output end of the frequency sweeping signal source 4 is simultaneously connected with the analog signal input end of the amplitude control 5 and the sine signal input end of the A/D synchronous converter 7, and the cosine signal output end of the frequency sweeping signal source 4 is connected with the cosine signal input end of the A/D synchronous converter 7; the digital control input end of the amplitude control 5 is connected with a data bus of the digital signal processor 1, the amplitude of a sinusoidal excitation signal output by the amplitude control 5 is controlled by the digital signal processor 1, and the sinusoidal excitation signal is applied to a system to be tested; the two input ends of the input amplification/attenuation 6 are used for inputting two response signals of a tested system, the two amplified or attenuated response signals are output to two analog signal input ends of an A/D synchronous converter 7, the input amplification/attenuation 6 is also connected with the digital signal processor 1, and the digital signal processor 1 controls the amplification factor or the attenuation factor; the A/D synchronous converter 7 is connected with the digital signal processor 1 and is controlled by the digital signal processor 1, and the A/D synchronous converter 7 synchronously converts input sine signals, input cosine signals, amplified or attenuated response signals input by two analog signal input ends into digital values and transmits the digital values to the digital signal processor 1; the output of the power supply 8 is connected to a corresponding circuit requiring a dc voltage.
The test procedure was: the analyzer outputs a sine excitation signal with certain amplitude and frequency according to parameters such as amplitude, frequency and the like of the excitation signal input in the test interface of the serial port touch screen 3;
the digital signal processor 1 controls the A/D synchronous converter 7 to synchronously convert sine and cosine signals output by the sweep frequency signal source 4 and a response signal of a tested system after being amplified or attenuated into digital values;
the digital signal processor 1 calculates the digital value obtained from the A/D synchronous converter 7 according to the sine correlation analysis principle to obtain the amplitude gain and the phase gain under the current frequency and stores the amplitude gain and the phase gain;
repeating the step 2 and the step 3 according to a measurement mode set by a test interface of the serial port touch screen 3 to obtain amplitude gains and phase gains of all frequency points;
according to the requirement, amplitude gain and phase gain under all frequency points and a frequency characteristic curve formed by all test data are displayed by a serial port touch screen 3, or the data are transmitted to a PC by a digital signal processor 1 through an RS2322 interface 2 to complete further processing of the data.
Example 2: the detailed structure of each part will be described in the present embodiment, specifically as follows.
As shown in fig. 2, the digital signal processor 1 includes a DSP chip 11, an address decoder 12, a RAM memory 13, and a program downloading port 14, where address pins of the DSP chip 11 are connected to address pins of the RAM memory 13 through the address decoder 12, data pins of the DSP chip 11 are connected to data pins of the RAM memory 13, and the program downloading port 14 is connected to program downloading pins of the DSP chip 11; meanwhile, the DSP chip 11 is also respectively connected with the RS232 interface 2, the sweep frequency signal source 4, the amplitude control 5, the input amplification/attenuation 6 and the A/D synchronous converter 7. The DSP chip 11 IS a TMS320F2812 chip, the address decoder 12 IS an SN74HC138D chip, and the RAM memory 13 IS implemented by 4 IS61LV25616AL chips.
The RS232 interface 2 is formed by a MAX3232CSE chip and is used for converting a +3.3V level output by the serial port of the digital signal processor 1 into an RS232 level so as to be connected with the serial port touch screen 3; meanwhile, the invention can also be connected with a PC through an RS232 interface 2 to transmit the test data to the PC for processing.
As shown in fig. 3, the swept-frequency signal source 4 includes an active crystal oscillator 47, a DDS141, a DDS242, a first low-pass filter 43, a second low-pass filter 44, a first waveform transformation 45, and a second waveThe output end of the active crystal oscillator 47 is simultaneously connected with clock input pins of a DDS141 and a DDS242, the output of the DDS141 is connected with the input of a first waveform transformation 45 through a first low-pass filter 43, the output of the DDS242 is connected with the input of a second waveform transformation 46 through a second low-pass filter 44, the first waveform transformation 45 outputs a sine signal sin ω t to an A/D synchronous converter 7 and an amplitude control 5, the second waveform transformation 46 outputs a cosine signal cos ω t to the A/D synchronous converter 7, and the DDS141 and the DDS242 are simultaneously controlled by the digital signal processor 1; both DDS141 and DDS242 adopt AD9850 type chips, the AD9850 chip has 32 bit frequency control bits and 5 bit phase control bits, can generate sine or cosine signals with different frequencies through digital control, and outputs the frequency fOUT＝(ΔPhase×CLKIN)/232Where Δ Phase is the frequency control value and CLKIN is the clock frequency. Here a serial input, 5V supply, 25Mhz clock frequency is used, with a frequency resolution of 0.00582 Hz. The phase of the AD9850 chip of the DDS141 is set to 0 degrees to generate a sine signal, and the phase of the DDS242 is set to 90 degrees to generate a cosine signal. The first waveform transformation 45 and the second waveform transformation 46 are both formed by integrated operational amplifier ADA4000-1, and have the functions of transforming 0.5+0.5sin ω t output by the DDS141 into sin ω t and transforming 0.5+0.5cos ω t output by the DDS242 into cos ω t.
As shown in fig. 4, the amplitude control unit 5 includes a D/a converter 51, a power amplifier 52, an amplitude amplifier 53, wherein the output of the amplitude amplifier 53 is connected to the reference input of the D/a converter 51, the input of the amplitude amplifier 53 is the sine signal sin ω t output by the first waveform transformation 45, the data input of the D/a converter 51 is input by the DSP chip 11 with a digital value, the output of the D/a converter 51 is connected to the input of the power amplifier 52, and the power amplifier 52 outputs the sine excitation signal to be applied to the system under test; the D/A converter 51 is composed of a DAC0832 type chip and an integrated operational amplifier chip ADA4000-1, in which case the D/A converter 51 is used as a multiplier and outputs Vout＝Vref×D/28In which V isrefThe amplitude of the sinusoidal signal outputted from the amplitude amplifier 53 is amplified, and D is a digital value, so that the DSP chip 11 controls the value of D to control the amplitude of the sinusoidal signal outputted from the D/a converter 51. The power amplifier is formed by an LM675 type chip and has the function of improving the load capacity of an excitation signal source. Amplitude amplification 53 with integrationThe operational amplifier chip ADA 4000-1.
As shown in fig. 5, the input amplifier/attenuator 6 is a dual-channel amplifier or attenuator circuit, and includes a first BNC interface 61, a second BNC interface 62, a first buffer circuit 63, a second buffer circuit 64, a first attenuator circuit 65, a second attenuator circuit 66, a first digitally controlled gain amplifier 67, and a second digitally controlled gain amplifier 68, where the first BNC interface 61 is connected to an input end of the first buffer circuit 63, an output end of the first buffer circuit 63 is connected to an input end of the first attenuator circuit 65, an output end of the first attenuator circuit 65 is connected to an input end of the first digitally controlled gain amplifier 67, the second BNC interface 62 is connected to an input end of the second buffer circuit 64, an output end of the second buffer circuit 64 is connected to an input end of the second attenuator circuit 66, and an output end of the second attenuator circuit 66 is connected to an input end of the second digitally controlled gain amplifier 68; the first BNC interface 61 and the second BNC interface 62 are input ends of 2 tested system response signals, the attenuation multiples of the first attenuation circuit 65 and the second attenuation circuit 66 and the gains of the first numerical control gain amplifier 67 and the second numerical control gain amplifier 68 are controlled by the DSP chip 11, and signals output by the two channels are connected to the input end of the A/D synchronous converter 7; the first buffer circuit 63 and the second buffer circuit 64 are realized by adopting ADA4000-1 chips to form voltage followers, the first attenuation circuit 65 and the second attenuation circuit 66 are realized by adopting digital potentiometers, and the first digital control gain amplifier 67 and the second digital control gain amplifier 68 are both realized by adopting AD526 chips; the input amplification/attenuation 6 serves to amplitude attenuate or amplify the measured response signal to accommodate the requirements of the a/D conversion.
As shown in fig. 6, the a/D synchronous converter (7) is an analog-to-digital converter for synchronously converting 4 analog signals into digital signals, and includes an address decoder chip SN74HC138, a level conversion chip SN74ALVC164245, an analog-to-digital conversion module a/DC1(71), an analog-to-digital conversion module a/DC2(72), an analog-to-digital conversion module a/DC3(73), an analog-to-digital conversion module a/DC4(74), a capacitor C1, a capacitor C7, a capacitor C8, and a resistor R1;
the internal structures of the analog-to-digital conversion module A/DC1(71), the analog-to-digital conversion module A/DC2(72), the analog-to-digital conversion module A/DC3(73) and the analog-to-digital conversion module A/DC4(74) are the same, and each module has the same internal structureThe internal part of the circuit comprises an analog-to-digital conversion chip AD7892-1, a reference voltage chip AD780, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6; MODE end and of the chip AD7892-1
The end is connected with a digital power supply +5V (D), the VDD end is connected with an analog power supply +5V (A), the capacitor C2 is connected with the capacitor C3 IN parallel, the positive end is connected with the analog power supply +5V (A), the negative end is connected with an analog ground AGND, the AGND end is connected with the analog ground AGND, the DGND end is connected with a digital ground DGND, and a reference voltage output/input end REF OUT/REF IN is connected with an output end OUT of a reference voltage chip AD 780; of chip AD7892-1
Analog-to-digital conversion starting control end with end as module
Chip selection input end with terminal as module
Read data control terminal with module as terminal
The VIN of the pin 3 and the VIN of the pin 4 are connected together to serve as an analog signal input end VIN of the module, and the data output ends DB0, DB2, DB3, DB4, DB5, DB6, DB7, DB8, DB9, DB10 and DB11 form a data bus serving as an output data bus of the module; the IN end of the chip AD780 is connected with an analog power supply +5V (A), and is connected with an analog ground AGND through a capacitor C4, the TEMPTRIM end is connected with the analog ground AGND through a capacitor C5, the GND end is connected with the analog ground AGND, the output end OUT is connected with a reference voltage output/input end REF OUT/REF IN of the analog-to-digital conversion chip AD7892-1, and is connected with the analog ground AGND through a capacitor C6; the address input end A, the address input end B and the address input end C of the chip SN74HC138 are connected with an external address bus XA [2..0 ] of the DSP chip (11)]Output enable terminal
A chip selection signal output end connected with the DSP chip (11)
The output enable end OE1 is connected with a digital power supply +5V (D), and the output enable end OE1 is connected with a digital power supply +5V (D)
A digital ground DGND connected to ground terminal GND, and a chip select signal output terminal
Chip selection signal output terminal
Chip selection signal output terminal
Chip selection signal output terminal
Respectively connected to chip selection input ends of the analog-to-digital conversion module A/DC1(71), the analog-to-digital conversion module A/DC2(72), the analog-to-digital conversion module A/DC3(73) and the analog-to-digital conversion module A/DC4(4)
Analog-to-digital conversion start control terminals of four analog-to-digital conversion modules A/DC1(71), A/DC2(72), A/DC3(73) and A/DC4(4)
Connected together and then connected with GPIO pin of DSP chip (11), and read data control terminal of the four
Are connected together and then are connected with an external read data pin of the DSP chip (11)
The analog signal input ends VIN of the four are respectively connected with the sweep frequency signal source (4)Sine signal output terminal, cosine signal output terminal, channel 1 output terminal y1(t) of input amplification/attenuation (6), channel 2 output terminal y2(t) are connected together, four output data buses are connected together, four data output terminals DB0, DB2, DB3, DB4, DB5, DB6, DB7, DB8, DB9, DB10 and DB11 are respectively connected with the terminals 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7, 1B8, 2B1, 2B2, 2B3 and 2B4 of the chip SN74ALVC164245, and the analog-to-digital conversion end signal terminal of the analog-to-digital conversion module ADC1(71) is connected with the terminals 1B1, 1B2 and 2B4, and the analog-to-digital conversion end signal terminal is connected
Is connected with the 2B5 end of the chip SN74ALVC 164245; the 1DIR, 2B6, 2B7, 2B8 and all GND terminals of the chip SN74ALVC164245 are connected with a digital DGND, all VCCB terminals are connected with a digital power supply +5V (D), and are connected with the digital DGND through a capacitor C7, and data buses formed by the 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7, 1A8, 2A1, 2A2, 2A3 and 2A4 ends and an XDB [11..0 ] 0 external data bus XDB of the DSP chip (11)]The connection is carried out by connecting the two parts,
terminal and
the ends of the voltage signal are connected together and then connected with a GPIO pin of the DSP chip (11), and simultaneously connected with a power supply +3.3V through a resistor R1, the end 2A5 is connected with an external interrupt request end XINT of the DSP chip (11), all VCCA ends are connected with the power supply +3.3V, and are connected with a digital DGND through a capacitor C8.
As shown in fig. 7, the power supply 8 includes an ac power plug 81, a switching power module 82, and a DC-DC module 83, where the ac power plug 81 is connected to an ac input terminal of the switching power module 82, a +5V output terminal of the switching power module 82 is connected to an input terminal of the DC-DC module 83, the ac power plug 81 is connected to an ac 220V power supply, +15V, -15V, and +5V output terminals of the switching power module 82 are connected to power supply terminals of other circuit modules that require corresponding DC voltages, and +3.3V and +1.8V output terminals of the DC-DC module 83 are respectively connected to power supply terminals of +3.3V and +1.8V of the DSP chip 11; the switching power supply module 82 is realized by adopting a HAW25-220T05-15IB9 type module, and the DC-DC module 83 is realized by adopting a TPS767D318 type chip.
The serial port touch screen 3 is a human-computer interface device of the invention, is a liquid crystal screen with serial port control, has a touch function, is a serial port true color display terminal integrating TFT (thin film field effect transistor) display drive, picture word stock storage, GUI (graphical user interface) operation, RTC (real time clock) display and various configuration controls, is suitable for DSP and other systems without display drive, and the like, and the digital signal processor can realize the display of texts, pictures, curves and the like only by sending instructions to the serial port touch screen through a serial port, and can also input commands or data through the serial port screen interface and send the commands or data to the digital signal processor through the serial port, wherein the serial port touch screen is an 8-inch DC80600B080 type serial port touch screen.
As shown in fig. 8, the serial port touch screen 3 can display a start-up interface, a test interface, a data interface, a curve interface, a test in-progress interface, an instruction interface 1, an instruction interface 2, and an instruction interface 3, where the start-up interface can be switched to the test interface and the instruction interface 1, the test interface can be switched to the start-up interface, the test in-progress interface, the data interface, and the curve interface, the test interface can be switched to the test interface, the data interface can be switched to the curve interface, the instruction interface 1 can be switched to the start-up interface and the instruction interface 2, the instruction interface 2 can be switched to the instruction interface 1 and the instruction interface 3, the instruction interface 3 can be switched to the instruction interface 2, the test interface, the data interface, and the instruction interface, The curve interface is the main 3 interfaces. The interfaces are illustrated below:
(1) starting up an interface: the interface which is firstly accessed after the power switch is turned on can be manually or automatically accessed to other interfaces according to the requirement.
(2) Testing an interface: the device is used for setting testing environment parameters, and comprises generator setting, measurement mode setting, analyzer output and measurement delay. Wherein:
a) the generator can set the amplitude of the excitation signal and the frequency in the manual measurement mode, the amplitude range is 0-5V, and the frequency range is 0.1-20000 Hz.
b)“The measurement mode setting comprises a frequency sweeping mode, a measurement mode, a maximum frequency, a minimum frequency, a linear step length, a logarithmic point number, an integral cycle number (integral period number), channel selection, channel gain 1 and channel gain 2. The "frequency sweep method" includes a logarithmic method (Logar) and a linear method (Line). "logarithmic mode" means that when the measurement mode is single mode or automatic mode, the change of frequency is changed according to the rule that every two times frequency tests several points, namely, the frequency f is fmin·2k/nWherein f isminFor the set minimum frequency, n is the number of points tested in the double frequency multiplication, and k is the test frequency. By "linear manner" is meant that the frequency change is a change according to the law that the next frequency value is the previous one plus a linear step value, i.e. the frequency f ═ fmin+ k · Δ f, where Δ f is a linear step size. The "measurement mode" includes a manual mode (manual), a single mode (single), and an automatic mode (Auto). The manual mode is that the frequency is set once in the generator setting every time a frequency point is tested, and the frequency can be set randomly according to the requirement. The "single mode" means that after the minimum frequency, the maximum frequency and the linear step or the number of logarithmic points are set, the frequency value is increased from the minimum frequency, and the linear step is increased every time a measuring button is pressed or the frequency is changed according to the rule that every 2 times the frequency is tested to a plurality of points until the maximum frequency value. The frequency value in the "automatic mode" varies in the same manner as in the single mode, except that the frequency is automatically increased by pressing the measurement button once. The integral cycle number means that when the amplitude gain and the phase angle gain are calculated according to the sine correlation analysis principle, a plurality of fundamental wave cycles are integrated, and the larger the numerical value is, the stronger the interference suppression capability is. "channel selection" means that either channel 1(CH1), or channel 2(CH2), or channel 2/channel 1(CH2/CH1) can be selected for testing, the first two are single channel test modes and only one input signal is tested, the third is a dual channel mode and two input signals can be tested simultaneously, with the result being that channel 2 is divided by channel 1.
c) The "analyzer output" displays the test result for each frequency value, including the test frequency at that time, the rectangular coordinate form, polar coordinate form, and logarithmic coordinate form of the result value, with the magnitude L in logarithmic coordinate form being 20lgr (db).
d) The measurement delay refers to the time from the output of the excitation signal to the start of sampling data, the test is started only after the output of the system to be tested is stable, and the set delay time is more than or equal to the time required by the stability of the system output.
(3) A data interface: displaying test data of all test frequency points in a form of a table, wherein the test data comprises the frequency and angular frequency of the test frequency points, and the amplitude and phase angle of the frequency characteristic of a tested system, and when the page 1 is not displayed enough, a next page button can be used for switching to pages 2,3, and n for displaying, and simultaneously displaying which channel is tested at the moment, and displaying the measurement date and time; the displayed data may be cleared with a "clear" button or redisplayed with a "show" button.
(4) Interface of the curve: used for displaying the plotted Bode plot of all the test data. The angular frequency, amplitude and phase angle display range can also be set on the display device.
(5) Test in progress interface: and when the analyzer is in the testing process, the prompting interface is used for prompting a user to 'test in progress'.
(6) Instructions interface 1, instructions interface 2, instructions interface 3: to describe how the invention may be used.
The specific test process of the analyzer is as follows:
(1) the analyzer outputs a sinusoidal excitation signal with certain amplitude and frequency according to parameters such as amplitude, frequency and the like of the excitation signal input in the test interface of the serial port touch screen 3;
(2) the digital signal processor 1 controls the A/D synchronous converter 7 to synchronously convert sine and cosine signals output by the sweep frequency signal source 4 and a response signal of a tested system after being amplified or attenuated into digital values;
(3) the digital signal processor 1 calculates the digital value obtained from the A/D synchronous converter 7 according to the sine correlation analysis principle to obtain the amplitude gain and the phase gain under the current frequency and stores the amplitude gain and the phase gain;
(4) repeating the step (2) and the step (3) according to a measurement mode set from a test interface of the serial port touch screen 3 to obtain amplitude gains and phase gains of all frequency points;
(5) according to the requirement, amplitude gain and phase gain under all frequency points and a frequency characteristic curve formed by all test data are displayed by a serial port touch screen 3, or the data are transmitted to a PC through an RS232 interface 2 by a digital signal processor 1 to complete further processing of the data.
In this embodiment, a sinusoidal correlation analysis principle is used to test the frequency characteristics of the system, and the specific process is as follows:
taking a channel test as an example, let an excitation signal input by a system to be tested be X (t) ═ Asin ω t, a steady-state response of the system to be tested be y (t) (including a direct current component, a fundamental wave component, a harmonic component, and random interference), a sine signal generated by a sweep frequency signal source and input to the a/D synchronous converter 7 be sin ω t, a cosine signal be cos ω t, and values of the 3 analog signals after synchronous conversion by the a/D synchronous converter 7 are y (i), X, and b, respectively1(i)、X2(i) (where, i is 1,2,3.. n +1, which is a sampling number, and n is NT/T)sN is the number of the periods of the sine fundamental wave, T is the period of the sine fundamental wave, TsFor the synchronous sampling period of the A/D synchronous converter 7, according to the sine correlation analysis principle and the numerical integration trapezoidal formula, the calculation formula of the homodromous component of the fundamental component in the steady-state response of the system to be tested can be obtained as follows:
the orthogonal component calculation formula of the fundamental component is as follows:
the amplitude of the fundamental component is calculated as:
the phase angle calculation formula of the fundamental component is as follows:
the formula for calculating the frequency characteristic amplitude (amplitude gain) when the angular frequency of the system to be measured is ω is:
the frequency characteristic phase angle (phase angle gain) calculation formula is:
the above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be within the technical scope of the present invention, and any modifications, equivalent replacements, improvements, etc. made according to the technical solution and the inventive concept of the present invention should be included in the scope of the present invention.
Claims (3)
1. A digital dual-channel frequency response analyzer comprises a digital signal processor (1), an RS232 interface (2), a sweep frequency signal source (4), an amplitude control (5), an input amplification/attenuation (6) and a power supply (8), and is characterized by further comprising a serial port touch screen (3) and an A/D synchronous converter (7); the serial port touch screen (3) is connected with the digital signal processor (1) through an RS232 interface (2) to exchange data; the digital control input end of the frequency sweeping signal source (4) is connected with an I/O pin of the digital signal processor (1), the digital signal processor (1) controls the frequency sweeping signal source (4) to generate sine and cosine signals, the sine signal output end of the frequency sweeping signal source (4) is simultaneously connected with the analog signal input end of the amplitude control (5) and the sine signal input end of the A/D synchronous converter (7), and the cosine signal output end of the frequency sweeping signal source (4) is connected with the cosine signal input end of the A/D synchronous converter (7); the digital control input end of the amplitude control (5) is connected with a data bus of the digital signal processor (1), the amplitude of a sine excitation signal output by the amplitude control (5) is controlled by the digital signal processor (1), and the sine excitation signal is applied to a system to be tested; the two input ends of the input amplification/attenuation (6) are used for inputting two response signals of a tested system, the two amplified or attenuated response signals are output to the two analog signal input ends of the A/D synchronous converter (7), the input amplification/attenuation (6) is also connected with the digital signal processor (1), and the digital signal processor (1) controls the amplification factor or the attenuation factor; the A/D synchronous converter (7) is connected with the digital signal processor (1) and is controlled by the digital signal processor (1), and the A/D synchronous converter (7) synchronously converts an input sine signal, a cosine signal and an amplified or attenuated response signal input by two analog signal input ends into a digital value and transmits the digital value to the digital signal processor (1); the output of the power supply (8) is connected to a corresponding circuit requiring a direct voltage.
2. The digital dual-channel frequency response analyzer as claimed in claim 1, wherein the serial port touch screen (3) is a TFT color screen with touch function, and is provided with a test interface, a data interface and a curve interface;
the test interface comprises a generator setting, a measurement delay, a measurement mode setting and an analyzer output, wherein the generator setting can set the amplitude and the frequency of an excitation signal, the measurement delay can set the time required by the stability of the output of a system to be tested from the application of the excitation signal, the measurement mode setting can set a test mode of the analyzer during testing, and the analyzer outputs result data capable of displaying single measurement;
the data interface can display the test data of all the test frequency points, including the frequency value, angular frequency value, amplitude value and test channel of the tested frequency points;
the curve interface can display curves formed by all test data, and can also set angular frequency, amplitude and phase angle display ranges.
3. The digital dual-channel frequency response analyzer as claimed in claim 1, wherein the a/D synchronous converter (7) is an analog-to-digital converter for synchronously converting 4 analog signals into digital signals, and comprises an address decoder chip SN74HC138, a level conversion chip SN74ALVC164245, an analog-to-digital conversion module a/DC1(71), an analog-to-digital conversion module a/DC2(72), an analog-to-digital conversion module a/DC3(73), an analog-to-digital conversion module a/DC4(74), a capacitor C1, a capacitor C7, a capacitor C8, a resistor R1;
the analog-to-digital conversion module A/DC1(71), the analog-to-digital conversion module A/DC2(72), the analog-to-digital conversion module A/DC3(73) and the analog-to-digital conversion module A/DC4(74) have the same internal structure, and each module internally comprises an analog-to-digital conversion chip AD7892-1, a reference voltage chip AD780, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6;
MODE end and of the chip AD7892-1
The end is connected with a digital power supply +5V (D), the VDD end is connected with an analog power supply +5V (A), the capacitor C2 is connected with the capacitor C3 IN parallel, the positive end is connected with the analog power supply +5V (A), the negative end is connected with an analog ground AGND, the AGND end is connected with the analog ground AGND, the DGND end is connected with a digital ground DGND, and a reference voltage output/input end REF OUT/REF IN is connected with an output end OUT of a reference voltage chip AD 780; of chip AD7892-1
Analog-to-digital conversion starting control end with end as module
Chip selection input end with terminal as module
Read data control terminal with module as terminal
VIN of pin 3 and VIN of pin 4 are connected together as a dieThe analog signal input end VIN and the data output ends DB0, DB2, DB3, DB4, DB5, DB6, DB7, DB8, DB9, DB10 and DB11 of the block form a data bus as an output data bus of the module;
the IN end of the chip AD780 is connected with an analog power supply +5V (A), and is connected with an analog ground AGND through a capacitor C4, the TEMPTRIM end is connected with the analog ground AGND through a capacitor C5, the GND end is connected with the analog ground AGND, the output end OUT is connected with a reference voltage output/input end REF OUT/REF IN of the analog-to-digital conversion chip AD7892-1, and is connected with the analog ground AGND through a capacitor C6;
the address input end A, the address input end B and the address input end C of the chip SN74HC138 are connected with an external address bus XA [2..0 ] of the DSP chip (11)]Output enable terminal
A chip selection signal output end connected with the DSP chip (11)
The output enable end OE1 is connected with a digital power supply +5V (D), and the output enable end OE1 is connected with a digital power supply +5V (D)
A digital ground DGND connected to ground terminal GND, and a chip select signal output terminal
Chip selection signal output terminal
Chip selection signal output terminal
Chip selection signal output terminal
Respectively connected to chip selection input terminals of the analog-to-digital conversion module A/DC1(71), the analog-to-digital conversion module A/DC2(72), the analog-to-digital conversion module A/DC3(73) and the analog-to-digital conversion module A/DC4(74)
Analog-to-digital conversion start control terminals of four analog-to-digital conversion modules A/DC1(71), A/DC2(72), A/DC3(73) and A/DC4(74)
Connected together and then connected with GPIO pin of DSP chip (11), and read data control terminal of the four
Are connected together and then are connected with an external read data pin of the DSP chip (11)
Four analog signal input ends VIN are respectively connected with a sine signal output end, a cosine signal output end, a channel 1 output end y1(t) of an input amplification/attenuation (6) and a channel 2 output end y2(t) of a sweep frequency signal source (4), the four output data buses are connected together, the four data output ends DB0, DB2, DB3, DB4, DB5, DB6, DB7, DB8, DB9, DB10 and DB11 are respectively connected with the 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7, 1B8, 2B1, 2B2, 2B3 and 2B4 ends of a chip SN74ALVC164245, and an analog-to-digital conversion ending signal end of an analog-digital conversion module ADC1(71)
Is connected with the 2B5 end of the chip SN74ALVC 164245;
the 1DIR, 2B6, 2B7, 2B8 and all GND terminals of the chip SN74ALVC164245 are connected with a digital DGND, all VCCB terminals are connected with a digital power supply +5V (D), and are connected with the digital DGND through a capacitor C7, and data buses formed by the 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7, 1A8, 2A1, 2A2, 2A3 and 2A4 ends and an XDB [11..0 ] 0 external data bus XDB of the DSP chip (11)]The connection is carried out by connecting the two parts,
terminal and
the ends of the voltage signal are connected together and then connected with a GPIO pin of the DSP chip (11), and simultaneously connected with a power supply +3.3V through a resistor R1, the end 2A5 is connected with an external interrupt request end XINT of the DSP chip (11), all VCCA ends are connected with the power supply +3.3V, and are connected with a digital DGND through a capacitor C8.
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| CN110174552A (en) * | 2019-05-31 | 2019-08-27 | 昆明理工大学 | A kind of digital double channel frequency response analyzer and test method |
| CN110174552B (en) * | 2019-05-31 | 2023-12-22 | 昆明理工大学 | Digital dual-channel frequency response analyzer and testing method |
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