CN115665000A - High-speed serial bus link test method based on 100G/400G PRBS test verification link realization - Google Patents

Abstract

The invention relates to a high-speed serial bus link test method based on 100G/400GPRBS test verification link realization, and belongs to the technical field of link test. The invention adopts a mode of combining the parallel serial thought, so that the PRBS test verification link is simple to realize and has better time sequence, and the PRBS test verification link has random code patterns, accords with the link transmission requirement, but is regular, thereby being capable of utilizing the PRBS test verification link to carry out the link test of the high-speed serial bus.

Description

High-speed serial bus link test method based on 100G/400G PRBS test verification link realization

Technical Field

The invention belongs to the technical field of link test, and particularly relates to a high-speed serial bus link test method based on 100G/400G PRBS test verification link.

Background

The PRBS (Pseudo-Random Binary Sequence) is a Pseudo-Random Binary Sequence, whose code pattern is Random relative to the channel, but whose data is regular, and therefore is widely used for error rate testing of various high-speed serial channels, such as PCIe, ethernet, OTN and optical module testing.

In recent years, the development of the internet of things, 5G, social media traffic and the like is rapid, and the data transmission demand is increased explosively, which stimulates the demand for a high-speed serial bus. For example, as the most typical high-speed serial bus, ethernet has undergone 1g,25g,100g, 400G ethernet is becoming the center of data, and 800G ethernet standard has been established. As a key link of high-speed serial channel transmission testing, the realization of a PRBS testing verification link of 100G/400G is very important. Compared with a CPU, the parallel computing capability of the FPGA enables the FPGA to realize higher speed and lower time delay, so that the FPGA is more suitable for being used as a PRBS test verification link of 100G/400G.

The conventional PRBS test verifies that the link is implemented in two ways: serial and parallel. The serial implementation mode has simple logic, but is very unreliable in high-speed communication, because each cycle of the serial generates delay, and the high-speed communication clock rate is very high, the convergence of time sequence is difficult to realize, so that the time sequence problem is caused; the parallel implementation method has good time sequence, but the logic is relatively complex, and hundreds or even thousands of logic formulas need to be generated in the rate of 100G/400G, which is also relatively unreasonable.

Disclosure of Invention

Technical problem to be solved

The technical problem to be solved by the invention is as follows: how to design a simple and time-sequential PRBS test verification link implementation method to implement the link test of a high-speed serial bus.

(II) technical scheme

In order to solve the technical problem, the invention provides a high-speed serial bus link test method based on a 100G/400G PRBS test verification link, which comprises the steps of firstly utilizing a PRBS11 generator to realize 1024 times of shift in one clock cycle to obtain 1024-bit PRBS11 data output, namely generating a PRBS test verification link, and then utilizing the generated PRBS test verification link to carry out link test on a high-speed serial bus, wherein the PRBS11 represents 11-order PRBS.

(III) advantageous effects

The invention adopts a mode of combining the parallel serial thought, so that the PRBS test verification link is simple to realize and has better time sequence, and the PRBS test verification link has random code patterns, accords with the link transmission requirement, but is regular, thereby being capable of utilizing the PRBS test verification link to carry out the link test of the high-speed serial bus.

Drawings

FIG. 1 is a schematic diagram of a PRBS11 generator;

FIG. 2 is a schematic diagram of a conversion of 1024 bits to 16 64 bits;

FIG. 3 is a schematic diagram of 16 PRBS11 sub-modules with 64 bits output in parallel and spliced into a PRBS11 module with 1024 bits;

FIG. 4 is a waveform diagram of the output simulation of the 16 PRBS11 sub-modules with DATA _ OUT being 16 64 bits each;

fig. 5 is a diagram showing simulation results of the PRBS11 generating one 1024bit by serial output.

Detailed Description

In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

Due to the influence of the manufacturing process and power consumption of the chip, the bus rate cannot be increased all the time, which requires increasing the data bit width of the bus. Under the condition of only considering a payload part, the realization of a 100G serial bus at least needs 512bit @200MHz, while the realization of a 400G serial bus at least needs 1024bit @400MHz, and in addition to other overheads, the speed requirement is only higher. The commonly used orders for PRBS are 7,9, 11, 15, 20, 23, 31, denoted as PRBS7, PRBS9, PRBS11, PRBS15, PRBS20, PRBS23, PRBS31. The period length of the PRBS code is related to the order number, the code length of the PRBS7 is 127, and the PRBS code is not suitable for a 100G serial bus, and the code length of the PRBS9 is 512, and the PRBS code is not suitable for a 400G serial bus. Therefore, in the present invention, for example, a 400G PRBS test verification link is generated by using an 11-order PRBS, that is, a PRBS11 of 1024 bits is implemented.

The PRBS generator is composed of two parts, namely a Linear Feedback Shift Registers (LFSR) and an exclusive-or circuit. The primitive polynomial of PRBS11 is x ¹¹ +x ⁹ +1, from this polynomial the generator of PRBS11 can be derived, as shown in fig. 1.

The PRBS11 generator shown in fig. 1 can achieve 1024 shifts in one clock cycle to obtain 1024-bit PRBS11 data output.

The specific implementation steps are as follows:

step 1) Generation of a transformation matrix for PRBS11

The following expression can be obtained from the state transition relationship of the PRBS11 shift register of fig. 1:

x11 ^N+1 ＝x10 ^N ；

x10 ^N+1 ＝x9 ^N ；

x9 ^N+1 ＝x8 ^N ；

x8 ^N+1 ＝x7 ^N ；

x7 ^N+1 ＝x6 ^N ；

x6 ^N+1 ＝x5 ^N ；

x5 ^N+1 ＝x4 ^N ；

x4 ^N+1 ＝x3 ^N ；

x3 ^N+1 ＝x2 ^N ；

x2 ^N+1 ＝x1 ^N ；

x1 ^N+1 ＝x0 ^N ＝x9 ^N ^x11 ^N ；

where xi +1 is a shift result of xi, i = 0.., 10,n represents the current state, and N +1 represents the next state;

the above-mentioned relation can be expressed by a matrix as shown in the following formula 1:

this results in a conversion matrix for PRBS 11:

step 2) obtaining a state transition polynomial at any moment according to the transformation matrix T

Let X = [ X ] ¹¹ ,x ¹⁰ ,x ⁹ ,x ⁸ ,x ⁷ ,x ⁶ ,x ⁵ ,x ⁴ ,x ³ ,x ² ,x ¹ ]

Then equation 1 can be expressed as:

X ^N+1 ＝T×X ^N

therefore, the state of any N + K moment can be known as

X ^N+K ＝T ^K ×X ^N (2)

According to T ^K The state transition polynomial at any time is deduced.

Step 3) implementation of PRBS11 with 64bit

The 64-bit PRBS11 generation can adopt a serial-parallel combination mode, because the data is generally processed by taking a byte as a unit, and the 64-bit PRBS11 can be realized by 8 times of parallel output circulation of the 8-bit PRBS11.

Firstly, 8-bit PRBS11 parallel output is realized, and 8-bit PRBS11 parallel output can be simply deduced according to the figure 1.

TABLE 1

Output the output

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

x11

1

x11^x9

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

x11

2

x10^x8

x11^x9

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

3

x9^x7

x10^x8

x11^x9

x1

x2

x3

x4

x5

x6

x7

x8

x9

4

x8^x6

x9^x7

x10^x8

x11^x9

x1

x2

x3

x4

x5

x6

x7

x8

5

x7^x5

x8^x6

x9^x7

x10^x8

x11^x9

x1

x2

x3

x4

x5

x6

x7

6

x6^x4

x7^x5

x8^x6

x9^x7

x10^x8

x11^x9

x1

x2

x3

x4

x5

x6

7

x5^x3

x6^x4

x7^x5

x8^x6

x9^x7

x10^x8

x11^x9

x1

x2

x3

x4

x5

8

x4^x2

x5^x3

x6^x4

x7^x5

x8^x6

x9^x7

x10^x8

x11^x9

x1

x2

x3

x4

In Table 1, the column below "output" is the output data, and the data to the right of the output data is the result of 1-2-3-4 cycles of FIG. 1.

The PRBS [11:

x7＝x4^x2；

x6＝x5^x3；

x5＝x6^x4；

x4＝x7^x5；

x3＝x8^x6；

x2＝x9^x7；

x1＝x10^x8；

x0＝x11^x9；

8 times of circulation is carried out on the 8-bit parallel PRBS11 polynomial, and then a 64-bit PRBS11 output result can be obtained. One polynomial data is generated once in a cycle, and in some occasions, the data continuity between messages can be ensured according to the 8 shift polynomial data (8-bit parallel PRBS11 polynomial) when the messages have the requirement of non-1024 byte integer multiples.

Step 4) 16 64-bit parallel PRBS11 polynomial realization

The 1024-bit parallel PRBS11 polynomial can be converted into 16 64-bit parallel PRBS11 polynomials, as shown in fig. 2, and then each of the generated 64-bit parallel PRBS11 polynomials is a submodule, and there are 16 submodules in total.

The implementation of the PRBS is based on a polynomial and a random code seed, and the PRBS can cycle indefinitely due to the two factors. The random code seed is an initial value generated when the PRBS generator starts to shift, the initial value is agreed by the transmitting and receiving parties together, and the initial value is generally regarded as all 1 by default. Therefore, for PRBS11, the initial value is typically 11' h7FF.

In fig. 2, 1024bit data random code seed is 11'h7ff, and this value is also the random code seed of the PRBS11 submodule 1, and according to the formula 2,n =0,k =64, the initial value seed of the PRBS11 submodule 2 is 11' h21d, and so on, the random code seeds of 16 PRBS11 submodules can be obtained. See table 2:

TABLE 2

Thus, 16 64-bit PRBS11 sub-modules can generate one 64-bit data per clock. In order for the data to cycle correctly, each clock needs to update the random code seed. The state of the current random code seed after 1024 cycles is the new random code seed, that is, K is 1024 in equation 2.

Matrix ofT ¹⁰²⁴ The operation of (3) can be performed by MATLAB, and the obtained result is subjected to modulo-2 operation to obtain a matrix of a polynomial. T of operation ¹⁰²⁴ The modulo-2 results are as follows:

according to the formula, a random code seed after 1024 moments starting from the current moment can be calculated for the next clock.

Step 5) implementation of 1024bit parallel PRBS11 polynomial

The 16 PRBS11 sub-modules with 64 bits are output in parallel and spliced into a PRBS11 module with 1024 bits, namely a parallel PRBS11 polynomial with 1024 bits, as shown in FIG. 3.

And 6) using the parallel PRBS11 polynomial generated in the step 5 as a PRBS test verification link to carry out the link test of the high-speed serial bus. The PRBS test verification link generated by the PRBS test verification link generation method has random code patterns, accords with link transmission requirements, and is regular, so that the PRBS test verification link generated by the method can be used for carrying out link test on a high-speed serial bus.

Next, a description will be given of a simulation result of the PRBS11 of 1024 bits.

The 16 DATA _ OUT of fig. 4 are the output simulation waveforms of the 16 64-bit PRBS11 sub-modules, respectively. In order to verify the correctness of the output result, a 1024-bit PRBS11 is generated in a serial output mode, and the simulation result is shown in FIG. 5. DATA1 to DATA16 in fig. 5 are 16 pieces of 64-bit DATA obtained by dividing DATA _ OUT. The data of the two are completely consistent through comparison, and the design is in accordance with the expectation. It should be noted that, the present invention only exemplifies 16 PRBS11 with 64 bits to realize PRBS11 with 1024 bits, and in practical application, the bit width and number of the sub-modules can be arbitrarily adjusted according to the relationship between the data clock and the data bit width.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.

Claims (10)

1. A high-speed serial bus link test method based on a 100G/400G PRBS test verification link is characterized in that a PRBS11 generator is used for achieving 1024 times of shifting in one clock cycle to obtain 1024-bit PRBS11 output, namely a PRBS test verification link is generated, and then the generated PRBS test verification link is used for carrying out link test on a high-speed serial bus, wherein the PRBS11 represents 11-order PRBS.

2. The method of claim 1, wherein the PRBS test validation link is generated using steps 1 through 5 as follows:

step 1, generating a conversion matrix T of a PRBS11 based on a state transition relation of a PRBS11 shift register in a PRBS11 generator;

step 2, obtaining a state transition polynomial at any moment according to the conversion matrix T;

step 3, obtaining a 64-bit parallel PRBS11 polynomial by adopting a serial-parallel combination mode;

step 4, obtaining 16 parallel PRBS11 polynomials of 64 bits based on the steps 2 and 3;

and step 5, obtaining a 1024-bit parallel PRBS11 polynomial based on the 16 64-bit parallel PRBS11 polynomials generated in the step 4.

3. The method of claim 2, wherein in step 1, the following expression is obtained from the state transition relationship of the PRBS11 shift register:

x11 ^N+1 ＝x10 ^N ；

x10 ^N+1 ＝x9 ^N ；

x9 ^N+1 ＝x8 ^N ；

x8 ^N+1 ＝x7 ^N ；

x7 ^N+1 ＝x6 ^N ；

x6 ^N+1 ＝x5 ^N ；

x5 ^N+1 ＝x4 ^N ；

x4 ^N+1 ＝x3 ^N ；

x3 ^N+1 ＝x2 ^N ；

x2 ^N+1 ＝x1 ^N ；

x1 ^N+1 ＝x0 ^N ＝x9 ^N ^x11 ^N ；

wherein xi +1 is a shift result of xi, i = 0.., 10,n represents a current state, and N +1 represents a next state;

the expression is expressed as the following formula 1 in a matrix:

this results in a conversion matrix for PRBS 11:

4. the method according to claim 3, wherein in step 2, let X = [ X ] ¹¹ ,x ¹⁰ ,x ⁹ ,x ⁸ ,x ⁷ ,x ⁶ ,x ⁵ ,x ⁴ ,x ³ ,x ² ,x ¹ ]

Then equation 1 is expressed as: x ^N+1 ＝T×X ^N

Thus, the state of any N + K moment is known as

X ^N+K ＝T ^K ×X ^N (2)

According to T ^K The state transition polynomial at any time is deduced.

5. The method of claim 4, wherein in step 3, 8-bit PRBS11 parallel output is first implemented, i.e. 8-bit parallel PRBS11 polynomial is:

x7＝x4^x2；

x6＝x5^x3；

x5＝x6^x4；

x4＝x7^x5；

x3＝x8^x6；

x2＝x9^x7；

x1＝x10^x8；

x0＝x11^x9；

then 8 times of circulation is carried out on the 8-bit parallel PRBS11 polynomial to obtain a 64-bit PRBS11 output result, and polynomial data are generated once in each circulation.

6. The method of claim 5, wherein in step 4, the 1024-bit parallel PRBS11 polynomial is converted into 16 64-bit parallel PRBS11 polynomials, and then each of the 64-bit parallel PRBS11 polynomials generated is a submodule, and a total of 16 submodules, namely PRBS11 submodule 1 to PRBS11 submodule 16;

assuming that a 1024-bit data random code seed is 11'h7ff and this value is a random code seed of the PRBS11 submodule 1, obtaining an initial value seed of the PRBS11 submodule 2 of 11' h21d according to the equation 2, n =0, k =64, and repeating the above steps to obtain random code seeds of 16 PRBS11 submodules;

thus, at each clock, 16 PRBS11 sub-modules with 64 bits generate data with 64 bits, the random code seeds are updated at each clock, and the state of the current random code seeds after 1024 cycles is the new random code seeds, namely K in formula 2 is 1024; thereby calculating the random code seed after 1024 moments starting from the current moment for the next clock.

7. The method as claimed in claim 6, wherein in step 5, 16 PRBS11 sub-modules of 64 bits are spliced into a PRBS11 module of 1024 bits in parallel, i.e. a PRBS11 polynomial of 1024 bits in parallel.

8. The method of claim 7, wherein in step 5, the matrix T is completed using MATLAB ¹⁰²⁴ Performing modulo-2 operation on the obtained result to obtain a matrix of polynomials, the T of the operation ¹⁰²⁴ The modulo-2 results are as follows:

9. the method of claim 8, wherein the random code seeds for the 16 PRBS11 sub-modules are tabulated as:

10. the method of any of claims 1 to 9, wherein the PRBS11 shift register in the PRBS11 generator is a linear feedback shift register.

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