CN101404557A - Cyclic redundancy check code generation apparatus and method - Google Patents

Abstract

The invention relates to the transmission data checking field, in particular to a technology for generating a low-cost CRC check code by a hardware circuit. A device for generating a cyclic redundancy check code and a method thereof have a characteristic polynomial, namely g(x) is equal to sigma plus 1; the device comprises trigger groups which are respectively corresponding to x<n1>-x<nk> and formed by a plurality of serially connected triggers; the trigger groups are serially connected in the sequence of the serial numbers of the trigger groups; an exclusive-or gate is connected between two neighboring trigger groups in series; an output terminal of an inverter is connected with an input terminal of a DG1 trigger group; an input terminal of an exclusive nor gate is the input terminal of the device, and the other input terminal of the exclusive nor gate is connected with the output terminal of a DGk trigger group; the output terminal of the exclusive nor gate is connected with the input terminal of the inverter and the input terminals of each exclusive-or gate. In a circuit of the prior art, the inverter connected with each trigger is removed and the inverter is connected to invert before the data is input to the triggers connected in series, thus the method saves a great number of inverters, simplifies a CRC check code generation circuit, and lower the hardware cost.

Description

A kind of cyclic redundancy check code generation apparatus and method

Technical field

The present invention relates to transmit the data check field, relate in particular to and adopt hardware circuit to realize CRC check sign indicating number generation technique cheaply.

Background technology

CRC (Cyclic Redundancy Code, cyclic redundancy check (CRC) code) is a kind of error check code the most frequently used in the data communication, and it can find to transmit single double bit error, odd number mistake in the data, and length is less than the continuous mistake of CRC progression.

The principle of cyclic redundancy check method is as follows:

Any one code of being made up of bit string can be only corresponding one by one with the multinomial of ' 1 ' value for ' 0 ' with a coefficient, and for example: the multinomial of code 110111 correspondences is X ⁵+ X ⁴+ X ²+ X+1.

If the multinomial of the data correspondence that transmit leg will send is V (x);

Transmit leg and recipient arrange a proper polynomial g (x), and the high order power of establishing this proper polynomial is R;

Add R 0 at the end of the data that will send, then its corresponding multinomial is M (x)=x ^RV (x);

Divided by g (x), obtain discussing Q (x) and residue R (x) with M (x), then M (x)=Q (x) g (x)+R (x); The pairing code value step-by-step of residue R (x) negate is the CRC check code value.

Make T (x)=M (x)+R (x), transmit leg sends the pairing data of T (x);

If the multinomial of the data correspondence that the recipient receives be T ' (x), (x) divided by g (x), if residue is 0 (or constant of setting), then the recipient praises and receives the data that transmit leg sends with T '; Otherwise, think the reception mistake.Thereby reach the purpose that the information flow that receives is carried out verification.

Can adopt two kinds of methods to calculate the CRC check code value that will send data at present:

1, adopt software approach to calculate the CRC check sign indicating number of the information code that receives, promptly by software approach according to proper polynomial g (x) calculate will the information transmitted sign indicating number the CRC check sign indicating number.But the software approach computational speed is slow, and need take CPU (Center Process Unit, CPU) resource.

2, information flow can also be crossed hardware circuit in the prior art and obtain the CRC check sign indicating number:

Because being the multinomial V (x) by the information code correspondence, the CRC check sign indicating number multiply by x ^R, be g (x) divided by proper polynomial again after, the pairing code value of the residue R that obtains (x), the hardware circuit that therefore generates the CRC check sign indicating number can be formed by polynomial multiplication circuit and polynomial division circuit synthesis:

Multiply by x ^RCircuit, be equivalent to list entries is postponed to export behind the R position, therefore multiply by x ^RCircuit form by R DQ trigger (perhaps register).Figure 1 shows that and multiply by x ³Circuit.Wherein, R0-R2 is DQ trigger (a perhaps register).

The process of division is exactly constantly displacement and does the process of subtraction with (merchant * divisor), corresponds to circuit and is a negative-feedback circuit.Figure 2 shows that and remove formula x ³+ x ²+ 1 division circuit.Wherein, Y1-Y2 is XOR gate (a logical difference exclusive disjunction circuit).

Multiplication and division circuit in conjunction with above-mentioned can obtain circuit as shown in Figure 3.

For example, be g (x)=x for proper polynomial ¹⁶+ x ¹²+ x ⁵+ 1, the hardware circuit of 16 CRC check sign indicating numbers of generation as shown in Figure 4.Wherein, N0-N15 is inverter (a logic negate circuit), and all after the input input, the output valve of register R15～R0 is residue to all information flows, after the step-by-step negate, just obtains 16 CRC check sign indicating number.According to the definition of different CRC check code types, in some cases, with the remainder of trigger output as the CRC check sign indicating number; (as the check code of CRC-CCITT16/32 type) in some cases, with the remainder negate of trigger output as the CRC check sign indicating number.

If the proper polynomial of CRC check sign indicating number is $g\left(x\right)=\underset{j=1}{\overset{k}{\mathrm{\&Sigma;}}}{x}^{n_j}+1,$ Wherein k, n ₁～n _kBe natural number, then the CRC check code generation circuit of the residue negate of prior art comprises: k trigger group, XOR gate, inverter.

K trigger group corresponds respectively to

Each trigger group is formed by several trigger serial connections; Wherein, corresponding to

DG _jTrigger number in the trigger group is n _j-n _J-1If j=1, then n _J-1=0; The reset values of each trigger is 1.

A plurality of XOR gate, each XOR gate are serially connected with between each trigger group, and the trigger group is according to the numeric order serial connection of trigger group.

Also have an XOR gate in addition, the input of this XOR gate is the input of CRC check code generation circuit, its output and DG ₁An input of the input of trigger group and other XOR gate links to each other.

The number of inverter is identical with the number of trigger, and the input of each inverter links to each other with the output of each trigger respectively.

Information code is imported successively from the input of CRC check code generation circuit, and after described input input, the output of each inverter is the CRC check sign indicating number of residue negate in all information codes.

The present inventor finds, adopt the CRC check code value speed of computed in software information code current slow, take more cpu resource, and the gate that the hardware circuit of the generation CRC check sign indicating number of employing prior art adopts is more, hardware cost is higher, it is bigger to take circuit space.

Summary of the invention

The embodiment of the invention provides a kind of cyclic redundancy check code generation apparatus and method, in order to reduce the cost of the circuit that generates the CRC check sign indicating number.

A kind of cyclic redundancy check code generation apparatus, the proper polynomial of described cyclic redundancy check (CRC) code is $g\left(x\right)=\underset{j=1}{\overset{k}{\mathrm{\&Sigma;}}}{x}^{n_j}+1,$ N wherein ₁～n _kFor natural number, the k of incremental order is natural number, described device comprises:

K trigger group DG ₁～DG _k, correspond respectively to

Each trigger group is formed by several trigger serial connections; Wherein, corresponding to Trigger group DG _jIn the trigger number be n _j-n _J-1If j=1, then n _J-1=0; The trigger group is according to the numeric order serial connection of trigger group;

At least one XOR gate is serially connected with respectively between two adjacent trigger groups;

An inverter, its output and trigger group DG ₁Input link to each other;

Biconditional gate, an one input is the input of described device, another input and trigger group DG _kOutput link to each other, its output links to each other with the input of described inverter and the input of each XOR gate.

The reset values of each trigger in the described trigger group is 0.

Preferable, k equals 3 described in the described device, n ₁～n ₃Equal 5,12,16 respectively.

Preferable, k equals 14 described in the described device, n ₁～n ₁₄Equal 1,2,4,5,7,8,10,11,12,16,22,23,26,32 respectively.

According to the method for said apparatus generation cyclic redundancy check (CRC) code, be used for the information code of input is carried out verification, comprising:

With of the input input of described information code from described device;

After described input input, the cyclic redundancy check (CRC) code of described information code is formed in the output of each trigger in all information codes.

The CRC check code generation circuit of the embodiment of the invention is owing to the inverter that each trigger in the prior art circuits is connected removes, and be input in data and connect inverter before the trigger of serial connection and carry out negate, thereby saved a large amount of inverters, simplified the CRC check code generation circuit, reduced hardware cost.

Description of drawings

Fig. 1 is the mlultiplying circuit schematic diagram of prior art;

Fig. 2 is the polynomial division circuit diagram of prior art;

Fig. 3 is the multiplication and division circuit diagram of prior art;

Fig. 4 is 16 CRC check code generation circuit schematic diagrames of prior art;

Fig. 5 is 16 CRC check code generation circuit schematic diagrames of the embodiment of the invention;

Fig. 6 is 32 CRC check code generation circuit schematic diagrames of the embodiment of the invention.

Embodiment

The CRC check code generation circuit of the embodiment of the invention removes the inverter that each trigger in the prior art circuits connects, and be input in data and connect an inverter before the trigger of serial connection and carry out negate, thereby saved a large amount of inverters, simplified circuit, reduced hardware cost.

The proper polynomial of CRC check sign indicating number can be expressed as $g\left(x\right)=\underset{j=1}{\overset{k}{\mathrm{\&Sigma;}}}{x}^{n_j}+1,$ N wherein ₁～n _kFor natural number, the k of incremental order is natural number.

For example, value k=3, n ₁=5, n ₂=12, n ₃=16 o'clock, then the proper polynomial of CRC check sign indicating number was g (x)=x ¹⁶+ x ¹²+ x ⁵+ 1 (this is the proper polynomial of the check code of CRC-CCITT16 type).

The CRC check code generation circuit of the embodiment of the invention is according to the proper polynomial of CRC check sign indicating number $g\left(x\right)=\underset{j=1}{\overset{k}{\mathrm{\&Sigma;}}}{x}^{n_j}+1$ Generate, specifically comprise: k trigger group, XOR gate, inverter, biconditional gate.

Wherein, k trigger group is DG ₁～DG _kThe trigger group corresponds respectively to the monomial in the proper polynomial

Each trigger group is formed by several trigger serial connections; Wherein, corresponding to DG _jTrigger number in the trigger group is n _j-n _J-1If j=1, then n _J-1=0; K trigger group comprises 16 triggers (R0～R15) altogether.

The trigger group is according to the numeric order serial connection of trigger group; That is to say that the order of trigger group serial connection is identical with the sequence number of trigger group.Such as DG ₁Trigger group back is DG ₂The trigger group, DG ₂Trigger group back is DG ₃The trigger group ...

Reset values for the trigger of the check code prior art that generates the CRC-CCITT16/32 type is 1, and then the reset values of each trigger in the trigger group of the CRC check code generation circuit in the Dui Ying embodiment of the invention is 0; But CRC check sign indicating number for some other type, if the reset values of the trigger of prior art circuits is 0, then the reset values of the trigger of the circuit in the embodiment of the invention is then corresponding becomes 1, that is to say that the reset values of the trigger of the circuit of the embodiment of the invention is opposite with prior art.

XOR gate is serially connected with between two adjacent trigger groups.Such as, at DG ₁Trigger group and DG ₂Be serially connected with XOR gate Y1 between the trigger group, at DG ₂Trigger group and DG ₃Be serially connected with XOR gate Y2...... between the trigger group, between with all adjacent flip-flops groups, be connected in series XOR gate.

Inverter, its output and DG ₁The input of trigger group links to each other.

Biconditional gate, an one input is the input of described CRC check code generation circuit, another input and DG _kThe output of trigger group links to each other, the input of its output and described inverter, and an input of each XOR gate links to each other.

In the process of the CRC check sign indicating number that generates information code, with the input of information code from the CRC check code generation circuit, an input that is biconditional gate is imported successively, then in all information codes after the input of described input, the output of each trigger of trigger group is the CRC check sign indicating number after the residue negate of information code.

Proper polynomial when the CRC check sign indicating number $g\left(x\right)=\underset{j=1}{\overset{k}{\mathrm{\&Sigma;}}}{x}^{n_j}+1$ In k=3, n ₁=5, n ₂=12, n ₃=16 o'clock, proper polynomial was g (x)=x ¹⁶+ x ¹²+ x ⁵+ 1, a concrete CRC check code generation circuit of the correspondence that the embodiment of the invention provides comprises as shown in Figure 5: 3 trigger group (DG ₁～DG ₃), XOR gate (Y1 and Y2), inverter (N0), biconditional gate (Y0).

Because polynomial k=3, so the CRC check code generation circuit comprises 3 trigger groups, wherein DG ₁Corresponding to monomial x ⁵, DG ₂Corresponding to monomial x ¹², DG ₃Corresponding to monomial x ¹⁶The reset values of each trigger in the trigger group can all be 0 according to actual conditions to the definition of CRC check sign indicating number, can all be 1 also.For example, the reset values that generates the trigger in the circuit of check code of CRC-CCITT16/32 type for the embodiment of the invention all is 0.

DG ₁Trigger number in the trigger group is: n ₁-n ₀=5-0=5; DG ₂Trigger number in the trigger group is: n ₂-n ₁=12-5=7; DG ₃Trigger number in the trigger group is: n ₃-n ₂=16-12=4;

At DG ₁～DG ₃Be serially connected with XOR gate Y1, Y2 between the trigger group.And DG ₁～DG ₃The serial connection sequence of trigger group is connected in series according to the sequence number of trigger group, and just, serial connection sequence is DG ₁, DG ₂, DG ₃

Inverter, its output and DG ₁The input of trigger group links to each other.

Biconditional gate, an one input is the input of described CRC check code generation circuit, another input and DG ₃The output of trigger group links to each other, and its output links to each other with the input of described inverter and an input of each XOR gate (Y1 and Y2).

Information code is from the input of as shown in Figure 5 CRC check code generation circuit, an input that is biconditional gate is imported successively, then in all information codes after the input of described input, the output of each trigger of trigger group is the CRC check sign indicating number after the residue negate of information code.

As can be seen from Figure 5, the CRC check code generation circuit that the embodiment of the invention provides has reduced by 15 inverters than the CRC check code generation circuit as described in Figure 4 of prior art, thereby has saved circuit cost, circuit space.And when the figure place of the check code that generates when needs was high more, the quantity of the gate of saving (inverter) was just more, and the circuit space of saving is also just bigger.

Again for example, the generative circuit of 32 CRC check sign indicating number as shown in Figure 6, its proper polynomial is g (x)=x ³²+ x ²⁶+ x ²³+ x ²²+ x ¹⁶+ x ¹²+ x ¹¹+ x ¹⁰+ x ⁸+ x ⁷+ x ⁵+ x ⁴+ x ²+ x+1.(this is the proper polynomial of the check code of CRC-CCITT32 type) circuit comprises 32 triggers (R0～R31), belong to 14 trigger group (DG ₁～DG ₁₄), also comprise: XOR gate (Y1～Y13), inverter (N0), biconditional gate (Y0).

According to said method, can calculate the trigger number in each trigger group.DG ₁～DG ₁₄The trigger number of trigger group be respectively: 1,1,2,1,2,1,2,1,1,4,6,1,3,6.Owing to be the generative circuit of the check code of CRC-CCITT32 type, so the reset values of each trigger in the trigger group of circuit is 0.The trigger group is according to the numeric order serial connection of trigger group.

Between each trigger group, also be serially connected with XOR gate Y1～Y13.XOR gate Y1～Y13 is serially connected with respectively between two adjacent trigger groups.

The output of inverter N0 and DG ₁The input of trigger group links to each other.

The input that input is 32 CRC check code generation circuits of biconditional gate Y0, another input and DG ₁₄The output of trigger group links to each other, and (input of Y1～Y13) links to each other its output with the input of inverter N0 and each XOR gate respectively.

Information code is from the input of as shown in Figure 6 CRC check code generation circuit, an input that is biconditional gate is imported successively, then in all information codes after the input of described input, the output of each trigger of trigger group is the CRC check sign indicating number after the residue negate of information code.

The reset values of the trigger in the circuit that above-mentioned CRC check sign indicating number with generation CRC-CCITT16/32 type is an example is 0, and for the trigger in the circuit of the CRC check sign indicating number of using other type that the principle of the invention generates, those skilled in the art can it be set to 0 or 1 according to actual conditions.

Be that the CRC check sign indicating number exported of CRC check sign indicating number and the CRC check code generation circuit of prior art of example CRC check code generation circuit output that the embodiment of the invention is described is identical with as shown in Figure 5 circuit below.

In circuit as shown in Figure 5, suppose that the reset values (being initial value) of each trigger is C0～C15, owing to the reset values of the reset values and the prior art of each trigger trigger shown in Figure 4 is opposite, then the initial value of each trigger in Fig. 4 circuit is C0～C15.

After a clock cycle, first data D0 of information code is input to as in Fig. 4, the circuit shown in Figure 5, and then each the trigger output valve in Fig. 4, the circuit shown in Figure 5 is as shown in the table:

Table 1

	R0	R1	R2	R3	R4	R5	R6	R7	R8	R9	R10	R11	R12	R13	R14	R15
																	Fig. 4 circuit	C15 ^D0	C0	C1	C2	C3	C4 ^C15 ^D0	C5	C6	C7	C8	C9	C10	C11 ^C15 ^D0	C12	C13	C14
Fig. 5 circuit	～C15 ^D0	～C0	～ C1	～ C2	～ C3	～C4 ^C15 ^D0	～C5	～C6	～C7	～C8	～C9	～ C10	～C11 ^C15 ^D0	C12	～C13	～C14

Can find out directly that from last table after a clock cycle, the value that trigger R1～R4, the R6～R11 in the value of trigger R1～R4, R6～R11 in Fig. 4 circuit and R13～R15 output and Fig. 5 circuit and R13～R15 export is opposite.

And the trigger R0 output valve in Fig. 4 circuit is C15^D0, and the trigger R0 output valve in Fig. 5 circuit is～C15^D0.According to formula A^B=～A^B, C15^D0=～C15^D0 is then arranged, so the R0 in Fig. 4 circuit is also opposite with R0 output valve in Fig. 5 circuit.

In like manner, the output valve of R5, the R12 in Fig. 4 circuit is also opposite with the output valve of R5, R12 in Fig. 5 circuit.Therefore, promptly R0～R15 the output valve with Fig. 5 circuit is identical after inverter is reverse for the R0 in Fig. 4 circuit～R15 output valve.

Through after the clock cycle, repeat the derivation of last clock cycle again, can find that R0 in Fig. 4 circuit～R15 output valve is still opposite with the R0～R15 output valve of Fig. 5 circuit.

And the like, through N clock cycle, after the N bit data stream had been imported in serial, R0 in Fig. 4 circuit～R15 output valve was still opposite with the R0～R15 output valve of Fig. 5 circuit.Promptly R0～R15 the output valve with Fig. 5 circuit is identical and R0 in Fig. 4 circuit～R15 output valve is after inverter is reverse, thereby Fig. 4 obtains identical CRC check sign indicating number with Fig. 5 circuit.

Therefore, the CRC check sign indicating number that generates of the circuit as shown in Figure 5 that provides of the embodiment of the invention is identical with the CRC check sign indicating number of prior art circuit generation as shown in Figure 4.Similarly, the CRC check sign indicating number that other circuit that generates for the method that adopts the embodiment of the invention generates also can be identical with the CRC check sign indicating number that the circuit of prior art generates, no longer various circuit are proved one by one that herein art technology can easyly realize according to the disclosed technology contents of the embodiment of the invention.

The CRC check code generation circuit of the embodiment of the invention is owing to the inverter that each trigger in the prior art circuits is connected removes, and be input in data and connect inverter before the trigger of serial connection and carry out negate, thereby saved a large amount of inverters, simplified the CRC check code generation circuit, reduced hardware cost.

One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct relevant hardware to finish by program, this program can be stored in the computer read/write memory medium, as: ROM/RAM, magnetic disc, CD etc.

Will also be appreciated that the apparatus structure shown in accompanying drawing or the embodiment only is schematically, the presentation logic structure.Wherein the module that shows as separating component may or may not be physically to separate, and the parts that show as module may be or may not be physical modules.

The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (5)

1, a kind of cyclic redundancy check code generation apparatus, the proper polynomial of described cyclic redundancy check (CRC) code is $g\left(x\right)=\underset{j=1}{\overset{k}{\mathrm{\&Sigma;}}}{x}^{n_j}+1,$ N wherein ₁～n _kFor natural number, the k of incremental order is natural number, it is characterized in that,

Described device comprises:

K trigger group DG ₁～DG _k, correspond respectively to

Each trigger group is formed by several trigger serial connections; Wherein, corresponding to

Trigger group DG _jIn the trigger number be n _j-n _J-1If j=1, then n _J-1=0; The trigger group is according to the numeric order serial connection of trigger group;

At least one XOR gate is serially connected with respectively between two adjacent trigger groups;

An inverter, its output and trigger group DG ₁Input link to each other;

Biconditional gate, an one input is the input of described device, another input and trigger group DG _kOutput link to each other, its output links to each other with the input of described inverter and the input of each XOR gate.

2, device as claimed in claim 1 is characterized in that, the reset values of each trigger in the described trigger group is 0.

3, device as claimed in claim 1 or 2 is characterized in that, described k equals 3, n ₁～n ₃Equal 5,12,16 respectively; And

Trigger group DG ₁Specifically form by 5 trigger serial connections;

Trigger group DG ₂Specifically form by 7 trigger serial connections;

Trigger group DG ₃Specifically form by 4 trigger serial connections;

The number of described XOR gate is specially 2.

4, device as claimed in claim 1 or 2 is characterized in that, described k equals 14, n ₁～n ₁₄Equal 1,2,4,5,7,8,10,11,12,16,22,23,26,32 respectively; And

Trigger group DG ₁～DG ₁₄In the number of the trigger that specifically comprises be respectively: 1,1,2,1,2,1,2,1,1,4,6,1,3,6;

The number of described XOR gate is specially 13.

5, a kind of method of passing through to generate as the arbitrary described device of claim 1-4 cyclic redundancy check (CRC) code is used for the information code of input is carried out verification, it is characterized in that, comprising:

With of the input input of described information code from described device;

After described input input, the cyclic redundancy check (CRC) code of described information code is formed in the output of each trigger in all information codes.

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