CN115664409A - FPGA supporting correlated signal to perform correlated wiring - Google Patents

Abstract

The FPGA further comprises a related wiring module on the basis of an initial architecture, a plurality of communicable paths in a related path group in the related wiring module are simultaneously gated under the action of the same control signal, and when wiring operation is executed, a plurality of related signals contained in the same related signal group are respectively and correspondingly connected with a plurality of communicable paths in a related path group of the related wiring module; and controlling a plurality of communicable paths included in the associated path group to be gated simultaneously through a control signal corresponding to the associated path group, and transmitting a plurality of associated signals of the same associated signal group to corresponding output ends of the associated path group by using the plurality of communicable paths. Therefore, the linkage wiring of a plurality of associated signals can be realized, the wiring of each associated signal does not need to be configured respectively, the wiring difficulty of the associated signal group is reduced, and the wiring efficiency is improved.

Description

FPGA supporting correlated signals to perform correlated wiring

Technical Field

The invention relates to the field of FPGA, in particular to an FPGA supporting associated signals for associated wiring.

Background

An FPGA (Field Programmable Gate Array) is a product developed further on the basis of Programmable devices such as PAL (Programmable Array logic) and GAL (general Array logic), which not only solves the defect of circuit customization, but also overcomes the defect of limited Gate circuit number of the original Programmable device.

The FPGA contains a large number of resource modules such as CLB, BRAM, DSP, IOB, each resource module corresponding to one or more interconnect modules INT surrounding its exterior, and by configuring the functional sub-modules FUNC inside the resource modules, the input ports and output ports of the resource modules can be connected to the input ends or output ends of the corresponding interconnect modules INT. Different interconnection modules INT are connected through wiring resources with different lengths, so that the interconnection between the ports of two resource modules can be realized by utilizing the serial connection of one or more interconnection modules INT, and the signal connection required by a user design netlist can be realized.

An interconnect module INT externally provides a plurality of input terminals and a plurality of output terminals, and the interconnect module INT internally includes a plurality of wiring switch boxes, each of which is generally implemented by a multiplexer MUX. All inputs of the interconnect module INT are typically divided into groups of inputs connected to different wiring switch boxes, the output of each wiring switch box being connected to one output of the interconnect module INT. The selection signals of the wiring switch boxes are controlled by the configuration bits with corresponding digits, and the configuration bits of the wiring switch boxes are independent and do not interfere with each other. The content of the configuration bits of each wiring switch box is changed through code stream downloading, and signals of different input ends of the interconnection module INT can be selectively transmitted to the output end to be output.

For example, fig. 1 shows an example where interconnect module INT includes 16 input terminals I0, I1 \8230 \ 8230, I15, and 4 output terminals and includes 4 wiring switch boxes therein, which are respectively written as MUX0, MUX1, MUX2, and MUX 3. The 16 input ends are divided into four groups and are respectively connected to the input ends of the 4 wiring switch boxes, and the output ends of the 4 wiring switch boxes are respectively connected with the 4 output ends Y0, Y1, Y2 and Y3 of the interconnection module INT. Therefore, 16 communicable paths are formed in the interconnection module INT, each of the 4 wiring switch boxes has 2-bit configuration bits, so that the interconnection module INT needs 8-bit configuration bits { S0, S1, S2, S3, S4, S5, S6 and S7} in total, and the on-off of the 16 communicable paths can be controlled by downloading and changing the content of the configuration bits through code streams, so that signals at a required input end are transmitted to a required output end.

In practice, however, the number of inputs and outputs included in an interconnect module INT is often large and not small as illustrated in fig. 1. Moreover, for the flexibility of wiring and the routing rate, only a single input terminal is connected to a single wiring switch box as illustrated in fig. 1, but one input terminal is distributed into different groups to be connected to a plurality of wiring switch boxes, so that each input terminal is possibly connected to each output terminal, namely, a communicable path is formed between each group of input terminals and output terminals. The group selection and distribution of the input ends of the interconnection module INT are determined according to the architecture requirements, and it is generally required to determine which wiring switch boxes an input end can be connected to after a software simulation experiment, so that in actual application, the number of communicable paths formed between different input ends and different output ends inside the interconnection module INT is very large, for example, the number of communicable paths formed inside a typical interconnection module INT can reach 4000, and the selection of each communicable path is independent and non-interfering with each other, so that although the wiring flexibility is high, each communicable path needs to be configured independently on and off, and the wiring difficulty and complexity are actually increased.

Disclosure of Invention

The invention provides an FPGA supporting relevant signals for relevant wiring aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

an FPGA supporting relevant signals for relevant wiring further comprises a relevant wiring module on the basis of an initial framework, wherein the initial framework comprises a resource module and an interconnection module;

the associated wiring module provides a plurality of input ends and a plurality of output ends externally, a plurality of communicable paths are formed between different input ends and different output ends in the associated wiring module, and the associated wiring module gates the communicable paths in the associated wiring module according to the acquired control signal;

at least one associated path group is formed on the communicable paths in the associated wiring module, a plurality of communicable paths in the same associated path group are simultaneously gated under the action of the same control signal, and the plurality of communicable paths in the same associated path group are connected with different input ends and different output ends;

when the wiring operation is executed, one associated signal group is connected to the input end of the associated wiring module, and a plurality of associated signals contained in the same associated signal group are respectively correspondingly connected with a plurality of communicable paths in one associated path group; and controlling the associated wiring module through a control signal corresponding to the associated path group, simultaneously gating a plurality of communicable paths included in the associated path group, and transmitting a plurality of associated signals of the same associated signal group to corresponding output ends of the associated path group by using the plurality of communicable paths.

The method comprises the following steps that a plurality of different associated path groups are formed on communicable paths in one associated wiring module, the communicable paths in the same associated path group are simultaneously gated under the action of the same control signal, and the communicable paths in different associated path groups are gated under the action of different control signals.

When executing wiring operation, connecting a plurality of associated signal groups to the input end of the same associated wiring module, wherein the associated signals contained in each associated signal group are respectively correspondingly connected with a plurality of communicable paths in one associated path group, and different associated signal groups are correspondingly connected with different associated path groups in the associated wiring module;

and when acquiring different control signals, the associated wiring module transmits the associated signals of different associated signal groups to the output end of the associated wiring module through different associated path groups.

The method comprises the following steps that when wiring operation is executed, one associated signal group is connected to the input end of the same associated wiring module, associated signals contained in each associated signal group are respectively and correspondingly connected with a plurality of associated path groups, one input end connected with each associated signal in each associated signal group is connected to the same output end through each communicable path in the associated path groups, and path delay of each communicable path in the associated path groups connected between the input end and the output end of the same group is different.

The method comprises the following steps that when the wiring operation is executed, one associated signal group is connected to the input end of the same associated wiring module, associated signals contained in each associated signal group are respectively and correspondingly connected with a plurality of associated path groups, and one input end connected with at least one associated signal in the associated signal group is connected to a plurality of different output ends through each communicable path in the associated path groups.

The further technical scheme is that the delay differences of the path delays of the communicable paths in different associated path groups in the associated wiring module do not exceed a predetermined threshold, or the delay differences of the path delays of at least two communicable paths exceed a predetermined threshold.

The further technical scheme is that at least one output end of the associated wiring module is combined with the output end of the interconnection module and then connected to the same input port of the corresponding resource module, and the output end of the associated wiring module and the output end of the interconnection module are not conducted with the input port of the resource module at the same time;

and/or the associated wiring module has at least one input end which is simultaneously connected with the same output port of the corresponding resource module with the input end of the interconnection module.

The further technical scheme is that the associated wiring module is arranged in the FPGA close to the resource module for transmitting the associated signal group.

The further technical scheme is that at least one input end of the related wiring module is connected with the output ends of other related wiring modules, and/or at least one output end of the related wiring module is connected with the input ends of other related wiring modules.

The further technical scheme is that the length of the connecting line between different related wiring modules is smaller than the span of the clock domain or exceeds the span of the clock domain.

The further technical scheme is that the connection between different related wiring modules is realized through a high-level metal layer.

The further technical scheme is that a group of BUS signals form a related signal group, and the delay difference of path delay of a plurality of communicable paths in the same related path group used for connecting the group of BUS signals in the related wiring module during gating does not exceed a preset threshold value.

The technical scheme is that a plurality of associated wiring modules are distributed in the FPGA and are distributed according to a row and/or column structure.

The further technical scheme is that the inside of the associated wiring module comprises a plurality of associated switch boxes, the associated switch boxes are simultaneously controlled by control signals of the associated wiring module, the input end of each associated switch box is connected with a plurality of input ends of the associated wiring module, the output end of each associated switch box is respectively connected with one output end of the associated wiring module, and the associated wiring module forms an internal communicable path through the associated switch boxes;

the multiple communicable paths in the same associated path group are respectively formed by gating of multiple different associated switch boxes, and the control signals acquired by the associated wiring module control the associated switch boxes in a linkage manner, so that the multiple communicable paths in the same associated path group are gated simultaneously.

The beneficial technical effects of the invention are as follows:

the application discloses support relevant signal to carry out FPGA of associated wiring, this FPGA has additionally added relevant wiring module on the basis of initial framework, and the inside associated route group that contains can coordinated control of associated wiring module, when inciting somebody to action a set of associated signal input associated wiring module, utilize associated route group just can realize the linkage wiring to a plurality of associated signals simultaneously, need not to dispose the wiring of each associated signal respectively to reduce the wiring degree of difficulty of associated signal group, improved wiring efficiency.

The connection ports and the path delay of the associated path groups in the associated wiring module can be configured as required, so that the associated signals can meet the requirements of required paths and delay when the associated signals are subjected to linkage wiring, and the wiring quality is ensured. Especially for the BUS signal which has requirements on synchronism, the path time delay of each associated signal does not need to be selected and adjusted respectively, and the method can effectively ensure the transmission synchronism.

Drawings

Fig. 1 is a schematic diagram of the internal structure of an interconnect module INT in the conventional initial architecture of an FPGA.

FIG. 2 is a schematic diagram of ganged wiring implemented by associated wiring modules added on the basis of the initial architecture in one embodiment.

Fig. 3 is a schematic diagram of ganged switching of an associated signal group to a communicable path with a different path delay using an associated routing module in one embodiment.

FIG. 4 is a diagram illustrating an embodiment of a linkage switch of an associated signal group to a different output terminal by using an associated wiring module.

FIG. 5 is a schematic diagram illustrating an embodiment of switching associated route groups in a coordinated manner by using an associated routing module to output different associated signal groups.

Fig. 6 is a schematic diagram of the internal structure of an associated wiring module and its parallel use with an interconnect module in one embodiment.

Detailed Description

The following description of the embodiments of the present invention will be made with reference to the accompanying drawings.

The application discloses an FPGA supporting relevant signals for relevant wiring, and the FPGA further comprises a relevant wiring module on the basis of a conventional initial architecture, namely the FPGA modifies an internal hardware architecture relative to the conventional FPGA. The conventional initial architecture is the architecture described in the background section, and the initial architecture includes resource modules and interconnection modules, where the resource modules include CLBs, BRAMs, DSPs, IOBs, and the like, and the interconnection module is an INT module, which includes a plurality of wiring switch boxes inside and provides a plurality of input terminals and a plurality of output terminals externally, and a plurality of communicable paths between different input terminals and different output terminals are formed inside the INT module, and each communicable path inside the INT module is controlled by a control signal of the INT module, and control signals of any two communicable paths are different.

The associated wiring module BITT added relative to the initial framework is also arranged around the resource modules, and the associated wiring module BITT and the interconnection module INT in the initial framework exist in the FPGA at the same time and are all used for signal interconnection among the resource modules.

The associated wiring module bin also provides a plurality of input terminals and a plurality of output terminals to the outside, and a plurality of communicable paths are also formed between different input terminals and output terminals inside the associated wiring module bin, and the on-off of each communicable path is controlled by the control signal ctrl acquired by the associated wiring module bin. However, unlike the conventional interconnection module INT, the communicable paths inside the associated wiring module bin are not completely independent from each other, and at least one associated path set is formed on the communicable paths inside the associated wiring module bin, where the same associated path set includes a plurality of communicable paths associated with each other, inputs of the plurality of communicable paths are respectively connected to different inputs of the associated wiring module bin, and outputs of the plurality of communicable paths are respectively connected to different outputs of the associated wiring module bin. This association between communicable paths in the same association path group is manifested in: a plurality of communicable paths in the same associated path group are simultaneously gated under the action of the same control signal ctrl. That is, unlike the interconnection module INT, any one of the communicable paths inside can be independently turned on and off, and the state in which the plurality of communicable paths are provided inside the associated wiring module BINT is linked, and these communicable paths are simultaneously turned on or off.

For example, fig. 2 illustrates an associated path group formed inside the associated wiring module bin, where the associated path group includes four communicable paths line1, line2, line3, and line4 that are associated with each other, the four communicable paths are respectively connected to four different input ends I0, I4, I8, and I12 of the associated wiring module bin, the associated wiring module bin is respectively connected to four output ends Y0, Y1, Y2, and Y3 of the associated wiring module bin, and the on/off of the four communicable paths are controlled by the control signal ctrl simultaneously. In order to show the on-off effect of the communicable path as shown in fig. 2, the switch may not be present in practice by taking the example of the switch on the path, and fig. 2 is only for illustration.

Based on the newly added associated wiring module bin, when the wiring operation is performed on the FPGA, the associated path group inside the associated wiring module bin can be used to perform linkage wiring on a plurality of associated signals included in the same associated signal group at the same time. When the wiring operation is executed, one associated signal group is connected to the input end of the associated wiring module bin, and a plurality of associated signals included in the same associated signal group are respectively correspondingly connected to the plurality of communicable paths in one associated path group, that is, connected to the input end connected with the plurality of communicable paths in one associated path group. Then, the associated routing module BINT is controlled by a control signal corresponding to the associated path group, so that a plurality of communicable paths included in the associated path group can be gated simultaneously, and a plurality of associated signals of the same associated signal group can be directly transmitted to corresponding output ends of the associated path group by using the plurality of gated communicable paths, without respectively configuring communicable paths of the associated signals.

For example, in fig. 2, one associated signal group Sig1[3], which includes four associated signals respectively written as Sig1[3], sig1[2], sig1[1], sig1[0], are connected to I0, I4, I8, I12 of the associated wiring module BINT as shown in fig. 2, that is, at the input ends to which the four communicable paths line1, line2, line3, and line4 are connected. The four communicable paths can be controlled to be closed simultaneously in an interlocked manner by the control signal ctrl, thereby outputting the associated signal Sig1[3] from Y0, the associated signal Sig1[2] from Y1, the associated signal Sig1[1] from Y2, and the associated signal Sig1[0] from Y3.

The related signals in the related signal group in the application can have functional relevance or functional relevance, and can be configured by user definition, and any plurality of signals needing linkage wiring can form one related signal group. In one embodiment, a group of BUS signals is formed into an associated signal group, that is, a group of BUS signals can be wired in a linkage manner by using the method of the present application, and in this application scenario, the delay difference of path delay of a plurality of communicable paths in the same associated path group used for connecting a group of BUS signals inside the associated wiring module BINT during gating does not exceed a predetermined threshold. In this embodiment, a plurality of communicable paths with substantially equal path delay in the associated wiring module bin may be gated by one control signal, so that an input group of BUS signals is output through corresponding output terminals, and not only can linkage wiring be implemented for a group of BUS signals, but also the requirement of transmission delay of a group of BUS signals can be satisfied. Otherwise, in the conventional initial architecture, when the interconnect module INT is used to transmit a group of BUS signals, a plurality of communicable paths with substantially equal path delay need to be selected from a large number of communicable paths inside the interconnect module INT, and then gating is configured respectively, which is tedious in operation and difficult.

As described above, the path delay of multiple communicable paths in the same associated path group during gating can be configured in a customized manner, so that the path delays of the multiple communicable paths have a specific relationship, so as to meet the wiring requirements of different usage scenarios. For example, the delay difference in the foregoing examples does not exceed the predetermined threshold, that is, the path delays are considered to be equal within the error range, or the path delays are sequentially increased, or other relationships of the path delays are not limited in this application.

On the basis, in another embodiment, one associated routing module bin includes a plurality of associated path groups, and the number of associatively connectable paths included in the plurality of associated path groups is equal to or unequal to each other. For example, an associated routing module bin includes three associated path groups, where each of two associated path groups includes four associatively connectable paths, and another associated path group includes three associatively connectable paths. The communicable paths included in different associated path groups are different from each other, the communicable paths in different associated path groups may connect to the same or different inputs, and the communicable paths in different associated path groups may connect to the same or different outputs. Different control signals corresponding to different associated path groups, so that the communicable paths in different associated path groups are gated under the action of different control signals.

When a plurality of associated path sets are included in one associated routing module bin, the relationship between the path latencies of the plurality of communicable paths within each associated path set may be as described above. The delay differences of the path delays of the communicable paths in different associated path groups in the associated routing module do not exceed the predetermined threshold, or the delay differences of the path delays of at least two communicable paths exceed the predetermined threshold, that is, the path delays of the communicable paths in different associated path groups may also form a corresponding relationship according to actual needs. Thereby being used for meeting different time delay requirements in the wiring process.

When one association routing module bin includes a plurality of association path groups, in an embodiment, a plurality of association path groups may be connected to the same association signal group, that is, a plurality of association signals included in the same association signal group are respectively and correspondingly connected to a plurality of association path groups. Then, when the associated wiring module bin acquires different control signals, the same associated signal group may be transmitted to the output terminal of the associated wiring module bin via different associated path groups. The embodiment is suitable for a scenario in which an input end connected to each correlation signal is connected to the same output end through each communicable path in the plurality of correlation path groups, and if path delays of each communicable path in the plurality of correlation path groups connected between the input end and the output end of the same group are different, different correlation path groups are switched through different control signals, so that delays of correlation signals between a group of input ends and output ends can be conveniently adjusted. Another scenario applicable to this embodiment is that there is at least one input end to which the correlation signal is connected, and the at least one communicable path in each correlation path group is connected to a plurality of different output ends through each communicable path in the plurality of correlation path groups, and each communicable path in each correlation path group is connected between different input ends and output ends, and then different correlation path groups are switched through different control signals, so that the output ends for outputting the correlation signals can be conveniently adjusted.

For example, referring to fig. 3 based on fig. 2, one associated routing module bin includes two associated path sets a and B, where the associated path set a includes four communicable paths, which are written as lineA1, lineA2, lineA3, and lineA4, and the path delays of the four communicable paths are delay1, which is indicated by a solid line in fig. 3. The associated path set B includes four communicable paths, which are denoted as lineB1, lineB2, lineB3, and lineB4, and the path delays of the four communicable paths are delay2, which is shown by a dashed-dotted line in fig. 3. The delay difference of the path delay1 and the path delay2 exceeds a predetermined threshold. It should be noted that the lengths and routing of the communicable paths in fig. 3 are only schematic and do not represent actual situations. The four communicable paths in the associated path group a are respectively connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module bin, and the four communicable paths in the associated path group B are also respectively connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module bin. Four associated signals Sig1[3], sig1[2], sig1[1] and Sig1[0] in one associated signal group Sig1[3] are respectively connected to the four input terminals I0, I4, I8 and I12 of the associated wiring module BINT, and then when the associated wiring module BINT receives the control signal ctrl A, four communicable paths in the associated path group A are simultaneously gated, so that Sig1[3], sig1[2], sig1[1] and Sig1[0] are sequentially output from Y0, Y1, Y2 and Y3 through lineA1, lineA2, lineA3 and lineA4 with path delay of delay 1. And when the associated wiring module BINT receives the control signal ctrl B, the four communicable paths in the associated path group B are simultaneously gated, so that Sig1[3], sig1[2], sig1[1] and Sig1[0] are sequentially output from Y0, Y1, Y2 and Y3 through the lineB1, lineB2, lineB3 and lineB4 with the path delay of delay 2. Therefore, synchronous linkage switching of paths of a plurality of associated signals can be achieved, time delay of the plurality of associated signals can be conveniently adjusted synchronously, the time delay of the plurality of associated signals before switching can be equal, the time delay of the plurality of associated signals after switching can be still equal, and independent configuration is not needed each time.

For another example, referring to fig. 4 based on fig. 2, one associated wiring module bin includes two associated path sets a and C, where the associated path set a includes four communicable paths, which are written as lineA1, lineA2, lineA3, and lineA4, and the four communicable paths in the associated path set a are respectively connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module bin, which are indicated by solid lines in fig. 4. The associated path set C includes four communicable paths, which are written as lineC1, lineC2, lineC3 and lineC4, and the four communicable paths in the associated path set C are also respectively connected to the four input terminals I0, I4, I8 and I12 of the associated wiring module bin, but the four communicable paths are sequentially connected to the four output terminals Y1, Y0, Y2 and Y3. Four associated signals Sig1[3], sig1[2], sig1[1] and Sig1[0] in one associated signal group Sig1[3] are respectively connected to the four input terminals I0, I4, I8 and I12 of the associated wiring module BINT, and then when the associated wiring module BINT receives the control signal ctrl A, four communicable paths in the associated path group A are simultaneously gated so that Sig1[3], sig1[2], sig1[1] and Sig1[0] are sequentially output from Y0, Y1, Y2 and Y3 through lineA1, lineA2, lineA3 and lineA 4. When the associative wiring module BINT receives the control signal ctrl C, the four communicable paths in the associative path group C are simultaneously gated so that Sig1[3], sig1[2], sig1[1] and Sig1[0] are sequentially output from Y1, Y0, Y2 and Y3 through lineC1, lineC2, lineC3 and lineC 4. Therefore, synchronous linkage switching of paths of a plurality of related signals can be realized, and output ports of the plurality of related signals can be conveniently and synchronously adjusted.

Or in another embodiment, there may be a plurality of association path groups connected to different association signal groups, that is, there may be a plurality of association signal groups accessing to the input end of the same association routing module BINT, each association signal group corresponds to one association path group, that is, the association signal included in each association signal group is connected to a plurality of communicable paths in one association path group, respectively, and different association signal groups are connected to different association path groups inside the association routing module BINT. In this scenario, the relationship of the path delays between different associated path groups is configured according to the actual situation. In this embodiment, when the associated wiring module BINT acquires a different control signal, the associated signals of the different associated signal groups may be transmitted to the respective output terminals of the associated wiring module BINT via the different associated path groups.

For example, referring to fig. 5, an associated routing module bin includes two associated path sets D and E, which respectively include four communicable paths. The four communicable paths lineD1, lineD2, lineD3, and lineD4 in the associated path group D are respectively connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module BINT. The four communicable paths lineE1, lineE2, lineE3, and lineE4 in the associated path group E are respectively connected to the four input terminals I2, I6, I10, I14 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module BINT. Four correlation signals in one correlation signal group Sig1[3] are connected to the four input terminals I0, I4, I8, I12 of the correlation routing module BINT, respectively, and four correlation signals in another correlation signal group Sig2[ 3] are connected to the four input terminals I2, I6, I10, I14 of the correlation routing module BINT, respectively. Then when the associated routing module BINT receives the control signal ctrl d, the four communicable paths within the associated path group C are simultaneously gated, and the associated signal group Sig1[3] is transmitted to the output terminal of the associated routing module BINT by using the four communicable paths within the associated path group C. When the association routing module BINT receives the control signal ctrl E, the four communicable paths in the association path group D are simultaneously gated, and the association signal group Sig2[ 3. Thereby, different associated signal groups can be conveniently switched to be output.

In any case, when the total routing resource requirement of the architecture is calculated by performing the routing operation, the original total resource number of the interconnection module INT in the initial architecture is not changed, the associated routing module BINT is regarded as being additionally increased, and the connection line of the associated routing module BINT does not affect the routing capability of the initial architecture.

The associated wiring module BINT may be connected to a resource module in the FPGA, and then the associated wiring module BINT has at least one output terminal which is combined with the output terminal of the interconnect module INT and then connected to the same input port of the corresponding resource module, and the output terminal of the associated wiring module and the output terminal of the interconnect module are not simultaneously conducted with the input port of the resource module. One implementation way is that the output of the associated wiring module bin and the output of the interconnection module INT are connected to the same input port of the resource module after passing through an alternative multiplexer, thereby implementing the above functions. And/or, the associated wiring module BINT has at least one input end connected to the same output port of the corresponding resource module as the input end of the interconnect module INT, that is, the input of the resource module fanout to the associated wiring module BINT is increased on the original architecture. Therefore, the parallel use of the associated wiring module BINT and the interconnection module INT can be realized on the basis of not influencing the integrity of the original framework.

Referring to fig. 6, the output terminal OUT0 of the resource block 1 is connected to the input terminals of both the interconnect block INT and the associated wiring block BINT, and OUT1, OUT2 and OUT3 are the same. The four output terminals Y0, Y1, Y2, and Y3 of the associated wiring module BINT and the four output terminals Y0, Y1, Y2, and Y3 of the interconnect module INT are respectively connected to the input terminals IN0, IN1, IN2, and IN3 of the resource module 2 after passing through the one-out-of-two multiplexer.

When the associated wiring module bin can be connected to the resource module in the FPGA, the associated wiring module bin is arranged inside the FPGA close to the resource module transmitting the associated signal group. I.e. within the FPGA, the set of associated signals is usually transmitted by some specific resource modules, and the associated routing module bin is built in close proximity to these resource modules to reduce the transmission distance between the associated routing module bin and the resource modules. For example, when the associated signal group is a group of BUS signals, common resource modules generating the BUS signals include a DSP, a BRAM, a GTH, and the like, and the associated wiring module BINT is arranged close to the resource modules.

On the basis of the method provided by the application, a plurality of associated wiring modules BITT are distributed in the FPGA, and the associated wiring modules are distributed according to a row and/or column structure. In general practical application, the associated wiring modules BINT are arranged in a column, one or more columns of associated wiring modules BINT are arranged in the FPGA, each column of associated wiring modules BINT may be arranged near the resource modules transmitting the associated signal group as described above, and the resource modules are often arranged in a column structure, and the arrangement forms of the two are matched. Or each column of associated wiring modules bin may be arranged at the boundary of the FPGA so as to be close to the IOB module and the CMT module, and the actual layout position is determined as required, which is not limited in the present application.

When a plurality of associated wiring modules bin are arranged inside the FPGA, the associated wiring modules bin can be connected with other associated wiring modules bin in addition to the resource modules in the FPGA. That is, an associated routing module has at least one input connected to an output of another associated routing module, and/or an associated routing module has at least one output connected to an input of another associated routing module.

In this embodiment, the wires between different associated routing modules BITT have lengths that are less than the span of the clock domain or that exceed the span of the clock domain. Also, long-distance wiring can be added between different associated wiring modules BITT, so that switching when the wiring module INT passes through is simplified when the long-distance wiring is needed, and time delay is reduced. The manner in which different lengths of wiring are supported between different associated wiring modules BINT may utilize a wire twisting approach similar to the conventional interconnection module INT. In another embodiment, the wiring between different associated routing modules BIT is implemented through a higher metal layer, thereby further reducing latency.

This embodiment provides an implementation of the internal structure of the associated wiring module BINT, which is similar to the conventional interconnect module INT, based on the function of the associated wiring module BINT, which internally includes a plurality of associated switch boxes, which may also be implemented by multiplexers. The associated switch boxes are simultaneously controlled by control signals of the associated wiring modules, the input end of each associated switch box is connected with a plurality of input ends of the associated wiring modules, the output end of each associated switch box is respectively connected with one output end of the associated wiring module, and the associated wiring module BITT forms an internal communicable path through the associated switch boxes. The multiple communicable paths in the same associated path group are respectively formed by gating of multiple different associated switch boxes, and the control signals acquired by the associated wiring module control the associated switch boxes in a linkage manner, so that the multiple communicable paths in the same associated path group are gated simultaneously.

For example, referring to fig. 6, a case corresponding to the internal structure of the interconnect module INT shown in fig. 1 includes 16 input terminals, 4 output terminals, and 4 parallel switch boxes inside, and the connection manner of the 4 parallel switch boxes to the input terminals and the output terminals is similar to that shown in fig. 1. In this embodiment, four associated path groups are formed by 4 parallel switch boxes, each associated path includes four communicable paths and is realized by 4 parallel switch boxes respectively, the 4 parallel switch boxes are controlled by two configuration bits S0 and S1 at the same time, and when a group of configuration bits are received, the 4 parallel switch boxes all act to realize the linkage control of one associated path group.

Claims (14)

1. An FPGA supporting relevant signals for relevant wiring is characterized in that the FPGA further comprises a relevant wiring module on the basis of an initial architecture, and the initial architecture comprises a resource module and an interconnection module;

the associated wiring module provides a plurality of input ends and a plurality of output ends externally, a plurality of communicable paths are formed between different input ends and different output ends in the associated wiring module, and the associated wiring module gates the communicable paths in the associated wiring module according to the acquired control signal;

at least one associated path group is formed on the communicable paths in the associated wiring module, a plurality of communicable paths in the same associated path group are simultaneously gated under the action of the same control signal, and the plurality of communicable paths in the same associated path group are connected with different input ends and different output ends;

when the wiring operation is executed, one associated signal group is connected to the input end of the associated wiring module, and a plurality of associated signals contained in the same associated signal group are respectively correspondingly connected with a plurality of communicable paths in one associated path group; the related wiring module is controlled through a control signal corresponding to the related path group, a plurality of communicable paths included in the related path group are gated at the same time, and a plurality of related signals of the same related signal group are transmitted to corresponding output ends of the related path group through the plurality of communicable paths.

2. The FPGA of claim 1, wherein the communicable paths in one associated routing module are formed with a plurality of different associated path groups, the plurality of communicable paths in one associated path group are simultaneously gated under the action of one control signal, and the communicable paths in different associated path groups are gated under the action of different control signals.

3. The FPGA of claim 2, wherein when performing routing operations, a plurality of associated signal sets are connected to an input end of the same associated routing module, associated signals included in each associated signal set are respectively correspondingly connected to a plurality of communicable paths in one associated path set, and different associated signal sets are correspondingly connected to different associated path sets inside the associated routing module;

and when acquiring different control signals, the association wiring module transmits association signals of different association signal groups to the output end of the association wiring module through different association path groups.

4. The FPGA of claim 2, wherein when performing a routing operation, one associated signal group is connected to an input end of the same associated routing module, each associated signal group includes associated signals respectively connected to a plurality of associated path groups, one input end of each associated signal group connected to each associated signal is connected to the same output end through each communicable path in the plurality of associated path groups, and path delays of each communicable path in the plurality of associated path groups connected between the input end and the output end of the same group are different.

5. The FPGA of claim 2, wherein when performing a routing operation, one associated signal group is connected to the input end of the same associated routing module, associated signals included in each associated signal group are respectively correspondingly connected to a plurality of associated path groups, and one input end connected to at least one associated signal in the associated signal group is connected to a plurality of different output ends through each communicable path in the associated path groups.

6. An FPGA according to claim 2, wherein none of the delay differences in path delays for communicable paths in different associated sets of paths in an associated routing module exceeds a predetermined threshold, or there is at least two of the delay differences in path delays for communicable paths that exceed a predetermined threshold.

7. The FPGA of claim 1,

the associated wiring module is connected to the same input port of the corresponding resource module after at least one output end of the associated wiring module is combined with the output end of the interconnection module, and the output end of the associated wiring module and the output end of the interconnection module are not conducted with the input port of the resource module at the same time;

and/or at least one input end of the associated wiring module and the input end of the interconnection module are simultaneously connected with the same output port of the corresponding resource module.

8. The FPGA of claim 7, wherein the associated routing module is routed within the FPGA proximate to a resource module that transmits the associated set of signals.

9. The FPGA of claim 1, wherein said associated routing module has at least one input connected to an output of another associated routing module and/or wherein said associated routing module has at least one output connected to an input of another associated routing module.

10. The FPGA of claim 9 wherein the length of the wiring between different associated routing modules is less than the span of the clock domain or exceeds the span of the clock domain.

11. The FPGA of claim 9 wherein connections between different associated routing modules are made through a high level metal layer.

12. The FPGA of claim 1, wherein a group of BUS signals is formed into an associated signal group, and the delay difference of the path delay of a plurality of communicable paths in the same associated path group for connecting the group of BUS signals in the associated wiring module during gating does not exceed a predetermined threshold value.

13. The FPGA of claim 1, wherein a plurality of associated routing modules are disposed within the FPGA and are arranged in a row and/or column configuration.

14. The FPGA of claim 1, wherein the associated routing module internally comprises a plurality of associated switch boxes, each of which is simultaneously controlled by a control signal of the associated routing module, an input of each associated switch box is connected to a plurality of inputs of the associated routing module, an output of each associated switch box is connected to one output of the associated routing module, and the associated routing module forms an internal communicable path through the associated switch boxes;

the multiple communicable paths in the same associated path group are respectively formed by gating of multiple different associated switch boxes, and the control signals acquired by the associated wiring module control the associated switch boxes in a linkage manner, so that the multiple communicable paths in the same associated path group are gated simultaneously.

Images