CN114861582A

CN114861582A - Multi-input LUT layout method based on FPGA

Info

Publication number: CN114861582A
Application number: CN202210462595.7A
Authority: CN
Inventors: 罗钧; 蒋中华; 郭敬霞; 刘桂林; 王海力
Original assignee: Jingwei Qili Beijing Technology Co ltd
Current assignee: Jingwei Qili Beijing Technology Co ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2022-08-05

Abstract

The invention provides a layout method of a multi-input LUT (look-up table) based on an FPGA (field programmable gate array), which is used for increasing at least one external signal input port in a logic area LP of the FPGA and is used when a register in the LP is accessed to an external input signal. And (3) laying out the FPGA, and judging the number of input ports and input ports used by the LUT when the register is driven by an external signal and wiring conflict occurs. When the input port and the output port of the LUT are empty, any one of the empty input ends and any one of the empty output ends of the LUT are arranged into a single-input single-output gate through mode selection setting, the input end of the gate is used for providing a new external input port for a register, and the logic functions realized by the input port and the output port which are originally used by the LUT are kept unchanged. The layout method reduces the number of LP units in the FPGA chip which needs to be re-laid, so that the FPGA chip has more compact layout result and shorter wiring distance, thereby reducing the transmission delay of the electric signal.

Description

Multi-input LUT layout method based on FPGA

Technical Field

The application relates to the field of integrated circuit application, in particular to a layout method of a multi-input LUT based on an FPGA.

Background

In the comprehensive implementation stage of the fpga (field Programmable Gate array) chip design process, the comprehensive layout stage will compile the circuit designed by the hardware description language into a logic netlist formed by connecting basic logic units, and the basic components of the netlist mainly include various registers reg (register) and multiple input look-up table lut (lookup table). In the later routing stage of the implementation, the program will assign these netlists to the gate circuits actually present on the chip and determine their connection paths.

Generally, an FPGA chip includes a plurality of Programmable Logic Blocks (PLBs), each PLB includes a certain number of Logic regions LP (Logic partition), each LP includes a certain number of look-up tables LUT, registers REG, adders ADD, multiplexers MUX, and the like, and in a layout stage, the PLBs are used as an independent unit, signals for implementing Logic mapping come from inside of the PLBs and also come from outside of the PLBs.

Disclosure of Invention

The invention aims to provide a layout method of a multi-input LUT based on an FPGA (field programmable gate array), which can fully utilize port resources in a PLB (programmable logic B), aiming at the defects of the prior art. When the register REG is driven by an external signal and the input terminal of the external signal has a wiring conflict, the number of the input ports actually used by the LUT is determined. And under the condition that the input port and the output port of at least one LUT are both suspended, converting any suspended input port and any suspended output port of the LUT into wiring resources of signals outside the register REG for use. Thereby reducing the number of LPs that need to be rearranged, making the layout result more compact and the area used smaller.

The invention provides a layout method of a multi-input LUT (look-up table) based on an FPGA (field programmable gate array). the layout method realizes that at least one external signal input port is added in a logic area LP of the FPGA, wherein the LP comprises a multi-input LUT and at least two registers REG; the external signal input port is used when the register is accessed to an external input signal, and the layout method comprises the following steps:

laying out an FPGA, wherein the FPGA comprises a PLB, the PLB comprises an LP, and an input port and an output port of an LUT in the LP are used for realizing logic functions; the LP comprises an LUT and at least two registers;

when the register is driven by an external signal, judging whether the input end of the external signal generates wiring conflict; when the input end of the external signal generates wiring conflict, judging the number of input ports and the number of output ports used by the LUT in the LP;

selecting a particular one of the at least one LUT in the LP when both the input port and the output port of the at least one LUT are suspended; any suspended input port of the specific LUT is combined with any suspended output port of the specific LUT to form a single-input single-output gate; the input end of the gate is used for accessing an external input signal to the register; the logic function of the other input and output ports of the particular LUT, except for the any one floating port and the any one output port, remains unchanged.

The multi-input LUT has two output ports, x and xy.

Preferably, the xy port at the output end outputs any required functional signal through a gating rule, and the x port at the output end is suspended. The gating rules are set in the LUT look-up table.

Preferably, the input ports not used by the LUT are left floating.

Preferably, writing b0 at the beginning of the control data of the specific LUT lookup table indicates that the specific LUT layout is unchanged, and writing b1 indicates a gate for laying out any one floating input port of the specific LUT in combination with any one floating output port of the specific LUT into one single input and single output.

Preferably, the FPGA is an HME C1/P1 FPGA chip.

Compared with the prior art, the layout method of the multi-input LUT based on the FPGA provided by the embodiment of the invention is based on the LP structure of HME C1/P1, and under the condition that the input port and the output port of the LUT are suspended, any suspended input port of the LUT is combined with any suspended output port to be laid out into a single-input single-output gate through mode selection of lookup table LUT control data, so that the suspended port is converted into a wiring resource for use. When the registers in the LPs are driven by the outside and wiring conflict occurs, the number of the LPs needing to be re-laid is reduced, the actual layout positions of the gate circuit elements of the related nets are closer, the wiring time is shortened, and the wiring path length is shortened, so that the delay of an FPGA chip can be reduced, and the key frequency of the FPGA chip is improved.

Drawings

In order to more simply explain the technical solution of the embodiment of the present invention, the drawings needed to be used in the description of the embodiment will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a prior art circuit diagram of a LUT based on HME C1/P1 FPGA devices, configured as six-input single-output in an embodiment of the present invention;

FIG. 2 is a circuit diagram of an embodiment of an LUT based on an HME C1/P1 FPGA device with floating input and output ports configured as a single-input single-output gate;

FIG. 3 is an internal block diagram of an LP based on HME C1/P1 FPGA device in an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without any creative efforts belong to the protection scope of the present invention.

The method in the following embodiment of the invention is realized based on an HME C1/P1 FPGA device, and for better understanding of the technical scheme provided by the embodiment of the invention, firstly, the logic structure of the HME C1/P1 FPGA device is briefly explained.

In the hardware architecture of HME C1/P1 FPGA, the FPGA chip includes a plurality of Programmable Logic Blocks (PLBs), typically N × M rectangular arrays, each PLB includes 4 Logic regions LP (Logic partition), each LP includes two six-output single-output look-up tables LUT6 and four registers REG, two adders ADD and eight multiplexers.

In fig. 1, the LUT used in the actual chip is a six-port input, and the placement algorithm places the multiple-input gates in the gate netlist onto the calculated LUT locations.

After the LUT6 layout is complete, the input ports are f [ 5: 0], the output port is x and xy, at least one input signal is accessed at the input end and distributed at any position of f0-f 5; and outputting any required functional signal at an output terminal xy port through a gating rule, wherein the output terminal x port is limited to be in a suspended state and has no signal output. The gating rules are set in a look-up table.

At input f [ 5: 0] the number of input signals accessed to any port is K (K is more than or equal to 0 and less than or equal to 6), when K is more than 0, the LUT6 function is not idle, and the position of the port occupied by the input signals is f: k (K is more than or equal to 0 and less than or equal to 5), the number of occupied ports is K, and the required function signals can be output at the xy ports by modifying the lookup table.

Divide the input of LUT6 into f: and other input ports except the K ports at the K (K is more than or equal to 0 and less than or equal to 5) positions are suspended.

In fig. 2, when the register is driven by an external signal, it is determined whether or not a wiring conflict occurs at the input terminal of the external signal. When a wiring conflict occurs at the input terminal of the external signal, the number of input ports used by the LUT6 is judged.

In one embodiment, when the LUT6 uses less than 5 input ports, at least two input ports are floating, and any one floating input port and any one floating output port of the LUT6 are configured as a single-input single-output strobe by controlling the mode selection setting of the data in the look-up table LUT 6. At this time, the layout of the LUT6 includes the newly added external interface module LUT5_1 and the original function module LUT5_ 2. Because of the internal structural features of the HME C1/P1 FPGA device, the input port f5 is directly vacant in the converted layout, has no signal connection and can not be used for layout and wiring any more.

Preferably, the added external interface module LUT5_1 is functionally equivalent to a single-input single-output selector, which is used to provide an input terminal for the register to be used as a wiring resource for external input signals.

Preferably, the original function block LUT5_2 is used to implement the original logic function of LUT6, and the position and sequence of the input and output ends used are not limited.

Preferably, the number of LUTs 6 that can be found in a LP to meet the layout conditions described above is the number of external signal input ports that can be added to the LP.

Preferably, the mode selection setting is implemented when writing control data inside the look-up table, for example, writing b0 at the beginning of the look-up table data indicates that the LUT6 layout is unchanged, and writing b1 indicates that any one of the floating input ports and any one of the floating output ports of the LUT6 are laid out as a single-input single-output strobe.

Preferably, the input ports not used by the LUT are left floating.

LUT6 has a floating input port and a floating output port for routing other gates in the LP. Therefore, the number of various gates such as registers which can be put down without path conflict is increased because one more routing path is added to the gates in the same LP in the subsequent DRC check, and the gates do not need to search for the position again for layout in the detailed layout process.

In one embodiment, the input port of the newly added external interface module LUT5_1 generated by the layout transition is f1[ 4: 0], the output port is x, the input port of the original functional module LUT5_2 is f2[ 4: 0], output port xy, input port f1[ 4: 0] and input f2[ 4: 0] are connected together in a one-to-one correspondence, such as port f 1: 0 connection f 2: 0, successively correspond.

An external driving input signal is accessed to any floating position of an input end f1[ 4: 0] of the LUT5_1, and the occupied port position is f 1: n (0 ≦ n ≦ 4), the output f1 may be gated at the x port by modifying the lookup table: an n-port external drive input signal. In this case, LUT5_1 is functionally equivalent to a single input single output selector.

The number of input signals accessed to an input end f2[ 4: 0] of the LUT5_2 is M (M is more than or equal to 0 and less than 5), when M is more than 0, the LUT5-2 function is not idle, and the number of occupied port of the input signal is f 2: m (M is more than or equal to 0 and less than or equal to 4, M is not equal to n), the number of occupied ports is M, and the required function signal can be output at the xy port by modifying the lookup table. LUT5_2 is used to implement the logic function of original LUT6, and the location and order of the used input and output terminals are not limited.

In fig. 2, because of the internal structure of the FPGA chip, the output port x of LUT5_1 and the output port xy of LUT5_2 are connected to a MUX, but the MUX can ignore the input signal from the x port by setting the gating of the MUX, so as not to affect the logic function of the original functional module LUT 5-2.

Preferably, the unused inputs in the LUT are left floating.

In fig. 3, the internal structure of LP based on HME C1/P1 FPGA is shown, and there are two LUTs, four REGs, two adders ADD and eight multiplexers in one LP, and for convenience of discussion, the adders ADD and redundant multiplexers are omitted, and a brief connection mode is provided, where the LUTs 6_1 and 6_2 are all six-input single-output multi-input lookup tables. In addition to this, there are two external input connection lines bypass0, bypass 1.

Based on the connection scheme in fig. 3, in the case that a certain pair of REGs (e.g., REG0 and REG8, REG1 and REG9) in the same LP are both driven by devices outside the PLB, it is assumed that a pair of REGs (assumed as REG0 and REG8) in the PLB both inputs come from outside the PLB where the current LP is located, and there is only one bypass line for a pair of REGs due to limited wiring resources. Although the bypass0 shown in fig. 3 is connected to the multiplexers at the front ends of REG0 and REG8, it can be ensured that bypass0 can only be used by one of REG0 and REG8 at the same time without mutual interference by writing a lookup table.

At this time, in the case of the layout of the LUT6 in the prior art, both REG0 and REG8 are used during layout, and each of them corresponds to a different input signal from the outside, and the available wiring resources are only one bypass0 connection, and at this time, a collision occurs due to insufficient wiring resources, so that the system determines the position of one of REGs as illegal, and needs to search for another legal layout position for this REG.

In this embodiment, for the LUT used, the number of input ports it uses under the layout of the prior art LUT6 is checked, and if the number of input ports used does not exceed 4, the usage pattern of the LUT is selected at the time of layout, which is converted into two LUT5 functional blocks.

At this time, there are two LUTs 5, and the input of LUT5 corresponding to the xy port is set as the input of the original LUT, which is called LUT5 as LUT5_ 2. Because of the floating ports, the ports of LUT5 are sufficient, and the floating input ports can always be set to go down from f4, referring to another LUT5 as LUT5_ 1. At this time, the input port f5 is directly left empty for internal structural reasons, and no signal is connected, and therefore, it cannot be used for the layout and wiring. Writing the look-up table of the LUT5_2 into the look-up result same as the LUT6 in the original layout ensures that the logic function of the LUT5_2 is consistent with the logic function of the LUT6 in the original layout.

As can be seen from the block diagram of the LUT5 layout in fig. 2, the input of LUT5_1 is the same as LUT5_2, and it has been mentioned above that this optimization is performed only when the number of input ports used is below 5, so that at least one floating port exists at the input port of LUT5_1, and the position of the floating port is also downward from f 4.

Any of the floating ports is selected for use and the look-up table of LUT5_1 is modified so that the value of its output port x is set to the input value of the selected floating port. At this time, LUT5_1 can be regarded as a single-input single-output selector, and its input and output are the same. What can then be approximated is a connection line with a slightly higher delay than a conventional connection line. For REGs 0 and REG8, at this time, LP may provide two wires for external input, one wire is accessed by bypass0, the MUX2 selects and outputs the external input for REG0, and the other wire is accessed by the input port of LUT5_1, after the external input is output by the output port x of LUT5_1, the MUX1 selects and outputs the external input for REG8, so that bypass collision will not occur, both wires are in legal positions, and no new positions need to be found later.

Relatively speaking, finding a new location for REGs tends to be found across PLBs, and the latency of connections between PLBs is usually much larger than that of a single LUT, so this optimization can effectively reduce logic latency and place the associated devices as close to each other as possible, so the chip area requirement is also much smaller.

It should be noted that, although the specific embodiment of the present invention is implemented based on the HME C1/P1 FPGA chip, it will be understood by those skilled in the art that the layout method provided in the present invention can be applied to FPGA chips with other architectures as well as with slight variations. The embodiment of the present invention is illustrated by taking six inputs as an example, and does not constitute a specific input number limitation, and the number of LUT input ports may be specifically determined by combining actual requirements. In accordance with the present example, which relates to principles and technical explanation, the layout transitions for LUTs with other numbers of input ports, and so on.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A layout method of a multi-input LUT based on an FPGA is characterized by comprising the following steps:

2. The layout method of claim 1 wherein the multiple-input LUT has two output ports, x, xy.

3. The layout method according to claim 2, wherein any required function signal is output from the xy port of the output terminal through a gating rule, and the x port of the output terminal is suspended. The gating rules are set in the LUT look-up table.

4. A placement method according to claim 3, characterized by floating the input ports not used by the LUT.

5. The method of claim 1 wherein writing b0 at the beginning of the particular LUT lookup table control data indicates that the particular LUT layout is unchanged and writing b1 indicates a gate that lays out any one of the floating-in ports of the particular LUT in combination with any one of the floating-in ports of the particular LUT as one of the single-input single-output.

6. The layout method of claim 1, wherein the FPGA is a HME C1/P1 FPGA chip.