CN115662978A - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
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- CN115662978A CN115662978A CN202211417218.8A CN202211417218A CN115662978A CN 115662978 A CN115662978 A CN 115662978A CN 202211417218 A CN202211417218 A CN 202211417218A CN 115662978 A CN115662978 A CN 115662978A
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Abstract
The application discloses an insulated gate bipolar transistor which comprises a grid bus, a grid lead bonding area and a plurality of built-in resistance islands, wherein the built-in resistance islands are connected with the grid bus, and at least one built-in resistance island is connected with the grid lead bonding area. The scheme can improve the adjustment flexibility of the grid built-in resistor.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a new power electronic device in which a MOS field effect Transistor and a Bipolar Transistor are combined. The power transistor has the advantages of easy driving and simple control of the MOSFET, has the advantages of reduced on-state voltage of the power transistor, large on-state current and small loss, becomes one of core electronic components in a modern power electronic circuit, and is widely applied to various fields of national economy such as communication, energy, traffic, industry, medicine, household appliances, aerospace and the like. The application of the IGBT plays an extremely important role in improving the performance of a power electronic system.
Some IGBT with specific requirements at present need a grid built-in resistor, and the resistance value needs to be customized according to application requirements. In an actual IGBT chip, due to the deviation between simulation and reality, the gate built-in resistance is usually adjusted many times, and a satisfactory gate built-in resistance can be obtained. At present, the mainstream technology is to introduce a gate built-in resistor by designing a polysilicon layer and a metal layer. Therefore, if the resistance value of the gate built-in resistor is adjusted, the polysilicon layer and the metal layer need to be changed again, the chip is manufactured again, and the flexibility of adjusting the gate built-in resistor is low.
Disclosure of Invention
The application provides an insulated gate bipolar transistor, which can improve the adjustment flexibility of a built-in resistance of a grid electrode.
The application provides an insulated gate bipolar transistor, including grid bus, grid lead bonding area and a plurality of built-in resistance island, it is a plurality of built-in resistance island with the grid bus is connected, at least one built-in resistance island with grid lead bonding area connects.
In the insulated gate bipolar transistor provided by the application, the built-in resistance island comprises first polycrystalline silicon, second polycrystalline silicon and an internal resistance pressure welding area, the first polycrystalline silicon is connected between the grid bus and the second polycrystalline silicon, and the internal resistance pressure welding area is arranged on the second polycrystalline silicon.
In the insulated gate bipolar transistor provided by the application, at least one built-in resistance island is connected with the grid lead bonding area through an internal resistance lead.
In the insulated gate bipolar transistor provided by the application, at least one built-in resistor island is directly connected with the grid lead bonding area through the internal resistance bonding area, and the rest built-in resistor islands are connected with the grid lead bonding area through internal resistance leads.
In the insulated gate bipolar transistor provided by the application, a first dielectric layer is arranged between the second polycrystalline silicon and the internal pressure welding area, a first contact hole is formed in the first dielectric layer, and the second polycrystalline silicon is connected with the internal pressure welding area through the first contact hole.
In the insulated gate bipolar transistor provided by the application, the minimum distance between the second polycrystalline silicon and the gate lead bonding area is 100-300 micrometers.
In the insulated gate bipolar transistor provided by the application, the size of the second polysilicon is larger than that of the first polysilicon.
In the insulated gate bipolar transistor provided by the application, the first polysilicon is rectangular, and the aspect ratio of the first polysilicon is 1 to 1.
In the insulated gate bipolar transistor provided by the application, the gate lead bonding area comprises third polysilicon and a lead bonding pad, and the lead bonding pad is arranged on the third polysilicon.
In the insulated gate bipolar transistor provided by the application, a second dielectric layer is arranged between the third polycrystalline silicon and the lead bonding pad, a second contact hole is formed in the second dielectric layer, and the third polycrystalline silicon is connected with the lead bonding pad through the second contact hole.
In summary, the insulated gate bipolar transistor provided by the present application includes a gate bus, a gate lead bonding area, and a plurality of built-in resistor islands, where the built-in resistor islands are connected to the gate bus, and at least one built-in resistor island is connected to the gate lead bonding area. The scheme can flexibly adjust the built-in resistance of the grid by adjusting the number of the built-in resistance islands connected with the grid lead bonding area. That is, the scheme can improve the adjustment flexibility of the grid built-in resistor.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a first structure of an insulated gate bipolar transistor according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a second structure of an insulated gate bipolar transistor according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a third structure of an insulated gate bipolar transistor according to an embodiment of the present application.
Fig. 4 is a fourth structural diagram of an insulated gate bipolar transistor according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, a reference to an element identified by the phrase "comprising one of 82308230a of 82303030, or an element defined by the phrase" comprising another identical element does not exclude the presence of the same element in a process, method, article, or apparatus comprising the element, and elements having the same designation may or may not have the same meaning in different embodiments of the application, the particular meaning being determined by its interpretation in the particular embodiment or by further reference to the context of the particular embodiment.
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.
In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The technical solution shown in the present application will be described in detail by specific examples. It should be noted that the description sequence of the following embodiments is not intended to limit the priority sequence of the embodiments.
Some IGBT with specific requirements at present need a grid built-in resistor, and the resistance value needs to be customized according to application requirements. In an actual IGBT chip, due to the deviation between simulation and reality, the gate built-in resistance is usually adjusted many times, and a satisfactory gate built-in resistance can be obtained. At present, the mainstream technology is to introduce a gate built-in resistor by designing a polysilicon layer and a metal layer. Therefore, if the resistance value of the gate built-in resistor is adjusted, the polysilicon layer and the metal layer need to be changed again, the chip is manufactured again, and the flexibility of adjusting the gate built-in resistor is low.
Based on this, the present application provides an insulated gate bipolar transistor, as shown in fig. 1 to 4, which may include a gate bus line 10, a gate lead bonding area 30, and a plurality of built-in resistive islands 20, where the plurality of built-in resistive islands 20 are connected to the gate bus line 10, and at least one built-in resistive island 20 is connected to the gate lead bonding area 30.
The embedded resistor island 20 includes a first polysilicon 21, a second polysilicon 22, and an inner resistive bonding area 23. The first polysilicon 21 is connected between the gate bus line 10 and the second polysilicon 22, and the inner blocking bonding region 23 is disposed on the second polysilicon 22. In some embodiments, a first dielectric layer is disposed between the second polysilicon 22 and the inner pinch-off pad 23, the first dielectric layer having a first contact hole disposed thereon, the second polysilicon 22 being connected to the inner pinch-off pad 23 through the first contact hole.
Wherein the gate wire bonding area 30 may include a third polysilicon 31 and a wire pad 32, the wire pad 32 being disposed on the third polysilicon 31. In some embodiments, a second dielectric layer is disposed between the third polysilicon 31 and the lead pad 32, and a second contact hole is disposed on the second dielectric layer, through which the third polysilicon 31 is connected to the lead pad 32.
Generally, when a power device is manufactured, a certain amount of impurities are doped in a polysilicon material, so that the polysilicon material has a certain resistance. Therefore, in some embodiments, the gate built-in resistance can be adjusted by adjusting the size of the first polysilicon 21.
In the embodiment of the present application, the first polysilicon 21 may be rectangular in shape. The aspect ratio of the first polysilicon 21 may be 1. The length of the first polysilicon 21 may be 10 μm to 100 μm. It should be noted that, in the present embodiment, each first polysilicon 21 may have a different length-width ratio, so that each first polysilicon 21 has a different single resistance value, which is beneficial to flexibly adjust the gate built-in resistor.
For example, when the aspect ratio of the first polysilicon 21 is 2. For another example, when the aspect ratio of the first polysilicon 21 is 3. In the embodiment of the present application, the square resistance of the first polysilicon 21 may be 1 Ω to 10 Ω.
To facilitate the connection of the internal resistance wire 40, the size of the second polysilicon 22 is larger than that of the first polysilicon 21. In the embodiment of the present application, the size of the second polysilicon 22 may be 100 μm to 250 μm.
It can be understood that since the first polysilicon 21 and the second polysilicon 22 are formed by the same polysilicon layer, the thicknesses of the first polysilicon 21 and the second polysilicon 22 are the same. Accordingly, dimensions in the embodiments of the present application refer to length by width. That is, the length and width of the second polysilicon 22 can be 100 μm to 250 μm.
It will be appreciated that the size of the inner pinch-off region 23 is smaller than the size of the second polysilicon 22. In the embodiment of the present application, the size of the inner pressure welding region 23 may be 50 μm to 200 μm.
In some embodiments, at least one of the built-in resistor islands 20 may be connected to the gate wire bonding area 30 through an internal resistor wire 40 to transmit gate electrical signals to the gate bus line 10 through one or more of the built-in resistor islands 20, thereby forming a gate built-in resistor using the resistance of the first polysilicon 21. It is understood that the gate built-in resistor can be flexibly adjusted by adjusting the number of the internal resistance wires 40 connecting the gate wire bonding area 30 and the built-in resistor island 20.
For example, as shown in fig. 1 or 3, when the resistance of each first polysilicon 21 is 10 Ω and the number of internal resistance wires 40 is 1, the gate built-in resistance at this time is 10 Ω. When the resistance of each first polysilicon 21 is 10 Ω and the number of built-in leads is 2, the gate built-in resistance at this time is 5 Ω. When the resistance of each first polysilicon 21 is 10 Ω and the number of built-in leads is 3, the gate built-in resistance is about 3.3 Ω at this time.
In some embodiments, to avoid the situation where there is no internal resistance lead 40 connecting the internal resistance island 20 and the gate lead bonding area 30, resulting in no gate internal resistance, at least one internal resistance island 20 may be provided to connect directly to the gate lead bonding area 30 through the internal resistance bonding area 23.
Note that the number of internal resistance islands 20 directly connected to the gate lead bonding area 30 through the internal resistance bonding area 23 is smaller than the total number of internal resistance islands 20. At this time, in order to facilitate flexible adjustment of the gate built-in resistance, the remaining built-in resistance islands 20 may be connected to the gate lead bonding area 30 through the internal resistance lead 40.
It will be appreciated that the total number of built-in resistive islands 20 may be adjusted according to actual requirements. In this embodiment, the total number of the built-in resistive islands 20 may be 3 to 10. The line width of the internal resistance lead 40 is 1mil to 10mil.
In the embodiment of the present invention, a plurality of internal resistor islands 20 are arranged in parallel between the gate bus lines 10 and the gate lead bonding areas 30, and in order to ensure a certain electrical isolation between the internal resistor islands 20 and the gate lead bonding areas 30, a certain distance is required between the internal resistor islands 20 and the gate lead bonding areas 30. In some embodiments, the minimum spacing between the second polysilicon 22 and the gate wire bonding area 30 may be 100 μm to 300 μm.
In this embodiment, the igbt may further include a package wire 50 and a wire pad 60. Bond pad 60 is connected to gate lead bond 30 by package bond 50, thereby allowing the electrical signal externally applied to the gate to be introduced into the igbt.
The embodiment also provides a manufacturing method of the insulated gate bipolar transistor, and the manufacturing method of the insulated gate bipolar transistor comprises the following steps: providing a semiconductor substrate, and manufacturing a field oxide and a terminal ring; step two, forming an active region; step three, forming a polysilicon layer and photoetching to form a first polysilicon 21, a second polysilicon 22 and a third polysilicon 31; step four, forming a dielectric layer and photoetching to form a first dielectric layer and a second dielectric layer; step five, forming a first contact hole and a second contact hole by etching; step five, forming a metal layer and photoetching to form an internal pressure welding area 23 and a lead welding pad 32; step six, forming a passivation layer and carrying out back process; and seventhly, packaging and testing.
It should be noted that, the above is a general manufacturing process of the igbt, and the specific manufacturing process of the igbt can be implemented by the prior art, and is not described in detail herein.
In summary, the igbt provided in the embodiment of the present invention may include a gate bus 10, a gate lead bonding area 30, and a plurality of internal resistive islands 20, where the plurality of internal resistive islands 20 are connected to the gate bus 10, and at least one internal resistive island 20 is connected to the gate lead bonding area 30. According to the scheme, the quantity of the built-in resistor islands 20 connected with the grid lead bonding area 30 can be adjusted, and the built-in resistors of the grid can be flexibly adjusted without re-flow chip manufacturing. That is, the scheme can improve the adjustment flexibility of the grid built-in resistor and save the manufacturing cost and the time cost.
The insulated gate bipolar transistor provided by the present application is described in detail above, and the principle and the implementation of the present application are explained in the present application by applying specific examples, and the description of the above examples is only used to help understand the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. The insulated gate bipolar transistor is characterized by comprising a gate bus, a gate lead bonding area and a plurality of built-in resistor islands, wherein the built-in resistor islands are connected with the gate bus, and at least one built-in resistor island is connected with the gate lead bonding area.
2. The igbt of claim 1, wherein the built-in resistive island comprises a first polysilicon, a second polysilicon, and an inner pinch-off pad, the first polysilicon being connected between the gate bus and the second polysilicon, the inner pinch-off pad being disposed on the second polysilicon.
3. The igbt of claim 2 wherein at least one of the built-in resistive islands is connected to the gate lead bond pad by an internal resistance lead.
4. The igbt of claim 2 wherein at least one of the internal resistive islands is connected directly to the gate lead bond pad through the internal resistance bond pad, and the remaining internal resistive islands are connected to the gate lead bond pad through internal resistance leads.
5. The insulated gate bipolar transistor of any of claims 2-4, wherein a first dielectric layer is disposed between said second polysilicon and said inner resistive bonding pad, said first dielectric layer having a first contact hole disposed therein, said second polysilicon being connected to said inner resistive bonding pad through said first contact hole.
6. The insulated gate bipolar transistor of any of claims 2-4 wherein the minimum spacing between said second polysilicon and said gate lead bond pad is between 100 μm and 300 μm.
7. The insulated gate bipolar transistor of any of claims 2-4, wherein the size of said second polysilicon is larger than the size of said first polysilicon.
8. The insulated gate bipolar transistor according to any one of claims 2 to 4, wherein the first polysilicon has a rectangular shape, and an aspect ratio of the first polysilicon is 1 to 4.
9. The insulated gate bipolar transistor of any of claims 1-4 wherein said gate wire bond pad comprises a third polysilicon and a wire bond pad, said wire bond pad disposed on said third polysilicon.
10. The igbt according to claim 9, wherein a second dielectric layer is provided between the third polysilicon and the lead pad, the second dielectric layer having a second contact hole provided thereon, and the third polysilicon is connected to the lead pad through the second contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211417218.8A CN115662978B (en) | 2022-11-14 | 2022-11-14 | Insulated gate bipolar transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211417218.8A CN115662978B (en) | 2022-11-14 | 2022-11-14 | Insulated gate bipolar transistor |
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| CN115662978A true CN115662978A (en) | 2023-01-31 |
| CN115662978B CN115662978B (en) | 2023-03-31 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592006A (en) * | 1994-05-13 | 1997-01-07 | International Rectifier Corporation | Gate resistor for IGBT |
| US6013940A (en) * | 1994-08-19 | 2000-01-11 | Seiko Instruments Inc. | Poly-crystalline silicon film ladder resistor |
| CN104022093A (en) * | 2014-06-17 | 2014-09-03 | 江苏中科君芯科技有限公司 | Integrated grid electrode structure with variable grid resistance |
| CN110770915A (en) * | 2017-07-06 | 2020-02-07 | 通用电气公司 | Grid network with positive temperature coefficient of resistance (PTC) for semiconductor power conversion devices |
| CN216749899U (en) * | 2022-01-26 | 2022-06-14 | 上海埃积半导体有限公司 | IGBT layout structure with built-in adjustable grid resistor |
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2022
- 2022-11-14 CN CN202211417218.8A patent/CN115662978B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592006A (en) * | 1994-05-13 | 1997-01-07 | International Rectifier Corporation | Gate resistor for IGBT |
| US6013940A (en) * | 1994-08-19 | 2000-01-11 | Seiko Instruments Inc. | Poly-crystalline silicon film ladder resistor |
| CN104022093A (en) * | 2014-06-17 | 2014-09-03 | 江苏中科君芯科技有限公司 | Integrated grid electrode structure with variable grid resistance |
| CN110770915A (en) * | 2017-07-06 | 2020-02-07 | 通用电气公司 | Grid network with positive temperature coefficient of resistance (PTC) for semiconductor power conversion devices |
| CN216749899U (en) * | 2022-01-26 | 2022-06-14 | 上海埃积半导体有限公司 | IGBT layout structure with built-in adjustable grid resistor |
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| CN115662978B (en) | 2023-03-31 |
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