CN115662715A - Chip resistor with high power and high resistance precision - Google Patents
Chip resistor with high power and high resistance precision Download PDFInfo
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- CN115662715A CN115662715A CN202211234181.5A CN202211234181A CN115662715A CN 115662715 A CN115662715 A CN 115662715A CN 202211234181 A CN202211234181 A CN 202211234181A CN 115662715 A CN115662715 A CN 115662715A
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- layer
- top surface
- resistance
- window
- insulating layer
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- 239000000463 material Substances 0.000 claims abstract description 51
- 239000011265 semifinished product Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000000919 ceramic Substances 0.000 claims abstract description 12
- 230000001681 protective effect Effects 0.000 claims abstract description 11
- 239000010949 copper Substances 0.000 claims description 56
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052748 manganese Inorganic materials 0.000 claims description 5
- 239000011572 manganese Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000005234 chemical deposition Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 26
- 238000002360 preparation method Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
The invention relates to a chip resistor with high power and high resistance precision, which comprises: a ceramic substrate; a first insulating layer attached to the top surface of the substrate, a first window being formed in the center of the first insulating layer; a first resistance layer filled in the first window and configured as a negative temperature coefficient resistance material; the Cu layers are positioned at two ends of the top surface of the semi-finished product and extend from the top surface of the negative temperature coefficient resistance material to the top surface of the first insulating layer, and a second window is formed between the Cu layers; a second insulating layer filled in the second window; the second resistance layer is prepared on the top surface of the semi-finished product, the shape of the second resistance layer is the same as that of the first resistance layer, the second resistance layer is positioned right above the first resistance layer, the bottom of the second resistance layer is electrically connected with the Cu layers at two ends respectively, and the second resistance layer is configured to be a positive temperature coefficient resistance material; and the protective film is used for protecting the second resistance layer and does not completely cover the top surface of the Cu layer.
Description
Technical Field
The invention relates to a high-power high-resistance-value-precision chip resistor.
Background
The conventional chip resistor can be classified into a thick film resistor and a thin film resistor according to the process, wherein the thick film resistor is manufactured by a screen printing process, generally, a resistor material is printed on an insulating substrate (such as alumina ceramic) and then sintered, and the main process of the thin film resistor is sputtering. The thick film resistor is characterized by large resistance and large power, but the screen printing has precision defects, and the thin film resistor can reach higher resistance precision, but the resistance of the resistor is relatively lower based on the sputtering process, so that a new process of the chip resistor needs to be researched to realize the relative balance of precision and power, namely, the precision of the chip resistor is improved relative to the thick film resistor, and the resistance of the chip resistor can be improved relative to the thin film resistor.
Disclosure of Invention
The invention provides the high-power high-resistance-value-precision chip resistor to solve the defects in the prior art, and the chip resistor has improved precision compared with a thick-film resistor and can achieve improved resistance compared with a thin-film resistor.
Therefore, a high-power high-resistance-value-precision chip resistor is provided, which is characterized by comprising:
a ceramic substrate;
the first insulating layer is attached to the top surface of the ceramic substrate, and a first window for preparing a first resistance layer is formed in the center of the first insulating layer;
a first resistance layer filled in the first window and configured as a negative temperature coefficient resistance material;
the Cu layers are positioned at two ends of the top surface of the semi-finished product after the negative temperature coefficient resistance material is prepared, extend from the top surface of the negative temperature coefficient resistance material to the top surface of the first insulating layer, and form a second window for preparing a second insulating layer between the Cu layers at two ends of the top surface of the semi-finished product;
a second insulating layer filled in the second window;
the second resistance layer is prepared on the top surface of the semi-finished product after the second insulating layer is prepared, the shape of the second resistance layer is the same as that of the first resistance layer, the second resistance layer is positioned right above the first resistance layer, the bottom of the second resistance layer is electrically connected with the Cu layers at two ends respectively, and the second resistance layer is configured to be a positive temperature coefficient resistance material;
and the protective film is covered on the top surface of the semi-finished product after the positive temperature coefficient resistance material is prepared, is used for protecting the second resistance layer and incompletely covers the top surface of the Cu layer.
Furthermore, the material of the first resistance layer is configured to be nickel, and a copper adhesion film is sputtered between the bottom of the first resistance layer and the ceramic substrate.
Further, the material of the second resistance layer is configured as manganese.
The manufacturing method of the chip resistor is also provided, and comprises the following steps:
1) Preparing a first insulating layer on the top surface of the ceramic substrate, coating photoresist on the top surface of the first insulating layer, exposing and developing, and etching the first insulating layer to remove the first insulating layer which is not covered by the photoresist and form a first window in the center of the first insulating layer;
2) Preparing a first resistance layer, stripping the photoresist, and preparing a negative temperature coefficient resistance material in a first window;
3) Preparing a Cu layer on the top surface of a semi-finished product after the negative temperature coefficient resistance material is prepared, coating photoresist on the top surface of the Cu layer, etching the Cu layer after exposure and development to remove the Cu layer which is not covered by the photoresist, wherein the etched Cu layer is positioned at two ends of the top surface of the semi-finished product and extends from the top surface of the negative temperature coefficient resistance material to the top surface of the first insulating layer, and a second window for preparing a second insulating layer is formed between the Cu layers at two ends of the top surface of the semi-finished product;
4) Stripping the photoresist, and preparing a second insulating layer in the second window;
5) Coating photoresist on the top surface of the semi-finished product after the second insulating layer is prepared, exposing and developing to form a third window, wherein the shape of the third window is the same as that of the first window and is positioned right above the first window;
6) Preparing a positive temperature coefficient resistance material in a third window;
7) And stripping the photoresist, and preparing a protective film for protecting the second resistance layer on the top surface of the semi-finished product after the positive temperature coefficient resistance material is prepared, wherein the protective film does not completely cover the top surface of the Cu layer.
Further, the negative temperature coefficient of resistance material is configured as nickel. The manner of preparing the negative temperature coefficient of resistance material further comprises: sputtering a copper adhesion film on the first window, controlling the thickness of the copper adhesion film to make the copper adhesion film non-conductive, and then forming the negative temperature coefficient resistance material in the first window through chemical deposition of a nickel deposition process. The thickness of the copper adhesion film is configured to be 5-10nm.
Further, the positive temperature coefficient of resistance material is configured as manganese and is attached to the second insulating layer and the Cu layer by a sputtering process.
According to the resistor structure and the preparation method, on one hand, positive and negative temperature coefficient resistor layers of the parallel structure are utilized to counteract the temperature change, so that the temperature drift influence is reduced, and the resistor precision is improved; on the other hand, the positive temperature coefficient resistance layer and the negative temperature coefficient resistance layer are configured to clamp the electrodes together to form a shunt effect as equal as possible, and the two resistance layers are separated by using the insulating layer to achieve the purpose of heat source dispersion, so that the upper limit of the resistance value of the resistor which can be prepared is increased, and the precision and the resistance value are considered and balanced.
Drawings
Fig. 1 shows a process flow of the chip resistor manufacturing of the invention.
Detailed Description
The technical solution of the present invention is further explained with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the method for manufacturing the chip resistor of the present invention includes the following steps:
1) The first insulating layer 2 is prepared on the top surface of the ceramic substrate 1, and the materials of the first insulating layer 2 and the later-described second insulating layer 5 are configured to be capable of being etched and have insulating properties, such as silicon nitride, and for the preparation manner of the insulating layer, as an example, the preparation process may be performed using a chemical vapor deposition process. After the first insulating layer 2 is prepared, a photoresist a is coated on the top surface thereof, and then exposure and development are performed, and the first insulating layer 2 is etched in combination to remove the first insulating layer 2 which is not covered by the photoresist a, and a first window 21 is formed in the center of the first insulating layer 2.
2) A first resistive layer is prepared by stripping the photoresist a on the first insulating layer 2 and then preparing the negative temperature coefficient of resistance material 3 within the first window 21.
3) Preparing a Cu layer 4 on the top surface of a semi-finished product after preparing the negative temperature coefficient resistance material 3 to be used as two-end electrodes, coating photoresist A on the top surface of the Cu layer 4, etching the Cu layer 4 after exposure and development to remove Cu4 which is not covered by the photoresist A, wherein the etched Cu layers are positioned at two ends of the top surface of the semi-finished product and extend from the top surface 3 of the negative temperature coefficient resistance material to the top surface 2 of the first insulating layer, and a second window 41 for preparing a second insulating layer 5 is formed between the Cu layers 4 at two ends of the top surface of the semi-finished product.
4) And preparing a second insulating layer, namely stripping the photoresist A on the Cu layer 4, and preparing a second insulating layer 5 in the second window 41.
5) And coating the photoresist A on the top surface of the semi-finished product after the second insulating layer 5 is prepared, and exposing and developing to form a third window, wherein the shape of the third window is the same as that of the first window 21 and the third window is positioned right above the first window 21.
6) And preparing a second resistance layer, and preparing a positive temperature coefficient resistance material 6 in a third window.
7) And stripping the photoresist, and preparing a protective film 7 for protecting the second resistance layer 6 on the top surface of the semi-finished product after the positive temperature coefficient resistor material is prepared, wherein the protective film 7 is preferably formed by printing paste and sintering, and the coverage area of the protective film 7 is configured to not completely cover the top surface of the Cu layer 4, so that the Cu layer 4 leaves an electrode with the exposed top surface for external electrical connection.
Through the above preparation method, the structure of the prepared chip resistor is shown as a final product in fig. 1, and the method comprises the following steps: a ceramic substrate 1; a first insulating layer 2 attached to the top surface of the ceramic substrate 1, the first insulating layer having a first window 21 formed in the center thereof for preparing a first resistance layer 3; a first resistance layer 3 filled in the first window 21 and configured as a negative temperature coefficient resistance material; the Cu layers 4 are positioned at two ends of the top surface of the semi-finished product after the negative temperature coefficient resistance material is prepared, extend from the top surface of the negative temperature coefficient resistance material to the top surface of the first insulating layer 2, and form a second window 41 for preparing a second insulating layer 5 between the Cu layers at two ends of the top surface of the semi-finished product; a second insulating layer 5 filled in the second window 41; a second resistance layer 6 prepared on the top surface of the semi-finished product after the second insulation layer 5 is prepared, the shape of the second resistance layer 6 is the same as that of the first resistance layer 3, the second resistance layer is positioned right above the first resistance layer 3, the bottom of the second resistance layer is electrically connected with the Cu layers 4 at the two ends respectively, and the second resistance layer 6 is configured to be a positive temperature coefficient resistance material; and the protective film 7 is covered on the top surface of the semi-finished product after the positive temperature coefficient resistance material is prepared, is used for protecting the second resistance layer 6 and does not completely cover the top surface of the Cu layer 4.
According to the resistor structure and the preparation method, on one hand, positive and negative counteractions of the positive and negative temperature coefficient resistor layers of the parallel structure on temperature change are utilized, so that the influence of temperature drift is reduced, and the improvement of the resistor precision is achieved; on the other hand, the positive and negative temperature coefficient resistor layers are configured to jointly clamp the electrodes to form a shunting effect as equal as possible, and the two resistor layers are separated by using the insulating layer to achieve the purpose of heat source dispersion, so that the upper limit of the resistance of the prepared resistor is increased, and the consideration and balance of precision and resistance are realized.
As an improvement, in the present invention, the negative temperature coefficient resistance material is configured as nickel, and during the preparation, a copper adhesion film is sputtered on the first window 21, wherein the thickness of the copper adhesion film can be controlled below 20nm, or 0-15nm, or 3-12nm, and preferably, the thickness of the copper adhesion film is configured to be 5-10nm so as to take into account the adhesion performance of the resistance layer based on nickel and the non-conductivity of the copper adhesion film. Then, the resistance layer 3 is prepared in the first window 21 by a chemical plating (nickel deposition) method, on one hand, the prepared resistance is relatively uniform in all positions in the window by the chemical plating method, and the precision of the resistance value of the product is improved, on the other hand, when the negative temperature coefficient resistance material is configured to be nickel, the nickel deposition process is assisted, so that the numerical value (upper limit) of the resistance which can be prepared under the condition of the same area can be improved, and the resistance value of the resistance is further increased.
Further, in the use of the nickel resistor, the ratio of the thickness of the copper adhesion film 2 to the thickness of the resistance layer 4 may be set to be at least less than 1.5x10 3 Further, the balance between the adhesion performance of the resistance layer 4 and the non-conductivity of the copper adhesion film 2 is achieved. Preferably, in order to make the top surface of the copper adhesion film more flush and provide a better platform for the adhesion of the resistor, the top surface of the copper film may be micro-etched by controlling the time using a chemical solution to perform leveling after sputtering the copper film.
On the basis that the negative temperature coefficient resistance material is configured to be nickel, the positive temperature coefficient resistance material can be configured to be manganese, the manganese can be attached to the second insulating layer 6 and the Cu layer 4 through a sputtering process, and the positive temperature coefficient resistance is prepared by the sputtering process due to the fact that the negative temperature coefficient resistance is prepared firstly (nickel deposition mode), and the positive temperature coefficient resistance is prepared through the sputtering process, so that the characteristic of accurate control of the resistance value of the sputtering process can be utilized, and accurate matching of parameters of the positive temperature coefficient resistance and the negative temperature coefficient resistance is achieved.
The above embodiments are merely some preferred embodiments of the present invention, and those skilled in the art can make various alternative modifications and combinations of the above embodiments based on the technical solution of the present invention and the related teaching of the above embodiments.
Claims (8)
1. A chip resistor with high power and high resistance precision is characterized by comprising:
a ceramic substrate;
the first insulating layer is attached to the top surface of the ceramic substrate, and a first window for preparing a first resistance layer is formed in the center of the first insulating layer;
a first resistance layer filled in the first window and configured as a negative temperature coefficient resistance material;
the Cu layers are positioned at two ends of the top surface of the semi-finished product after the negative temperature coefficient resistance material is prepared, extend from the top surface of the negative temperature coefficient resistance material to the top surface of the first insulating layer, and form a second window for preparing a second insulating layer between the Cu layers at two ends of the top surface of the semi-finished product;
a second insulating layer filled in the second window;
the second resistance layer is prepared on the top surface of the semi-finished product after the second insulating layer is prepared, the shape of the second resistance layer is the same as that of the first resistance layer, the second resistance layer is positioned right above the first resistance layer, the bottom of the second resistance layer is electrically connected with the Cu layers at the two ends respectively, and the second resistance layer is configured to be a positive temperature coefficient resistance material;
and the protective film covers the top surface of the semi-finished product after the positive temperature coefficient resistor material is prepared, is used for protecting the second resistor layer and does not completely cover the top surface of the Cu layer.
2. The chip resistor according to claim 1, wherein the material of the first resistance layer is nickel, and a copper adhesion film is sputtered between the bottom of the first resistance layer and the ceramic substrate.
3. The chip resistor as claimed in claim 2, wherein the material of the second resistance layer is configured as manganese.
4. The chip resistor according to claim 1, wherein the method of manufacturing the chip resistor further comprises:
1) Preparing a first insulating layer on the top surface of the ceramic substrate, coating photoresist on the top surface of the first insulating layer, exposing and developing, and etching the first insulating layer to remove the first insulating layer which is not covered by the photoresist and form a first window in the center of the first insulating layer;
2) Preparing a first resistance layer, stripping the photoresist, and preparing a negative temperature coefficient resistance material in a first window;
3) Preparing a Cu layer on the top surface of a semi-finished product after the negative temperature coefficient resistance material is prepared, coating photoresist on the top surface of the Cu layer, etching the Cu layer after exposure and development to remove the Cu layer which is not covered by the photoresist, wherein the etched Cu layer is positioned at two ends of the top surface of the semi-finished product and extends from the top surface of the negative temperature coefficient resistance material to the top surface of the first insulating layer, and a second window for preparing a second insulating layer is formed between the Cu layers at two ends of the top surface of the semi-finished product;
4) Stripping the photoresist, and preparing a second insulating layer in the second window;
5) Coating photoresist on the top surface of the semi-finished product after the second insulating layer is prepared, exposing and developing to form a third window, wherein the shape of the third window is the same as that of the first window and is positioned right above the first window;
6) Preparing a positive temperature coefficient resistance material in a third window;
7) And stripping the photoresist, and preparing a protective film for protecting the second resistance layer on the top surface of the semi-finished product after the positive temperature coefficient resistance material is prepared, wherein the protective film does not completely cover the top surface of the Cu layer.
5. The patch resistor of claim 4, wherein the negative temperature coefficient of resistance material is configured as nickel.
6. The chip resistor according to claim 5, wherein the negative temperature coefficient of resistance material is formed in a manner further comprising: sputtering a copper adhesion film on the first window, controlling the thickness of the copper adhesion film to make the copper adhesion film non-conductive, and then forming the negative temperature coefficient resistance material in the first window through chemical deposition of a nickel deposition process.
7. The chip resistor according to claim 6, wherein the thickness of the copper adhesion film is configured to be 5-10nm.
8. A patch resistor according to claim 4, wherein the positive temperature coefficient resistance material is configured as manganese and is attached to the second insulating layer and the Cu layer by a sputtering process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211234181.5A CN115662715A (en) | 2022-10-10 | 2022-10-10 | Chip resistor with high power and high resistance precision |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211234181.5A CN115662715A (en) | 2022-10-10 | 2022-10-10 | Chip resistor with high power and high resistance precision |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115662715A true CN115662715A (en) | 2023-01-31 |
Family
ID=84987532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211234181.5A Withdrawn CN115662715A (en) | 2022-10-10 | 2022-10-10 | Chip resistor with high power and high resistance precision |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115662715A (en) |
-
2022
- 2022-10-10 CN CN202211234181.5A patent/CN115662715A/en not_active Withdrawn
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Application publication date: 20230131 |
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