CN115657788A - High-speed multiphase clock generation circuit, serializer and electronic equipment - Google Patents
High-speed multiphase clock generation circuit, serializer and electronic equipment Download PDFInfo
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Abstract
The invention provides a high-speed multiphase clock generating circuit, a serializer and electronic equipment, wherein the high-speed multiphase clock generating circuit comprises a frequency multiplication phase generating module and a multiphase clock recombination module which are electrically connected; the frequency multiplication phase generation module receives a plurality of base frequency clock signals and carries out first processing on the base frequency clock signals in groups to form at least two groups of frequency multiplication phase signal groups; the multiphase clock recombination device receives the frequency multiplication phase signals in at least two groups of frequency multiplication phase signal groups and performs grouping recombination and compensation on the frequency multiplication phase signals, and further the effective signal time of the high-speed clock signals in each group is larger than the effective signal time of the corresponding frequency multiplication phase signals for recombination. Therefore, the high-speed clock signal can not only support high-speed application, but also solve the problem of poor signal transmission quality caused by time delay brought by a frequency multiplication phase generation module.
Description
Technical Field
The invention relates to the field of semiconductor chips, in particular to a high-speed multiphase clock generating circuit, a serializer and electronic equipment.
Background
In recent years, a high-speed serial communication technology is widely applied to the field of high-speed data communication, particularly to the fields of optical fiber data transmission, short-distance chip interconnection and the like, and the transmission speed of the high-speed serial communication technology is far higher than that of the traditional parallel communication technology.
Currently, high-speed serial interfaces, including USB, RJ45 interfaces, serial ports of switches, etc., are widely used in devices and systems requiring high-speed data exchange, where the performance of a serializer in a transmitting end of the high-speed serial interface is a key for realizing high-speed data transmission.
The conventional serializer needs to use a multi-phase clock with the same frequency, the phase difference between two adjacent clock signals is the same, the two adjacent clock signals are subjected to logic operation through a transmission gate to obtain a plurality of non-overlapped signals, the signals are input to a required device, and the required device triggers to work by using the jumping edge of the signals.
However, when the clock signal is logically operated through the transmission gate, the output signal has a transmission delay due to the speed limitation and the circuit topology limitation of the standard cell. In this case, the output frequency-doubled phase signal changes slowly along the edge, and the effective signal time is short, so that inputting such a signal to the desired device may cause data sampling errors of the desired device.
Disclosure of Invention
The invention provides a high-speed multiphase clock generating circuit, a serializer and electronic equipment, which are used for solving the technical problem that a clock signal cannot meet the requirement of high-speed application and simultaneously influence caused by time delay is effectively reduced.
According to a first aspect of the present invention, a high-speed multiphase clock generating circuit is provided, which includes a frequency-doubling phase generating module and a multiphase clock recombining module electrically connected to each other; wherein:
the frequency doubling phase generation module is used for receiving a plurality of base frequency clock signals and grouping the base frequency clock signals for first processing to form at least two groups of frequency doubling phase signal groups, each group of frequency doubling phase signal group comprises a plurality of frequency doubling phase signals, and at least two groups of frequency doubling phase signals between the frequency doubling phase signal groups are opposite phase signals which are in one-to-one correspondence with each other; wherein the first processing comprises duty cycle processing to make the duty cycle of the multiplied phase signal smaller than the duty cycle of the corresponding fundamental frequency clock signal; the phases of the plurality of fundamental frequency clock signals are different, and the phases of the plurality of frequency multiplication phase signals included in each group of frequency multiplication phase signal groups are different;
the multiphase clock recombination module is used for receiving the frequency multiplication phase signals in the at least two groups of frequency multiplication phase signal groups, performing grouping recombination on the received frequency multiplication phase signals, and prolonging the effective signal time of the frequency multiplication phase generation module to form a plurality of groups of high-speed clock signal groups, wherein each group of high-speed clock signal groups at least comprises two high-speed clock signals with opposite phases, and the phases of the high-speed clock signals in different groups are different.
Optionally, the grouping and recombining the received frequency-doubled phase signals specifically includes:
for two high-speed clock signals in the ith group of high-speed clock signal groups, the ith-1 frequency multiplication phase signal of the 1 st group and the ith frequency multiplication phase signal of the 2 nd group in two groups of frequency multiplication phase signal groups of opposite-phase signals which are mutually corresponding one to one are adopted as the frequency multiplication phase signal for recombination of one high-speed clock signal; the ith frequency multiplication phase signal of the 1 st group and the (i-1) th frequency multiplication phase signal of the 2 nd group are used as the frequency multiplication phase signals of the other high-speed clock signal for recombination; sequencing all frequency multiplication phase signals in the 1 st group and all frequency multiplication phase signals in the 2 nd group according to phase sizes; the total number of the high-speed clock signal groups is N, the number of the frequency multiplication phase signals of the 1 st group and the 2 nd group is M respectively, i, N and M are positive integers, and i is not less than 1,N but not less than 2,M but not less than N is not less than i.
Optionally, the multiphase clock recombination module includes N groups of gating signal unit groups, where each group of gating signal unit groups includes two logic gate circuit units;
a logic gate circuit unit in the ith gating signal unit group is used for receiving the (i-1) th frequency multiplication phase signal of the 1 st group and the (i) th frequency multiplication phase signal of the 2 nd group, and performing logic combination on the (i-1) th frequency multiplication phase signal of the 1 st group and the (i) th frequency multiplication phase signal of the 2 nd group to output a high-speed clock signal in the ith high-speed clock signal group;
and the other logic gate circuit unit in the ith gating signal unit group is used for receiving the ith frequency multiplication phase signal of the 1 st group and the ith-1 frequency multiplication phase signal of the 2 nd group, logically combining the ith frequency multiplication phase signal of the 1 st group and the ith-1 frequency multiplication phase signal of the 2 nd group and outputting the other high-speed clock signal in the ith high-speed clock signal group.
Optionally, the 1 st multiplied phase signal in the 1 st group and the 2 nd group is respectively overlapped with the nth multiplied phase signal in the same group.
Optionally, the logic gate circuit unit is a CMOS single-tube logic gate circuit, and the CMOS single-tube logic gate circuit includes: the source electrode of the PMOS transistor is connected with a power supply end, the drain electrode of the PMOS transistor is connected with the drain electrode of the NMOS transistor, and the source electrode of the NMOS transistor is grounded; the grid electrode of the PMOS transistor is used for connecting a negative phase signal in the two corresponding frequency doubling phase signals, and the grid electrode of the NMOS transistor is used for connecting a positive phase signal in the two corresponding frequency doubling phase signals; and the drain electrode of the PMOS transistor is used as the output end of the CMOS single-tube logic gate circuit and is used for outputting a corresponding high-speed clock signal.
Optionally, the duty ratio of the high-speed clock signal is 1/N.
Optionally, the frequency multiplication phase generation module includes at least two groups of logic gate units, where each group of logic gate units includes N logic gate units;
the logic gate unit is configured to: receiving at least two different phase clock signals, and outputting corresponding frequency multiplication phase signals by using a circuit delay mode;
and the frequency multiplication phase signals output by the corresponding logic gate units in the two groups of logic gate unit groups are mutually opposite signals corresponding to each other.
Optionally, the logic gate units in one of the logic gate unit groups are nand gate logic gates, and the logic gate units in the other logic gate unit group are nor gate logic gates.
Optionally, the first processing further includes frequency doubling ratio processing, so that the frequency of the frequency-doubled phase signal is greater than the frequency of the corresponding fundamental frequency clock signal.
Optionally, the apparatus further includes a baseband clock module, where the baseband clock module is configured to generate a plurality of baseband clock signals with different phases according to an initial clock signal.
Optionally, the frequencies of the plurality of base frequency clock signals are the same.
Optionally, the frequency of the high-speed clock signal in each group is greater than or equal to the frequency of the corresponding multiplied-frequency phase signal for recombination.
According to a second aspect of the present invention, there is provided a serializer comprising the high-speed multiphase clock generating circuit provided in any one of the first aspects of the present invention and a high-speed data strobe device;
the high-speed multiphase clock generating circuit is electrically connected with the high-speed data gating device;
the high-speed data gating device comprises a plurality of data gating units, wherein each data gating unit comprises a control end; the control ends of all the data gating units receive one group of high-speed clock signal groups in a plurality of groups of high-speed clock signal groups generated by the high-speed multiphase clock generating circuit in sequence according to the address bit sequence; the input ends of all the data gating units receive a specific data bit of the parallel data in sequence according to the order of the address bits; each data gating unit is gated or closed under the control of two high-speed clock signals with opposite phases of the corresponding high-speed clock signal group so as to sequentially transmit corresponding data bits; the sequencing of the high-speed clock signal groups is carried out according to the phase size.
Optionally, the data gating unit is a CMOS transmission gate, wherein a positive phase signal of two high-speed clock signals with opposite phases in the corresponding high-speed clock signal group is input to a positive control terminal of the CMOS transmission gate, and a negative phase signal of the two high-speed clock signals with opposite phases is input to a negative control terminal of the CMOS transmission gate.
According to a third aspect of the present invention, there is provided an electronic device comprising the serializer provided in any one of the second aspects of the present invention.
The high-speed multiphase clock generating circuit provided by the invention comprises a frequency multiplication phase generating module and a multiphase clock recombination module which are electrically connected; the frequency multiplication phase generation module receives a plurality of base frequency clock signals and carries out first processing on the base frequency clock signals in groups to form at least two groups of frequency multiplication phase signal groups; the multiphase clock recombination device receives the frequency multiplication phase signals in at least two groups of frequency multiplication phase signal groups and performs grouping recombination and compensation on the frequency multiplication phase signals, and further the effective signal time of the high-speed clock signals in each group is larger than the effective signal time of the corresponding frequency multiplication phase signals for recombination. Therefore, the high-speed clock signal can not only support high-speed application, but also solve the time delay caused by a frequency multiplication phase generation module.
The control ends of all data gating units of the high-speed data gating device sequentially receive one group of high-speed clock signal groups in a plurality of groups of high-speed clock signal groups generated by the high-speed multiphase clock generating circuit according to an address bit sequence, and the input end of the high-speed data gating device sequentially receives a specific data bit of parallel data according to the address bit sequence; each data gating unit is gated or closed under the control of two high-speed clock signals with opposite phases of the corresponding high-speed clock signal group so as to sequentially transmit corresponding data bits; thereby enabling the serializer to realize high-speed serial transmission of data; and because the high-speed clock signal generated by the high-speed multiphase clock generating circuit of the invention is subjected to delay compensation, the effective signal time is widened, thereby ensuring the quality of signal transmission.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a high-speed multiphase clock generation circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a frequency multiplication phase generation module according to an embodiment of the present invention;
FIG. 3 is a first schematic diagram of a multiphase clock reassembly module according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram of the multiphase clock reassembly module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the serializer configuration in an embodiment of the invention;
FIG. 6 is a schematic circuit diagram of a high-speed data strobe apparatus according to an embodiment of the present invention;
fig. 7 is a timing diagram illustrating the operation of the serializer according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, circuit, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
In view of the prior art that in the process of carrying out logic processing on clock signals through a transmission gate, the clock signals cannot meet high-speed application and effectively reduce the influence caused by time delay, the invention provides a high-speed multiphase clock generating circuit, which comprises a frequency multiplication phase generating module and a multiphase clock recombination module which are electrically connected; the frequency multiplication phase generation module receives a plurality of base frequency clock signals and carries out first processing on the base frequency clock signals in groups to form at least two groups of frequency multiplication phase signal groups; the multiphase clock recombination device receives the frequency multiplication phase signals in at least two groups of frequency multiplication phase signal groups, and performs grouping recombination and compensation on the frequency multiplication phase signals, so that the effective signal time of the high-speed clock signals in each group is longer than the effective signal time of the corresponding frequency multiplication phase signals for recombination. Therefore, the high-speed clock signal can not only support high-speed application, but also solve the time delay caused by a frequency multiplication phase generation module.
Referring to fig. 1, an embodiment of the invention provides a high-speed multiphase clock generating circuit, which includes a frequency-doubling phase generating module 11 and a multiphase clock recombining module 12 electrically connected to each other; wherein:
the frequency doubling phase generation module 11 is configured to receive a plurality of base frequency clock signals, and perform first processing on the base frequency clock signals in groups to form at least two groups of frequency doubling phase signal groups, where each group of frequency doubling phase signal group includes a plurality of frequency doubling phase signals, and at least two groups of frequency doubling phase signals between the frequency doubling phase signal groups are inverted signals corresponding to each other one to one; wherein the first processing comprises duty cycle processing to make the duty cycle of the multiplied phase signal smaller than the duty cycle of the corresponding fundamental frequency clock signal; the phases of the plurality of fundamental frequency clock signals are different, and the phases of the plurality of frequency multiplication phase signals included in each group of frequency multiplication phase signal groups are different;
the multiphase clock recombination module 12 is configured to receive the multiplied frequency phase signals in the at least two groups of multiplied frequency phase signal groups, and perform grouping recombination on the received multiplied frequency phase signals to form multiple groups of high-speed clock signal groups, where each group of high-speed clock signal groups at least includes two high-speed clock signals with opposite phases, the effective signal time of the high-speed clock signal in each group is longer than the effective signal time of the corresponding multiplied frequency phase signal for recombination, and the phases of the high-speed clock signals in different groups are different.
And the frequency of the high-speed clock signal in each group is greater than or equal to the frequency of the corresponding frequency multiplication phase signal for recombination.
In a preferred embodiment, the high-speed multi-phase clock generating circuit may further include a baseband clock module, and the baseband clock module is configured to generate a plurality of baseband clock signals with different phases according to an initial clock signal. Further, the frequencies of the plurality of fundamental frequency clock signals generated by the fundamental frequency clock module may be the same, in this case, the multiplied phase signals may all be equal-width non-overlapping signals, wherein the equal-width signals may be understood as that the sum of the rise time, the effective signal time and the fall time of all the signals in the multiplied phase signal group is equal; non-overlapping signals are understood to mean that the sum of the rise time, the effective signal time and the fall time of all signals in the set of frequency multiplied phase signals is the time of one period of the fundamental frequency clock signal.
In one example, the frequency multiplication phase generation module 11 includes at least two groups of logic gate units, where each group of logic gate units includes N logic gate units;
the logic gate unit is used for: receiving at least two different phase clock signals, and outputting corresponding frequency multiplication phase signals by using a circuit delay mode;
and the frequency multiplication phase signals output by the corresponding logic gate units in the two groups of logic gate unit groups are inverse signals which are in one-to-one correspondence with each other.
In the example shown in fig. 2, two sets of logic gate units are exemplified. The logic gate units in the first group of logic gate unit groups 111 are nand gate logic gates, and the logic gate units in the second group of logic gate unit groups 112 are nor gate logic gates. Fig. 2 shows that each logic gate unit group includes 4 logic gate units, for example, the first logic gate unit group 111 includes 4 nand gate units, which are a first nand gate 1111, a second nand gate 1112, a third nand gate 1113, and a fourth nand gate 1114 respectively; the second set of logic gate unit 112 includes 4 nor gate logic gates, which are a first nor gate logic gate 1121, a second nor gate logic gate 1122, a third nor gate logic gate 1123, and a fourth nor gate logic gate 1124, respectively. The phase difference between adjacent baseband clock signals is 90 degrees, and sequentially CLK0, CLK90, CLK180, CLK270, and CLK360 (CLK 360 is substantially the same as CLK0, and CLK360 is replaced by CLK0 in fig. 2).
The fundamental frequency clock signals received by the first nand gate 1111 are CLK90 and CLK180, the 0 th negative-phase multiplied phase signal formed by the first nand gate 1111 is denoted as PL0 (since the phase of the fundamental frequency clock signal starts from 0, the numbering of the multiplied phase signals also starts from the 0 th in order to correspond to the phase), the fundamental frequency clock signals received by the first and gate 1121 are CLK0 and CLK270, and the 0 th positive-phase multiplied phase signal formed by the first and gate 1121 is denoted as PH0; the 0 th negative-phase multiplied frequency phase signal PL0 and the 0 th positive-phase multiplied frequency phase signal PH0 are inverse signals, and the inverse signals can be understood as that the phase difference of the multiplied frequency phase signals output by the corresponding logic gate units in the two groups of logic gate units is 180 °, and when one of the multiplied frequency phase signals is at a high level, the other multiplied frequency phase signal is at a low level.
Similarly, the 1 st negative-phase multiplied phase signal PL1 and the 1 st positive-phase multiplied phase signal PH1, the 2 nd negative-phase multiplied phase signal PL2 and the 2 nd positive-phase multiplied phase signal PH2, and the 3 rd negative-phase multiplied phase signal PL3 and the 3 rd positive-phase multiplied phase signal PH3 are all inverted signals in one-to-one correspondence. And PL0, PL1, PL2, PL3 differ in phase from one another, and PH0, PH1, PH2, PH3 differ in phase from one another.
Of course, the present invention is not limited thereto, and in other examples, the multiplied-frequency phase generating module may also select other logic gate units, for example, an exclusive or gate and an inverter as logic gate units for processing two different phase clock signals. Moreover, the phase difference between adjacent baseband clock signals is not necessarily 90 degrees, but may also differ by other values, such as 60 degrees.
As a preferred embodiment, the first processing performed by the multiplied-frequency phase generating module 11 on the plurality of baseband clock signal groups further includes frequency multiplication processing, so that the frequency of the multiplied-frequency phase signal is greater than the frequency of the corresponding baseband clock signal. For example, the frequency multiplication phase generation module 11 may include a phase-locked loop circuit, and the frequency multiplication of the baseband clock signal is implemented by inputting the baseband clock signal into the phase-locked loop circuit; the frequency multiplication phase generation module 11 may further include a non-linear device, and the frequency multiplication of the baseband clock signal is implemented by inputting the baseband clock signal to the non-linear device.
When the clock signal is logically operated through the transmission gate, the output signal has transmission delay due to the speed limit and the circuit topology structure limit of the standard unit. In this case, the output frequency-doubled phase signal changes slowly along the edge, and the effective signal time is short, and the signal sampling is performed by using this signal as a clock signal, which reduces the accuracy of data sampling.
Therefore, the present invention performs grouping and recombination on the frequency-multiplied phase signals in the multiphase clock recombination module 12 to form a plurality of groups of high-speed clock signal groups, and replaces the frequency-multiplied phase signals with the same phase with the high-speed clock signals to be transmitted as actual clock signals to subsequent devices for further processing.
The multiphase clock restructuring module 12 is specifically described as follows:
in one example, the grouping and recombining are performed on the received frequency-doubled phase signals, specifically:
for two high-speed clock signals in the ith group of high-speed clock signal groups, the ith-1 frequency multiplication phase signal of the 1 st group of frequency multiplication phase signal group and the ith frequency multiplication phase signal of the 2 nd group of frequency multiplication phase signal group which are anti-phase signals corresponding to each other one by one are adopted as the frequency multiplication phase signals for recombination of one high-speed clock signal; the ith frequency multiplication phase signal of the 1 st group of frequency multiplication phase signal group and the (i-1) th frequency multiplication phase signal of the 2 nd group of frequency multiplication phase signal group are used as the frequency multiplication phase signals for recombination of another high-speed clock signal; all frequency multiplication phase signals in the 1 st group of frequency multiplication phase signal group and all frequency multiplication phase signals in the 2 nd group of frequency multiplication phase signal group are sequenced according to the phase size; the total number of the high-speed clock signal groups is N groups, the number of the frequency multiplication phase signals of the 1 st group and the 2 nd group is M respectively, i, N and M are positive integers, and i is not less than 1,N not less than 2,M not less than N not less than i.
As an embodiment, the multiphase clock reassembly module 12 includes N groups of strobe signal cells, each group of strobe signal cells including two logic gate circuit cells;
the first logic gate circuit unit in the ith gating signal unit group is used for receiving the (i-1) th frequency multiplication phase signal of the 1 st group and the (i) th frequency multiplication phase signal of the 2 nd group, and performing logic combination on the (i-1) th frequency multiplication phase signal of the 1 st group and the (i) th frequency multiplication phase signal of the 2 nd group to output one high-speed clock signal in the ith high-speed clock signal group;
and the second logic gate circuit unit in the ith gating signal unit group is used for receiving the ith frequency multiplication phase signal of the 1 st group and the ith-1 frequency multiplication phase signal of the 2 nd group, logically combining the ith frequency multiplication phase signal of the 1 st group and the ith-1 frequency multiplication phase signal of the 2 nd group and outputting another high-speed clock signal in the ith high-speed clock signal group.
In one embodiment, please refer to FIG. 3, as shown in FIG. 3, the total number of the high-speed clock signal groups is n groups, n is a positive integer and n ≧ 2; correspondingly, the multiphase clock recombination module 12 includes n groups of gating signal unit groups, each group of gating signal unit group includes two logic gate circuit units, which are denoted as a first logic gate circuit unit 121 and a second logic gate circuit unit 122; and as an example, the first and second logic gate circuit units 121 and 122 are each a CMOS single-tube logic gate circuit.
Specifically, as shown in fig. 3, each CMOS single-tube logic gate circuit includes a PMOS transistor and an NMOS transistor; the source electrode of the PMOS transistor is connected with a power supply end, the drain electrode of the PMOS transistor is connected with the drain electrode of the NMOS transistor, and the source electrode of the NMOS transistor is grounded; the grid electrode of the PMOS transistor is used for connecting a negative phase signal in the two corresponding frequency doubling phase signals, and the grid electrode of the NMOS transistor is used for connecting a positive phase signal in the two corresponding frequency doubling phase signals; and the drain electrode of the PMOS transistor is used as the output end of the CMOS single-tube logic gate circuit and is used for outputting a corresponding high-speed clock signal.
As shown in fig. 3, taking the group 1 gating signal unit as an example, the gate of the PMOS transistor in the first logic gate circuit unit 121 is connected to the 1 st negative phase multiplied phase signal PL1, the gate of the NMOS transistor is connected to the 0 th positive phase multiplied phase signal PH0, and the output end of the NMOS transistor is used for outputting the first high-speed clock signal TGP1 in the group 1 high-speed clock signal group; the gate of the PMOS transistor in the second logic gate circuit unit 122 is connected to the 0 th negative phase multiplied phase signal PL0, the gate of the NMOS transistor thereof is connected to the 1 st positive phase multiplied phase signal PH1, and the output end thereof is used for outputting the second high-speed clock signal TGN1 in the 1 st group of high-speed clock signal group; the 1 st negative-phase multiplied phase signal PL1 and the 0 th negative-phase multiplied phase signal PL0 are negative phase signals, the 0 th positive-phase multiplied phase signal PH0 and the 1 st positive-phase multiplied phase signal PH1 are positive phase signals, and the timings of PH0 and PL0 are earlier than the timings of PL1 and PH1, respectively. The first high-speed clock signal TGP1 and the second high-speed clock signal TGN1 in the 1 st group of high-speed clock signal groups are inverse signals. It can be understood that, for the first group of high-speed clock signal groups, the delay problem of the first high-speed clock signal TGP1 can be compensated by selecting the 0 th positive-phase multiplied-frequency phase signal PH0 at the previous time and the 1 st negative-phase multiplied-frequency phase signal PL1 at the current time as the trigger signals of the first logic gate circuit unit 121; the same is true for the second high-speed clock signal TGN 1.
The working principle of the CMOS single-tube logic gate circuit is described as follows:
taking the group 1 gating signal unit group as an example, for the first logic gate circuit unit 121, if the 1 st negative-phase multiplied frequency phase signal PL1 is an effective low-level signal, since the 0 th positive-phase multiplied frequency phase signal PH0 is an inverted signal of the 1 st negative-phase multiplied frequency phase signal PL1 at the previous time, the 0 th positive-phase multiplied frequency phase signal PH0 is also an effective low-level signal, in which case the corresponding PMOS transistor is turned on, and the corresponding NMOS transistor is turned off, so that the first high-speed clock signal TGP1 is at a high level; if the 0 th positive phase multiplied frequency phase signal PH0 is an effective high level signal, since the 1 st negative phase multiplied frequency phase signal PL1 is an inverted signal at a later time of the 0 th positive phase multiplied frequency phase signal PH0, the 1 st negative phase multiplied frequency phase signal PL1 is also an effective high level signal, in which case the corresponding PMOS transistor is turned off and the corresponding NMOS transistor is turned on, so that the first high speed clock signal TGP1 becomes a low level; the instant of the level transition of the first high-speed clock signal TGP1 is approximately the time point when the multiplied phase signal at the current time (i.e., the 1 st negative-phase multiplied phase signal PL 1) starts to fall, so the phase of the output first high-speed clock signal TGP1 is the same as or close to the phase of the multiplied phase signal at the current time. Otherwise, the first high-speed clock signal TGP1 maintains the current state. Similarly, the same principle applies to the second logic gate circuit unit 122.
Since the CLK360 is substantially the same as the CLK0, the 0 th multiplied phase signals in the 1 st group and the 2 nd group are respectively overlapped with the nth multiplied phase signals in the same group. In the example shown in fig. 4, taking 4 groups of gate signal unit groups as an example, the 0 th negative phase multiplied phase signal PL0 is the same as the 4 th negative phase multiplied phase signal PL4, and the 0 th positive phase multiplied phase signal PH0 is the same as the 4 th positive phase multiplied phase signal PH4. Thus, in the 4 th group gate signal unit group, the 4 th negative-phase multiplied phase signal PL4 is replaced with the 0 th negative-phase multiplied phase signal PL0, and the 4 th positive-phase multiplied phase signal PH4 is replaced with the 0 th positive-phase multiplied phase signal PH 0.
A fixed delay time exists between effective signals of two frequency multiplication phase signals received by each logic gate circuit unit, for example, a fixed delay time exists between PL1 and PH0; the effective time length of the signal output after passing through the CMOS single-tube logic gate circuit is approximately equal to the fixed delay time, and the fixed delay time is the same as the sum of the rising time, the effective signal time and the falling time of the frequency doubling phase signal, so that the effective signal time of the high-speed clock signal in each group is greater than the effective signal time of the corresponding frequency doubling phase signal for recombination, and the frequency of the high-speed clock signal is equal to the frequency of the corresponding frequency doubling phase signal for recombination.
And the ideal duty ratio of the output high-speed clock signals is 1/N, wherein the number of N is the total number of the high-speed clock signal groups. As a preferred embodiment, the total number of high speed clock signal groups may be 4, so that the desired duty cycle of the high speed clock signal is 25%.
The CMOS single-tube logic is selected because the CMOS single-tube logic has the characteristics of high speed, low power consumption, small area and the like, and the defect that the traditional logic gate based on a standard cell library has low speed and large power consumption area consumption is overcome, so that the edge change of the output high-speed clock signal is high. It should be appreciated, of course, that the CMOS single-tube logic is only a preferred way of the present invention, and those skilled in the art can set different circuit elements according to practical situations, and it is within the protection scope of the present invention as long as the high-speed clock signal output by the circuit element changes rapidly along the edge, so that the effective signal time of the high-speed clock signal in each group is greater than the effective signal time of the corresponding multiplied phase signal for recombination.
In addition, an embodiment of the present invention further provides a serializer, please refer to fig. 5, which includes the high-speed multi-phase clock generating circuit and the high-speed data strobe device 13;
the high-speed multiphase clock generating circuit is electrically connected with the high-speed data gating device 13;
the high-speed data strobe apparatus 13 includes a plurality of data strobe units 131, each data strobe unit 131 including a control terminal; the control terminals of all the data strobe units 131 sequentially receive one high-speed clock signal group of the multiple high-speed clock signal groups generated by the high-speed multiphase clock generation circuit according to the address bit sequence; and the input terminals of all the data strobe units 131 receive a specific data bit of the parallel data in sequence according to the address bit sequence; each data gating unit 131 gates or turns off under the control of two high-speed clock signals with opposite phases of the corresponding high-speed clock signal group to sequentially transmit corresponding data bits; the sequencing of the high-speed clock signal groups is carried out according to the phase size.
The high-speed clock signal generated by the high-speed multiphase clock generating circuit is subjected to delay compensation, so that the effective signal time is widened, and the quality of signal transmission is ensured.
In one embodiment, as shown in fig. 6, the data strobe unit 131 is a CMOS transmission gate, wherein the positive phase signal of the two high-speed clock signals with opposite phases in the corresponding high-speed clock signal group is input to the positive control terminal (i.e., the gate of the NMOS) of the CMOS transmission gate, and the negative phase signal is input to the negative control terminal (i.e., the gate of the PMOS) of the CMOS transmission gate. When the voltage difference between the two input high-speed clock signals with opposite phases reaches a preset voltage value, single-bit data of corresponding data bits are transmitted.
As shown in FIG. 6, taking n-bit data transmission as an example, the least significant bit d1 of the input data corresponds to the first data strobe unit, and the nth bit dn of the input data corresponds to the nth data strobe unit. Taking the first data gating unit as an example, the first high-speed clock signal TGP1 in the 1 st group of high-speed clock signal groups is input to the negative control terminal of the CMOS transmission gate, the second high-speed clock signal TGN1 in the 1 st group of high-speed clock signal groups is input to the positive control terminal of the CMOS transmission gate, when the voltage difference between the positive control terminal and the negative control terminal is positive (i.e., TGN1 is high level, and TGP1 is low level), the CMOS transmission gate is turned on to transmit the corresponding data bit, and when the voltage difference between the pole control terminal and the negative control terminal is negative (i.e., TGN1 is low level, and TGP1 is high level), the CMOS transmission gate is turned off to not transmit the corresponding data bit. The same is true for the other data strobe units, which convert the parallel data into a high speed single bit data output dout.
The working principle of the serializer described in fig. 5 is described in detail below with reference to the timing diagram shown in fig. 7:
assuming that the fundamental phase clock signals are characterized by square waves, inputting the fundamental four-phase clock signals of CLK0, CLK90, CLK180 and CLK270 to the multiplied phase generation module 11, wherein the CLK90 is phase-shifted by 90 degrees from the CLK180, the CLK180 is phase-shifted by 90 degrees from the CLK270, the CLK0 (i.e., CLK 360) is phase-shifted by 90 degrees from the CLK270, and the CLK0 is phase-shifted by 90 degrees from the CLK 90;
each not gate logic gate and not gate logic gate in the frequency multiplication phase generation module 11 respectively and correspondingly receive two different fundamental frequency clock signals with a phase difference of 90 degrees, and sequentially output two groups of frequency multiplication phase signal groups according to the phase difference after processing, the frequency multiplication phase signals in the frequency multiplication phase signal groups are equal-width non-overlapped signals, the waveform of the frequency multiplication phase signals is slowed down due to delay after passing through the logic gates, wherein the 1 st group in the frequency multiplication phase signal groups comprises four frequency multiplication phase signals of PH 0-PH 3, the 2 nd group in the frequency multiplication phase signal groups comprises four frequency multiplication phase signals of PL 0-PL 3, the frequency multiplication phase signals between the two groups of frequency multiplication phase signal groups are mutually reverse phase signals in one-to-one correspondence, and the sum of the rise time, the effective signal time and the fall time of all the fundamental frequency signals in the frequency multiplication phase signal groups is the time of one period of the clock signals; the frequency multiplication phase signal shown in fig. 7 is simplified and illustrated as a triangular wave signal, and for the triangular wave signal, the effective signal time corresponds to one point (i.e., a vertex);
after the corresponding frequency doubling phase signals in the two groups of frequency doubling phase signal groups pass through the CMOS single-tube logic gate circuit, the rising edge of the previous frequency doubling phase signal in one group of positive phase signals and the falling edge of the current frequency doubling phase signal in the other group of negative phase signals are respectively used as the rising edge and the falling edge to form the current high-speed clock signal, and the corresponding high-speed clock signal is a square-wave signal; wherein, the high-speed clock signals are specifically TGN1-TGN4 and TGP1-TGP4; compared with the fundamental frequency phase clock signal, the duty ratio of the high-speed clock signal is obviously reduced, so that the high-speed clock signal can support high-speed transmission; in addition, the rising edge of the previous frequency doubling phase signal and the falling edge of the current frequency doubling phase signal in the other group of negative phase signals are respectively used as the rising edge and the falling edge, so that the problem of time delay caused by each circuit module can be effectively solved;
a first high-speed clock signal TGP1 in a 1 st group of high-speed clock signal groups is input to a negative control end of a first data gating unit (CMOS transmission gate), and a second high-speed clock signal TGN1 in the 1 st group of high-speed clock signal groups is input to a positive control end of the first data gating unit (CMOS transmission gate); when the active signal of the first high-speed clock signal TGP1 is at a low level and the active signal of the second high-speed clock signal TGN1 is at a high level, the first data strobe unit of the high-speed data strobe device 13 is turned on, and the data (specifically, a) corresponding to the least significant bit D1 of the input data is output by the first data strobe unit. Similarly, the data (specifically B) corresponding to the second bit D2 of the input data, the data (specifically C) corresponding to the third bit D3 of the input data, and the data (specifically D) corresponding to the fourth bit D4 of the input data are output by the second data strobe unit, the third data strobe unit, and the fourth data strobe unit, respectively.
It should be understood that the waveform of the frequency-doubled phase signal in the timing diagram shown in fig. 7 is merely an illustration, and the effective signal time is simplified to be the top of the waveform; the actual multiplied phase signal may be a trapezoidal wave signal or other form of signal. Any time point in the effective signal time of the frequency-multiplied phase signal can be set as the basis for the edge conversion of the high-speed clock signal output by the multiphase clock recombination module 12.
It should be understood that the delay time between the signals having trigger relationship is not an exact value, and the delay time between the transition time point of the edge of the multiplied phase signal and the transition time point of the corresponding output high-speed clock signal is only an illustration.
In addition, the embodiment of the invention also provides electronic equipment comprising the serializer. By way of example, the device may be a USB interface, an RJ45 interface, a serial port of a switch, and the like, and may be applied to other devices and systems requiring high-speed data exchange.
In summary, the present invention includes an electrically connected frequency-doubling phase generation module and a multiphase clock recombination module; the frequency multiplication phase generation module receives a plurality of base frequency clock signals and carries out first processing on the base frequency clock signals in groups to form at least two groups of frequency multiplication phase signal groups; and the multiphase clock recombination device receives the frequency multiplication phase signals in at least two groups of frequency multiplication phase signal groups and performs grouping recombination and compensation on the frequency multiplication phase signals, and further the effective signal time of the high-speed clock signals in each group is greater than the effective signal time of the corresponding frequency multiplication phase signals for recombination. Therefore, the high-speed clock signal can not only support high-speed application, but also solve the problem of poor signal transmission quality caused by time delay brought by a frequency multiplication phase generation module.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. A high-speed multiphase clock generating circuit is characterized by comprising a frequency multiplication phase generating module and a multiphase clock recombination module which are electrically connected; wherein:
the frequency doubling phase generation module is used for receiving a plurality of base frequency clock signals and grouping the base frequency clock signals for first processing to form at least two groups of frequency doubling phase signal groups, each group of frequency doubling phase signal group comprises a plurality of frequency doubling phase signals, and at least two groups of frequency doubling phase signals between the frequency doubling phase signal groups are opposite phase signals which are in one-to-one correspondence with each other; wherein the first processing comprises duty cycle processing to make the duty cycle of the multiplied phase signal smaller than the duty cycle of the corresponding fundamental frequency clock signal; the phases of the plurality of fundamental frequency clock signals are different, and the phases of the plurality of frequency multiplication phase signals included in each group of frequency multiplication phase signal groups are different;
the multiphase clock recombination module is used for receiving the frequency multiplication phase signals in the at least two groups of frequency multiplication phase signal groups, performing grouping recombination on the received frequency multiplication phase signals, and compensating the frequency multiplication phase signals to form a plurality of groups of high-speed clock signal groups, wherein each group of high-speed clock signal groups at least comprises two high-speed clock signals with opposite phases, and the phases of the high-speed clock signals in different groups are different.
2. A high-speed multiphase clock generation circuit according to claim 1, wherein the grouping and recombining of the received multiplied phase signals is specifically:
for two high-speed clock signals in the ith group of high-speed clock signal groups, the ith-1 frequency multiplication phase signal of the 1 st group and the ith frequency multiplication phase signal of the 2 nd group in two groups of frequency multiplication phase signal groups which are opposite phase signals corresponding to each other one to one are adopted as the frequency multiplication phase signal for recombination of one high-speed clock signal; the ith frequency multiplication phase signal of the 1 st group and the (i-1) th frequency multiplication phase signal of the 2 nd group are used as the frequency multiplication phase signal for recombination of the other high-speed clock signal; sequencing all frequency multiplication phase signals in the 1 st group and all frequency multiplication phase signals in the 2 nd group according to phase sizes; the total number of the high-speed clock signal groups is N groups, the number of the frequency multiplication phase signals of the 1 st group and the 2 nd group is M respectively, i, N and M are positive integers, and i is not less than 1,N not less than 2,M not less than N not less than i.
3. A high speed multiphase clock generation circuit according to claim 2, wherein said multiphase clock reassembly module comprises N groups of strobe signal cells, each group comprising two logic gate cells;
a logic gate circuit unit in the ith gating signal unit group is used for receiving the (i-1) th frequency multiplication phase signal of the 1 st group and the (i) th frequency multiplication phase signal of the 2 nd group, and performing logic combination on the (i-1) th frequency multiplication phase signal of the 1 st group and the (i) th frequency multiplication phase signal of the 2 nd group to output a high-speed clock signal in the ith high-speed clock signal group;
and the other logic gate circuit unit in the ith gating signal unit group is used for receiving the ith frequency multiplication phase signal of the 1 st group and the ith-1 frequency multiplication phase signal of the 2 nd group, logically combining the ith frequency multiplication phase signal of the 1 st group and the ith-1 frequency multiplication phase signal of the 2 nd group and outputting the other high-speed clock signal in the ith high-speed clock signal group.
4. A high speed multiphase clock generating circuit according to claim 3, wherein the 1 st multiplied phase signals in groups 1 and 2 are respectively coincident with the nth multiplied phase signals of the same group.
5. A high-speed multiphase clock generation circuit according to claim 3, wherein the logic gate circuit unit is a CMOS single-transistor logic gate circuit, the CMOS single-transistor logic gate circuit comprising: the source electrode of the PMOS transistor is connected with a power supply end, the drain electrode of the PMOS transistor is connected with the drain electrode of the NMOS transistor, and the source electrode of the NMOS transistor is grounded; the grid electrode of the PMOS transistor is used for connecting a negative phase signal in the two corresponding frequency doubling phase signals, and the grid electrode of the NMOS transistor is used for connecting a positive phase signal in the two corresponding frequency doubling phase signals; and the drain electrode of the PMOS transistor is used as the output end of the CMOS single-tube logic gate circuit and is used for outputting a corresponding high-speed clock signal.
6. A high speed multiphase clock generation circuit according to claim 5, wherein a duty cycle of said high speed clock signal is 1/N.
7. The high speed multiphase clock generation circuit of any one of claims 1-6, wherein said multiplied phase generation module comprises at least two sets of logic gate units, each set comprising N logic gate units, respectively;
the logic gate unit is used for: receiving at least two different phase clock signals, and outputting corresponding frequency multiplication phase signals by using a circuit delay mode;
and the frequency multiplication phase signals output by the corresponding logic gate units in the two groups of logic gate unit groups are mutually opposite signals corresponding to each other.
8. The high speed multiphase clock generation circuit of claim 7, wherein the logic gate cells of one set of said logic gate cells are nand gate logic gates and the logic gate cells of the other set of logic gate cells are nor gate logic gates.
9. The high-speed multiphase clock generation circuit of claim 7, wherein said first processing further comprises a frequency doubling processing such that the frequency of a doubled phase signal is greater than the frequency of a corresponding base frequency clock signal.
10. The high-speed multiphase clock generating circuit of claim 1, further comprising a baseband clock module for generating a plurality of baseband clock signals with different phases according to an initial clock signal.
11. The high speed multiphase clock generating circuit of claim 10, wherein the plurality of baseband clock signals are of the same frequency.
12. A high-speed multiphase clock generation circuit according to claim 1, wherein the frequency of the high-speed clock signals in each group is greater than or equal to the frequency of the corresponding multiplied phase signal for recombination.
13. A serializer comprising a high speed multiphase clock generating circuit as claimed in any one of claims 1 to 12 and a high speed data strobe apparatus;
the high-speed multiphase clock generating circuit is electrically connected with the high-speed data gating device;
the high-speed data gating device comprises a plurality of data gating units, wherein each data gating unit comprises a control end; the control ends of all the data gating units receive one group of high-speed clock signal groups in a plurality of groups of high-speed clock signal groups generated by the high-speed multiphase clock generating circuit in sequence according to the address bit sequence; the input ends of all the data gating units receive a specific data bit of the parallel data in sequence according to the order of the address bits; each data gating unit is gated or closed under the control of two high-speed clock signals with opposite phases of the corresponding high-speed clock signal group so as to sequentially transmit corresponding data bits; the sequencing of the high-speed clock signal groups is carried out according to the phase size.
14. The serializer of claim 13, wherein the data strobe unit is a CMOS transmission gate, wherein the positive phase signal of the two high speed clock signals of the corresponding high speed clock signal group with opposite phases is input to the positive control terminal of the CMOS transmission gate, and the negative phase signal is input to the negative control terminal of the CMOS transmission gate.
15. An electronic device comprising the serializer of any one of claims 13-14.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478308A (en) * | 2009-01-13 | 2009-07-08 | 北京时代民芯科技有限公司 | Configurable frequency synthesizer circuit based on time-delay lock loop |
| CN102158205A (en) * | 2011-03-14 | 2011-08-17 | 北京龙芯中科技术服务中心有限公司 | Clock frequency multiplier, device and clock frequency multiplication method |
| CN103607174A (en) * | 2013-12-02 | 2014-02-26 | 哈尔滨理工大学 | Multi-channel sinusoidal signal generator and method for generating multi-channel sinusoidal signals |
| US20150222277A1 (en) * | 2014-02-03 | 2015-08-06 | Advanced Micro Devices, Inc. | Self-adjusting clock doubler and integrated circuit clock distribution system using same |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| US20170373675A1 (en) * | 2016-06-28 | 2017-12-28 | Altera Corporation | Method and apparatus for phase-aligned 2x frequency clock generation |
| CN110649922A (en) * | 2019-10-26 | 2020-01-03 | 复旦大学 | Digital clock frequency multiplier |
-
2022
- 2022-12-27 CN CN202211681290.1A patent/CN115657788B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478308A (en) * | 2009-01-13 | 2009-07-08 | 北京时代民芯科技有限公司 | Configurable frequency synthesizer circuit based on time-delay lock loop |
| CN102158205A (en) * | 2011-03-14 | 2011-08-17 | 北京龙芯中科技术服务中心有限公司 | Clock frequency multiplier, device and clock frequency multiplication method |
| CN103607174A (en) * | 2013-12-02 | 2014-02-26 | 哈尔滨理工大学 | Multi-channel sinusoidal signal generator and method for generating multi-channel sinusoidal signals |
| US20150222277A1 (en) * | 2014-02-03 | 2015-08-06 | Advanced Micro Devices, Inc. | Self-adjusting clock doubler and integrated circuit clock distribution system using same |
| US20170373675A1 (en) * | 2016-06-28 | 2017-12-28 | Altera Corporation | Method and apparatus for phase-aligned 2x frequency clock generation |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN110649922A (en) * | 2019-10-26 | 2020-01-03 | 复旦大学 | Digital clock frequency multiplier |
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