CN115642090A - Fan-out packaging method - Google Patents
Fan-out packaging method Download PDFInfo
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- CN115642090A CN115642090A CN202211125695.7A CN202211125695A CN115642090A CN 115642090 A CN115642090 A CN 115642090A CN 202211125695 A CN202211125695 A CN 202211125695A CN 115642090 A CN115642090 A CN 115642090A
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Abstract
The invention discloses a fan-out packaging method, and relates to the technical field of semiconductor packaging. Be used for solving current fan-shaped structure drawback, realize fan-shaped chip and pile up and paste the passive device of dress, avoid sticking up the limit problem. The method comprises the following steps: drilling a hole in the Dummy silicon wafer and electroplating a TSV (through silicon via) conducting circuit; etching a groove on the upper surface of the Dummy silicon wafer, and arranging a first chip in the groove so that the first chip and the upper surface of the Dummy silicon wafer have the same height; preparing a first fan-out wiring layer on the upper surface of the first chip, wherein the first fan-out wiring layer completely covers the upper surface of the Dummy silicon chip; attaching a flip FC chip to the upper surface of the first fan-out wiring layer, and performing film pasting and plastic packaging on the FC chip so that the upper surface of a plastic packaging material is higher than the upper surface of the FC chip; and preparing a second fan-out wiring layer on the lower surface of the Dummy silicon chip, and preparing a plurality of solder balls on the upper surface of the second fan-out wiring layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging method.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. In order to comply with the development of the new generation of electronic products, especially the development of mobile phones, notebooks, etc., the chip will be developed toward higher density, faster speed, smaller size, lower cost, etc. The appearance of the fan-out type square chip level packaging technology is used as an upgrading technology of the fan-out type wafer level packaging technology, and has wider development prospect.
For the requirements of package miniaturization and large-scale package, the existing fan-shaped process cannot realize chip stacking and a large number of passive devices due to the structural limitation of the fan-shaped process, and the problem of warping is easy to occur.
Disclosure of Invention
The embodiment of the invention provides a fan-out packaging method, which is used for solving the defects of the existing fan-shaped structure, realizing the stacking and mounting of fan-shaped chips on a passive device and avoiding the problem of edge warping.
The embodiment of the invention provides a fan-out packaging method, which comprises the following steps:
drilling and electroplating the inside of the Dummy silicon wafer to form a TSV conducting circuit;
etching a groove on the upper surface of the Dummy silicon wafer, and arranging a first chip in the groove so that the upper surfaces of the first chip and the Dummy silicon wafer have the same height;
preparing a first fan-out wiring layer on the upper surface of the first chip, wherein the first fan-out wiring layer completely covers the upper surface of the Dummy silicon chip;
attaching a flip FC chip to the upper surface of the first fan-out wiring layer, and performing film pasting and plastic packaging on the FC chip so that the upper surface of a plastic packaging material is higher than the upper surface of the FC chip;
preparing a second fan-out wiring layer on the lower surface of the Dummy silicon chip, and preparing a plurality of solder balls on the upper surface of the second fan-out wiring layer.
Preferably, the mounting of the flip FC chip on the upper surface of the first fan-out wiring layer specifically includes:
attaching a flip FC chip to the upper surface of the first fan-out wiring layer, and arranging a passive component at an interval of two FC chips;
gaps exist between adjacent FC chips, and gaps exist between the passive component and the adjacent FC chips.
Preferably, a plurality of TSV conducting lines are formed through drilling and electroplating in the interior of the Dummy silicon wafer.
Preferably, the first sub fan-out wiring layer and the second sub fan-out wiring layer are connected through the TSV conductive line.
Preferably, after preparing a plurality of solder balls on the upper surface of the second fan-out wiring layer, the method further includes:
and cutting the whole panel to obtain a plurality of single packaged chips.
The embodiment of the invention provides a fan-out packaging method, which comprises the following steps: drilling and electroplating inside the Dummy silicon wafer to form a TSV (through silicon via) conducting circuit; etching a groove on the upper surface of the Dummy silicon wafer, and arranging a first chip in the groove so that the upper surfaces of the first chip and the Dummy silicon wafer have the same height; preparing a first fan-out wiring layer on the upper surface of the first chip, wherein the first fan-out wiring layer completely covers the upper surface of the Dummy silicon chip; attaching an inverted FC chip to the upper surface of the first fan-out wiring layer, and carrying out film pasting and plastic packaging on the FC chip so that the upper surface of a plastic packaging material is higher than the upper surface of the FC chip; preparing a second fan-out wiring layer on the lower surface of the Dummy silicon chip, and preparing a plurality of solder balls on the upper surface of the second fan-out wiring layer. According to the method, the first chip and the FC chip are vertically stacked on the Dummy silicon chip, so that a signal transmission path can be effectively shortened, and the electrical property of a product is improved; moreover, the embedded mounting of the passive component can meet the requirement of packaging systematization integration; fan-out wiring is carried out on the basis of the Dummy silicon wafer, the plastic package flatness of the product is good, the heat dissipation performance of the product is improved, and meanwhile the problem of warping of the product is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a fan-out packaging method according to an embodiment of the present invention;
fig. 2A is a schematic structural diagram of a first chip disposed in a Dummy silicon wafer according to an embodiment of the present invention;
FIG. 2B is an enlarged schematic view of the single chip package chip included in FIG. 2A according to an embodiment of the present invention;
fig. 3A is a schematic structural diagram of an FC chip disposed on a first fan-out wiring layer according to an embodiment of the present invention;
FIG. 3B is an enlarged schematic view of the single chip package chip included in FIG. 3A according to an embodiment of the present invention;
fig. 4A is a schematic diagram of a structure for laminating and plastically packaging an FC chip according to an embodiment of the present invention;
FIG. 4B is an enlarged schematic view of the single chip package chip included in FIG. 4A according to an embodiment of the present invention;
fig. 5A is a schematic structural view of a second fan-out wiring layer prepared on the lower surface of a Dummy silicon wafer according to an embodiment of the present invention;
FIG. 5B is a schematic diagram of a cut single packaged chip;
wherein, the silicon chip is 101-Dummy; 102 to a first chip; 103-TSV conducting lines; 104-first fan-out wiring layer; 105-FC chips; 106 passive components; 107-plastic packaging material; 108-second bump; 109-second fan-out wiring layer; 110-solder balls.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic flow diagram of a fan-out packaging method according to an embodiment of the present invention, and fig. 2A is a schematic structural diagram of a first chip disposed in a Dummy silicon wafer according to an embodiment of the present invention; FIG. 2B is an enlarged schematic view of the single package chip included in FIG. 2A according to an embodiment of the present invention; fig. 3A is a schematic structural diagram of an FC chip disposed on a first fan-out wiring layer according to an embodiment of the present invention; FIG. 3B is an enlarged schematic view of the single package chip included in FIG. 3A according to an embodiment of the present invention; fig. 4A is a schematic diagram of a structure for laminating and plastically packaging an FC chip according to an embodiment of the present invention; FIG. 4B is an enlarged schematic view of the single chip package chip included in FIG. 4A according to an embodiment of the present invention; fig. 5A is a schematic structural diagram of a second redistribution layer formed on the lower surface of a Dummy silicon wafer according to an embodiment of the present invention; FIG. 5B is a schematic diagram of a cut single packaged chip;
the fan-out packaging method provided by the embodiment of the invention is described in detail below by taking fig. 1 and fig. 2A to fig. 5B as examples.
Specifically, as shown in fig. 1, the packaging method based on fan-out provided by the embodiment of the present invention includes the following steps:
103, preparing a first redistribution layer on the upper surface of the first chip, wherein the first redistribution layer completely covers the upper surface of the Dummy silicon wafer;
104, attaching a flip FC chip to the upper surface of the first fan-out wiring layer 104, and performing film pasting and plastic packaging on the FC chip to enable the upper surface of a plastic packaging material to be higher than the upper surface of the FC chip;
In step 101, as shown in fig. 2A and 2B, a TSV (Through Silicon Via) Via line is etched inside the Dummy Silicon wafer 101, and the TSV Via line 103 penetrates Through the upper and lower surfaces of the Dummy Silicon wafer 101.
In step 103, etching is performed on the upper surface of the Dummy silicon wafer 101 according to the position of the first chip 102, that is, a groove for disposing the first chip 102 is etched on the upper surface of the Dummy silicon wafer 101, and then the first chip 102 is disposed in the groove. It should be noted that the position of the first chip 102 on the Dummy silicon wafer 101 is preset, and the position of the first chip 102 on the Dummy silicon wafer 101 is not limited herein.
Further, since the first fan-out wiring layer 104 is also prepared on the Dummy silicon chip 101, it is necessary to determine that the upper surface of the first chip 102 and the upper surface of the Dummy silicon chip 101 have the same height. Here, the width and depth of the groove for disposing the first chip 102 are not particularly limited, as long as it is ensured that the upper surface of the first chip 102 and the upper surface of the Dummy silicon wafer 101 have the same height after the first chip 102 is disposed on the Dummy silicon wafer 101.
In step 103, a first fan-out wiring layer 104 is prepared on the upper surface of the first chip 102, and the first fan-out wiring layer 104 is ensured to cover the first chip 102 and completely cover the upper surface of the Dummy silicon wafer 101. It should be noted that, in the entire panel shown in fig. 2A, a plurality of grooves may be disposed on the Dummy silicon wafer 101, and in order to ensure that a plurality of single packaged chips have the same function after being cut, the distances between the plurality of grooves etched on the Dummy silicon wafer 101 are equal, and herein, the distances between adjacent grooves are not limited.
In step 104, a flip FC chip 105 and a passive component 106 are mounted on the upper surface of the first fan-out wiring layer 104, and as shown in fig. 3A and 3B, two FC chips 105 and passive components 106 are included on one single package chip.
In the embodiment of the present invention, the passive component 106 is embedded and mounted on the upper surface of the first fan-out wiring layer 104, so that the requirement of packaging systematization integration can be met, meanwhile, the transmission path between the passive component 106 and the chip is shortened, and the performance of the product is optimized.
Further, a gap exists between the FC chip 105 and the passive component 106 disposed on the upper surface of the first fan-out wiring layer 104, and a specific value of the gap is not limited herein.
It should be noted that, when the FC chip 105 is disposed on the upper surface of the first fan-out wiring layer 104, a connection line between the FC chip 105 and the first fan-out wiring layer 104 is further included between the FC chip and the first fan-out wiring layer.
In step 104, as shown in fig. 4A and 4B, the FC chip 105, the passive component 106, and the upper surface of the first fan-out wiring layer 104 are subjected to film pasting and plastic packaging, that is, a plastic packaging material 107 is disposed on the upper surface of the first fan-out wiring layer 104, and finally, it is determined that the height of the upper surface of the plastic packaging material 107 is higher than the height of the upper surface of the FC chip 105, that is, the plastic packaging material 107 completely covers the FC chip 105.
In this embodiment, since the height of the upper surface of the passive component 106 is lower than the height of the upper surface of the FC chip 105, when the molding compound 107 completely covers the FC chip 105, it also completely covers the passive component 106.
In step 105, as shown in fig. 5A, a second fan-out wiring layer 109 is prepared on the lower surface of the Dummy silicon chip 101, and green oil is coated; further, as shown in fig. 5A, a plurality of solder balls 110 are prepared on the second fan-out wiring layer 109, thereby obtaining a whole piece of panel.
In practical applications, a whole panel is cut to obtain a plurality of single packaged chips as shown in fig. 5B.
In summary, an embodiment of the present invention provides a fan-out packaging method, including: etching a TSV (through silicon Via) conducting circuit in the Dummy silicon wafer; etching a groove on the upper surface of the Dummy silicon wafer, and arranging a first chip in the groove so that the upper surfaces of the first chip and the Dummy silicon wafer have the same height; preparing a first fan-out wiring layer on the upper surface of the first chip, wherein the first fan-out wiring layer completely covers the upper surface of the Dummy silicon chip; attaching an inverted FC chip to the upper surface of the first fan-out wiring layer, and carrying out film pasting and plastic packaging on the FC chip so that the upper surface of a plastic packaging material is higher than the upper surface of the FC chip; preparing a second fan-out wiring layer on the lower surface of the Dummy silicon chip, and preparing a plurality of solder balls on the upper surface of the second fan-out wiring layer. According to the method, the first chip and the FC chip are vertically stacked on the Dummy silicon chip, so that a signal transmission path can be effectively shortened, and the electrical property of a product is improved; moreover, the requirement of packaging systematization integration can be realized by embedding and mounting the passive component; fan-out wiring is carried out on the basis of the Dummy silicon wafer, the plastic package flatness of the product is good, the heat dissipation performance of the product is improved, and meanwhile the problem of warping of the product is solved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A fan-out packaging method, comprising:
drilling and electroplating the inside of the Dummy silicon wafer to form a TSV conducting circuit;
etching a groove on the upper surface of the Dummy silicon wafer, and arranging a first chip in the groove so that the upper surfaces of the first chip and the Dummy silicon wafer have the same height;
preparing a first fan-out wiring layer on the upper surface of the first chip, wherein the first fan-out wiring layer completely covers the upper surface of the Dummy silicon chip;
attaching a flip FC chip to the upper surface of the first fan-out wiring layer, and performing film pasting and plastic packaging on the FC chip so that the upper surface of a plastic packaging material is higher than the upper surface of the FC chip;
preparing a second fan-out wiring layer on the lower surface of the Dummy silicon chip, and preparing a plurality of solder balls on the upper surface of the second fan-out wiring layer.
2. The packaging method of claim 1, wherein attaching a flip-chip FC chip to an upper surface of the first fan-out wiring layer specifically comprises:
attaching a flip FC chip to the upper surface of the first fan-out wiring layer, and arranging a passive component at an interval of two FC chips;
gaps exist between adjacent FC chips, and gaps exist between the passive component and the adjacent FC chips.
3. The packaging method according to claim 1, wherein a plurality of TSV conductive lines are etched in the Dummy silicon wafer.
4. The packaging method of claim 3, wherein the first sub-fan-out routing layer and the second sub-fan-out routing layer are connected by the TSV conductive lines.
5. The packaging method of claim 1, wherein after the preparing the plurality of solder balls on the upper surface of the second fan-out wiring layer, further comprising:
and cutting the whole panel to obtain a plurality of single packaged chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211125695.7A CN115642090A (en) | 2022-09-16 | 2022-09-16 | Fan-out packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211125695.7A CN115642090A (en) | 2022-09-16 | 2022-09-16 | Fan-out packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115642090A true CN115642090A (en) | 2023-01-24 |
Family
ID=84942652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211125695.7A Pending CN115642090A (en) | 2022-09-16 | 2022-09-16 | Fan-out packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115642090A (en) |
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- 2022-09-16 CN CN202211125695.7A patent/CN115642090A/en active Pending
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