CN115632670A - CMOS current multiplexing type self-oscillation receiver front end - Google Patents

Abstract

The invention discloses a front end of a CMOS current multiplexing type self-oscillating receiver, including a low-noise transconductance amplifying circuit, a mixer, and an orthogonal voltage-controlled oscillator; the input terminals of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-; the mixer includes a first mixer and a second mixer; the output V1 of the low-noise transconductance amplifying circuit Gm is mixed with the input terminal Vm1 of the first mixer and the second mixer The input terminal Vm3 of the device, and the input terminal V _Q1 of the quadrature voltage-controlled oscillator QVCO are connected, the output terminal V2 of the low-noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer, and the second mixer The input terminal Vm4 of the oscillator is connected to the input terminal V _Q2 of the quadrature voltage-controlled oscillator QVCO. The current of the transconductor of the present invention is reused by the mixer and the oscillator, thereby significantly reducing power consumption.

Description

CMOS current multiplexed self-oscillating receiver front end

technical field

The invention relates to the technical field of radio frequency integrated circuits, in particular to the front end of a CMOS current multiplexing type self-oscillating receiver.

Background technique

With the development of semiconductor integrated circuits and the vigorous development of wireless communication, the front-end circuit of the receiver is constantly facing technological innovation and performance improvement. Among them, the demand for low power consumption is becoming more and more prominent. Receiver structures are very commonly used. In retrospect, commonly used methods for generating quadrature signals include the use of analog polyphase filter structures, or digital quadrature logic gate frequency division structures, or direct quadrature coupling VCO structures; for current millimeter-wave broadband communication applications, The first two structures are limited by technical bottlenecks, which make the quadrature coupled oscillator a rare effective solution. Its superior power and area efficiency are attractive technical advantages; however, traditional quadrature coupled oscillators suffer from phase noise and poor quadrature accuracy performance.

In traditional technology, low-noise amplifiers, mixers, and oscillators are usually designed in a modular way, which means that, to a large extent, they are designed as independent modules that are eventually wired together. Over the years, there have been innovative designs trying to highly integrate these modules for the purpose of reducing receiver power consumption. A typical representative is shown in Figure 1. In the existing document 1, its innovative structure includes an oscillator and a mixer. The oscillator is stacked on the output load of the mixer and shares a DC path; the circuit is called self-oscillating mixer. However, there is a trade-off between the phase noise of the oscillator and the noise figure of the mixer. Low phase noise requires sufficient bias current for the oscillator. However, this will inevitably cause a large contribution to the noise of the switch and deteriorate the noise figure of the mixer. In addition, this structure does not have orthogonal performance and cannot be applied to mainstream direct conversion receiver solutions. Therefore, we propose a more practical CMOS current multiplexed self-oscillating receiver front end.

Contents of the invention

The purpose of the present invention is to provide a CMOS current multiplexing type self-oscillating receiver front end, which solves the existing problems.

To achieve the above object, the present invention provides the following technical solutions: CMOS current multiplexing type self-oscillating receiver front end, including a low-noise transconductance amplifier circuit and a mixer, and a quadrature voltage-controlled oscillator;

The input ends of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-;

The mixer includes a first mixer and a second mixer;

The output terminal V1 of the low-noise transconductance amplifying circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, and the input terminal _VQ1 of the quadrature voltage-controlled oscillator QVCO, so The output terminal V2 of the low-noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal VQ2 of the quadrature voltage-controlled oscillator _QVCO .

Preferably, the low-noise transconductance amplifying circuit includes NMOS transistor Mn1, NMOS transistor Mn2, PMOS transistor Mp1, PMOS transistor Mp2, PMOS transistor Mp3, PMOS transistor Mp4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5 , capacitor C6, capacitor C16, capacitor C17, capacitor Cntr1, capacitor Cntr2, inductor L5, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13 and resistor R14.

Preferably, one end of the capacitor C1 is connected to one end of the capacitor C2 and one end of the capacitor C16 as the input terminal Vin+ of the low-noise transconductance amplifier circuit, and the other end of the capacitor C2 is connected to the gate terminal of the NMOS transistor Mn1 and the capacitor Cntr1 One end is connected to one end of the resistor R10, the source end of the NMOS transistor Mn1 is grounded, the drain end of the NMOS transistor Mn1 is connected to the drain end of the PMOS transistor Mp3 and the drain end of the PMOS transistor Mp1 is connected to one end of the capacitor Cntr2 as a low-noise crossover The output terminal V1 of the conduction amplifier circuit, the gate terminal of the PMOS transistor Mp3 is connected to the other end of the capacitor C1 and one end of the resistor R9, the drain terminal of the PMOS transistor Mp3 is connected to the power supply voltage VDD, and the gate terminal of the PMOS transistor Mp1 It is connected with one end of the capacitor C6 and one end of the resistor R11, the source end of the PMOS transistor Mp1 is connected with one end of the capacitor C5, one end of the capacitor C17 and the a end of the inductor L5, and the c end of the inductor L5 is connected with the power supply voltage VDD , the b end of the inductance L5 is connected to the other end of the capacitor C16 and the other end of the capacitor C6 is connected to the source end of the PMOS transistor Mp2, the gate end of the PMOS transistor Mp2 is connected to the other end of the capacitor C5 and one end of the resistor R12, The other end of the resistor R12 is connected to the other end of the resistor R11, the drain end of the PMOS transistor Mp2 is connected to the other end of the capacitor Cntr1 and the drain end of the PMOS transistor Mp4 is connected to the drain end of the NMOS transistor Mn2 as a low-noise transconductance amplifier The output terminal V2 of the circuit, the source terminal of the PMOS transistor Mp4 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor Mp4 is connected to one end of the capacitor C4 and one end of the resistor R13, and the other end of the capacitor C4 is connected to the capacitor C17 The other end of the capacitor C3 is connected to the input terminal Vin- of the low-noise transconductance amplifier circuit, the other end of the capacitor C3 is connected to the gate terminal of the NMOS transistor Mn2 and the other end of the capacitor Cntr2 is connected to one end of the resistor R14, The source end of the NMOS transistor Mn2 is grounded.

Preferably, the output terminals of the first mixer are respectively IFq+ and IFq-, and the input terminal LO0 of the first mixer is connected to the output terminal V _QO2 of the quadrature voltage-controlled oscillator QVCO through a capacitor C11, so The input terminal LO2 of the first mixer is connected to the output terminal V _QO1 of the quadrature voltage-controlled oscillator QVCO through the capacitor C10, the output terminals of the second mixer are IFi+ and IFi- respectively, and the second mixer The input terminal LO3 of the frequency mixer is connected to the output terminal V _QO3 of the quadrature voltage-controlled oscillator QVCO through the capacitor C9, and the input terminal LO1 of the second mixer is connected to the output terminal V of the quadrature voltage-controlled oscillator QVCO through the capacitor C8. _QO4 connection.

Preferably, the structures of the first mixer and the second mixer are the same, including PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, capacitor C _L1 , resistor R _L1 , resistor R _L2 , resistor R7 and resistor R8 , and comparator Opamp.

Preferably, the gate terminal of the NMOS transistor M4 is connected to the gate terminal of the NMOS transistor M5 and one end of the resistor R7 is used as the input terminal V _LO+ of the mixer, and the source terminal of the NMOS transistor M4 is connected to the source terminal of the NMOS transistor M3 Connected as Vmix+, the drain end of the NMOS transistor M4 is connected to the drain end of the PMOS transistor M1, one end of the resistor _{RL1, one end of the capacitor C L1 ,} and the drain end of the NMOS transistor M6 as the output end IF+ of the mixer. The source terminal of the PMOS transistor M1 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor M1 is connected to the output terminal of the comparator Opamp and the gate terminal of the PMOS transistor M2, and the positive terminal of the comparator Opamp is connected to the reference voltage vref, so The negative end of the comparator Opamp is connected to the other end of the resistor RL1 and one end of the resistor _RL2 , and the other end of the resistor _RL2 is connected to the drain end of the PMOS transistor _{M2, the other end of the capacitor C L1 and} the drain of the NMOS transistor M3. The terminal is connected as the output terminal IF- of the mixer, the source terminal of the PMOS transistor M2 is connected to the power supply voltage VDD, the gate terminal of the NMOS transistor M3 is connected to one end of the gate terminal resistor R8 of the NMOS transistor M6 as a mixer The input terminal V _LO- of the resistor R8 is connected to the other terminal of the resistor R7, and the source terminal of the NMOS transistor M6 is connected to the source terminal of the NMOS transistor M5 as Vmix-.

Preferably, the quadrature voltage-controlled oscillator includes inductor L1, inductor L2, inductor L3, inductor L4, NMOS transistor Mn3, NMOS transistor Mn4, PMOS transistor Mp5, PMOS transistor Mp6, NMOS transistor Mn5, NMOS transistor Mn6, PMOS transistor M7, NMOS tube M8, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, capacitor C7, capacitor C12, capacitor C13, capacitor Cp1, capacitor Cp2, capacitor C14, capacitor C15, variable capacitor Cvar1, variable The capacitor Cvar2, the variable capacitor Cvar3 and the variable capacitor Cvar4.

Preferably, terminal a of the inductor L4 is connected to the input terminal V _Q1 , terminal b of the inductor L4 is connected to the input terminal V _Q2 , terminal c of the inductor L4 is connected to the drain terminal of the PMOS transistor M7 and the source terminal of the NMOS transistor M8 It is connected to the drain end of the NMOS transistor M8, the gate end of the NMOS transistor M8 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor M7 is connected to the bias voltage Vbp2, and the source end of the PMOS transistor M7 is connected to one end of the capacitor C7 It is connected to the c terminal of the inductance L3, the other end of the capacitor C7 is grounded, the a terminal of the inductance L3 is connected to the source terminal of the NMOS transistor Mn3, the source terminal of the NMOS transistor Mn4, the drain terminal of the PMOS transistor Mp5, and one end of the capacitor Cp1 connected, the gate end of the NMOS transistor Mn3 is connected to the resistor R1 and one end of the capacitor C13, and the drain end of the NMOS transistor Mn3 is connected to one end of the capacitor C12 and one end of the variable capacitor Cvar1 and the a end of the inductor L1 as an orthogonal voltage The output terminal Vosc+ of the controlled oscillator, the c terminal of the inductance L1 is connected to the power supply voltage VDD, the b terminal of the inductance L1 is connected to the drain terminal of the NMOS transistor Mn4, the other end of the capacitor C13 and one end of the variable capacitor Cvar2 as an orthogonal The output terminal Vosc- of the voltage controlled oscillator, the other end of the variable capacitor Cvar2 is connected to the other end of the variable capacitor Cvar1, the gate end of the NMOS transistor Mn4 is connected to the other end of the capacitor C12 and one end of the resistor R2, the The other end of the resistor R2 is connected to the other end of the resistor R1, and the b-end of the inductor L3 is connected to the source end of the NMOS transistor Mn6, the source end of the NMOS transistor Mn5, the drain end of the PMOS transistor Mp6, and one end of the capacitor Cp2. The gate end of the NMOS transistor Mn6 is connected to the resistor R6 and one end of the capacitor C14, and the drain end of the NMOS transistor Mn6 is connected to one end of the capacitor C15, one end of the variable capacitor Cvar4, and the b end of the inductor L2 as a quadrature voltage-controlled oscillator. The output terminal Voscq-, the c terminal of the inductance L2 is connected to the power supply voltage VDD, the a terminal of the inductance L1 is connected to the drain terminal of the NMOS transistor Mn5, the other end of the capacitor C14 and one end of the variable capacitor Cvar3 as an orthogonal voltage controlled oscillation The output terminal Voscq+ of the device, the other end of the variable capacitor Cvar3 is connected to the other end of the variable capacitor Cvar4, the gate end of the NMOS transistor Mn5 is connected to the other end of the capacitor C15 and one end of the resistor R5, and the other end of the resistor R5 One end is connected to the other end of the resistor R6, the gate end of the PMOS transistor Mp6 is connected to one end of the resistor R4 and the other end of the capacitor Cp1, the source end of the PMOS transistor Mp6 is connected to the source end of the PMOS transistor Mp5 and the power supply voltage VDD , the gate terminal of the PMOS transistor Mp5 is connected to one end of the resistor R3 and the other end of the capacitor Cp2, and the other end of the resistor R3 is connected to the other end of the resistor R4.

Compared with the prior art, the beneficial effects of the present invention are as follows:

1. The current of the transconductor of the present invention is reused by the mixer and the oscillator, which significantly reduces power consumption.

2. The auxiliary positive feedback cross-coupling structure of the present invention improves the differential mode loop gain of the tail node transformer, making the phase quadrature accuracy of the output signal of the quadrature oscillator more accurate and the phase noise lower.

Description of drawings

Fig. 1 is a circuit structure diagram of a traditional self-oscillating mixer;

Fig. 2 is a front-end architecture diagram of the present invention;

Fig. 3 is a schematic diagram of a specific circuit of the present invention;

Fig. 4 is a schematic diagram of a low-noise transconductance amplifier circuit of the present invention;

Fig. 5 is a schematic diagram of a mixer of the present invention;

6 is a schematic diagram of a quadrature voltage-controlled oscillator of the present invention;

Fig. 7 is a schematic diagram of the input matching characteristic S11 of the present invention;

Fig. 8 is a schematic diagram of the gain bandwidth of the present invention

Fig. 9 is a schematic diagram of the noise figure of the present invention;

Fig. 10 is a schematic diagram of in-band linearity of the present invention;

Fig. 11 is a schematic diagram of the oscillation frequency of the quadrature oscillator of the present invention;

Fig. 12 is a schematic diagram of phase noise of the present invention;

Fig. 13 is a schematic diagram of the quadrature phase error of the quadrature oscillator of the present invention;

FIG. 14 is a schematic diagram of the differential phase error of the quadrature oscillator of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.

Specific implementation case one

As shown in Figure 1 and Figure 2, the front end of the CMOS current multiplexed self-oscillating receiver includes a low-noise transconductance amplifier circuit, a mixer, and a quadrature voltage-controlled oscillator;

The input ends of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-;

The mixer includes a first mixer and a second mixer;

The output terminal V1 of the low-noise transconductance amplifying circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, and the input terminal _VQ1 of the quadrature voltage-controlled oscillator QVCO, so The output terminal V2 of the low-noise transconductance amplifying circuit Gm and the input terminal Vm2 of the first mixer are connected with the input terminal Vm4 of the second mixer and the input terminal VQ2 of the quadrature voltage-controlled oscillator _QVCO ;

The input RF signal is input at both ends of the port Vin+ and port Vin-, and is converted into a current by a low-noise transconductance amplifier circuit, and then mixed by a mixer to obtain useful intermediate frequency signal output IFi+/- and IFq+/-, in particular, The local oscillator source of the mixer is provided by a self-oscillating voltage-controlled oscillator, and the DC current of the oscillator and the mixer is reused by the transconductor, so as to achieve the effect of reducing power consumption; in addition, based on the super-harmonic coupling structure, the With an auxiliary cross-coupling structure, the oscillator is able to provide a local oscillator signal with high phase accuracy.

With reference to Fig. 3, the overall structural diagram of the present invention can be shown clearly, and the front end of CMOS current multiplexing type self-oscillating receiver is made up of low-noise transconductance amplifying circuit, mixer, quadrature voltage-controlled oscillator; Low-noise transconductor The bias current is multiplexed by the mixer and oscillator for low power consumption.

As far as the low-noise transconductor is concerned, its structure diagram is shown in Figure 4, which includes a capacitive cross-coupled common-gate input structure (Mp1/Mp2) to provide input impedance matching; it also includes a complementary common-source input stage (Mn1/Mp3 and Mn2/Mp4); on the one hand, the complementary common-source stage improves the input transconductance of the circuit, and at the same time, it can partially eliminate the noise of the common-gate input pole, and the capacitive cross-coupling (C5, C6) turns the common-gate transistor The noise output is halved; so this structure largely guarantees the low noise effect of the circuit; in addition, the cross-coupled neutralization capacitors (Cntr1, Cntr2) are used to reduce the adverse influence of the Miller effect on the input matching.

The mixer circuit is shown in Figure 5, based on the classic Gilbert fully differential structure, an active feedback structure is used at the intermediate frequency load; the active feedback structure samples the common-mode level of the load resistance, and is controlled by the feedback of the comparator Transistor gate bias, so as to ensure that the DC level of the load is properly biased and obtain good linearity; at the same time, the bias current of the oscillator shunts the bias current of the transconductor through the transistor M7, so that the mixer obtains a reduction The small bias current and reduced noise output indirectly obtain the technical effect of current injection; furthermore, the inductance L4 is used to resonantly absorb the parasitic capacitance of the tail node of the switch tube of the mixer, so that the noise charging and discharging effect of the switch tube can be eliminated. Avoidance is also beneficial to the low-noise effect of the overall circuit.

The quadrature oscillator circuit shown in Figure 6 consists of two main LC oscillators and an auxiliary positive feedback cross-coupled structure (Mp5/Mp6); specifically, the two LC oscillators use a transformer (L3) at the tail node The coupling structure; in this way, in order to ensure the reverse coupling resonance of the transformer at 2f0 frequency (transformer self-inductance and parasitic capacitance at this node), quadrature oscillation at the f0 frequency of the LC oscillator can be formed, but the 2f0 frequency signal amplitude It is very weak, and the coupling coefficient of the transformer is often less than 1. In this way, considering the mismatch generated by the layout, and the RF signal leaked by the transconductor and the mixer through the M7 path, the strong common-mode interference generated by the transformer is likely to damage the transformer. The quadrature oscillation at f0 frequency of the LC oscillator becomes undesired oscillation in the same direction.

In order to solve this problem, on the one hand, a positive feedback loop can be designed at the transformer to appropriately increase the differential-mode loop gain of the tail node, thereby improving the orthogonality of the output signal of the LC oscillator; of course, the differential-mode loop gain It cannot be too large, so that the positive feedback cross-coupling structure and the transformer constitute another oscillator at the frequency of 2f0, which affects the turn-on and turn-off of the main LC oscillator transistor; specifically, the differential mode can be realized by adjusting the control bias voltage Vadj Control and tuning of loop gain; on the other hand, add a filter capacitor through the M7 path to overcome the RF signal leakage of the transconductor mixer; in the case of RF input differential pair layout mismatch, there must be RF port signals in common mode Interfering with the differential-mode operation of the transformer at the tail node of the oscillator; of course, the 2f0 harmonic frequency signal at the tail node of the mixer directly constitutes the common-mode interference of the transformer at the tail node of the oscillator. For these two mechanisms, two capacitors M8 and C7 can be added to filter out; here the transistor M8 acts as a filter capacitor. Although the transistor capacitor has the disadvantages of noise and linearity, the transistor M8 is located in the common mode path and will not It has an impact on the output of the mixer, and the C7 capacitor can absorb the noise of the transistor M8 and the nonlinear interference to the oscillator. Thanks to the above design strategies, the accuracy of the quadrature oscillator of the present invention can be improved and improved. ensure.

Injection locking is also a technical issue to be considered. In Document 2, when the signal of the radio frequency port is strong, it can be coupled to the output node of the intermediate frequency load through the parasitic capacitance of the mixer transistor, which may cause oscillation there Injection locking occurs in the mixer, and the mixer cannot work at the desired intermediate frequency; in contrast, with the structure of the present invention, the stronger signal of the radio frequency port can be filtered by two capacitors M8 and C7, and the M7 transistor can also act A certain reverse isolation effect is obtained, which makes the injection locking phenomenon less likely to occur in the present invention.

Specific implementation case two

The front-end circuit of a current multiplexing self-oscillating direct-conversion receiver provided in this embodiment is designed and realized by using a 65nm standard CMOS process.

In the circuit, only the intermediate frequency load transistor (M1/M2) of the mixer adopts a 250nm long channel structure to reduce flicker noise, and the other transistors use a 60nm length to obtain good RF performance; the power supply voltage is 1.2V, and the differential transconductor consumes current is 4.6mA*2, the overall power consumption is 12mW, the bias current of a single transistor of the mixer is 128uA, the current of M7 in the working mode path is 3.3mA, the auxiliary cross unit coupling consumes 0.3mA, and the bias current of the common gate input stage 0.6mA, the capacitor C7 is 15pF, and the equivalent capacitance of the transistor M8 is 200pF; based on the above optimized bias current, the circuit simulation performance can be obtained, and the results are as follows.

Figure 7 shows the simulation results of the input matching characteristic S11 of the circuit. It can be seen that _S11 is less than -10dB in the 7.7-9.8GHz frequency band;

Figure 8 shows the simulation results of the gain bandwidth of the circuit, the 3dB bandwidth is about 50MHz, and the gain is as high as 34.8dB at low frequencies;

Figure 9 shows the simulation results of the noise figure NF of the circuit. It can be seen that the noise figure is lower than 3dB from 1MHz to 100MHz. And the flicker noise corner is around 400KHz;

Figure 10 shows the simulation result of the third-order intermodulation input IP3 of the circuit, which is -19.5dBm;

Figure 11 shows the output waveform of the quadrature oscillator of the circuit. The frequency of the four signals is 8.5215 GHz. Adjusting the tuning capacitor of the oscillator can change the frequency within a certain range, and no illustration is given here;

Figure 12 shows the simulation results of the phase noise of the circuit. In the frequency range of 0.1MHz to 1MHz, the phase noise drops from -80dBc/Hz to -108dBc/Hz, thanks to the oscillator-assisted cross-coupling structure, and CLASS C configuration (avoiding the main oscillator transistor entering the deep triode region, resulting in the degradation of the loaded Q value of the LC resonant network), the phase noise has achieved a good level;

Figure 13 shows the simulation results of the 270° phase error between the quadrature ports of the quadrature oscillator. It can be seen from the delay curve that the phase quadrature error is within 2° and the stabilization time is about 8 ns. The simulation also shows that without using the auxiliary cross-coupling structure, the obtained quadrature error is about 5°, no separate illustration is given here, the lower the quadrature error means that the receiver can obtain better The demodulation signal-to-noise ratio;

Figure 14 shows the simulation results of the 180° phase error of the differential port of the quadrature oscillator of the circuit. The delay curve shows that a single oscillator has good differential performance, and the stabilization time is within 1ns.

Table 1 has provided the comprehensive comparison of the performance of the present invention and previous documents, and it can be seen that the upper consumption power is the same, but the structure of the present invention provides a dual-channel reception mode of IQ, which realizes the same dual-channel reception than the comparison document, saving Half the power makes this invention very competitive; on key electrical indicators, such as gain, noise/phase noise, this invention has also obtained overwhelming technical advantages, even if it is linearity, if you use the output IP3 (OIP3) To measure, the present invention also has significant advantages; the comparative literature requires 6 inductors, which takes up a large area; the present invention requires 5 inductors/transformers, which reduces the area and cost of the chip. Based on the above comparison and discussion, the present invention proposes on the whole A current-multiplexing quadrature receiver front-end is developed; the current of the oscillator and the mixer is reused by the transconductor, and the highly integrated circuit structure significantly reduces power consumption and even simplifies the bias circuit; includes auxiliary cross-coupling The quadrature oscillator of the structure provides more accurate phase precision and lower phase noise.

Table 1 Comprehensive performance comparison

Among them, references 1 and 2 are [Stanley S.K.Ho; Carlos E.Saavedra "A Low-Noise Self-Oscillating Mixer Using a Balanced VCO Load," IEEE Transactions on Circuits and Systems, vol.58, no.8, pp.1705 –1712, Feb. 2011.].

Claims (8)

1. The CMOS current multiplexing type self-oscillating receiver front end is characterized in that it includes a low-noise transconductance amplifier circuit and a mixer, and a quadrature voltage-controlled oscillator; The input ends of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-; The mixer includes a first mixer and a second mixer; The output terminal V1 of the low-noise transconductance amplifying circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, and the input terminal _VQ1 of the quadrature voltage-controlled oscillator QVCO, so The output terminal V2 of the low-noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal VQ2 of the quadrature voltage-controlled oscillator _QVCO . 2. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the low-noise transconductance amplifying circuit comprises NMOS transistor Mn1, NMOS transistor Mn2, PMOS transistor Mp1, PMOS transistor Mp2, PMOS transistor Tube Mp3, PMOS tube Mp4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C16, capacitor C17, capacitor Cntr1, capacitor Cntr2, inductor L5, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13 and resistor R14. 3. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein one end of the capacitor C1 is connected with one end of the capacitor C2 and one end of the capacitor C16 as an input of a low-noise transconductance amplifier circuit Terminal Vin+, the other end of the capacitor C2 is connected to the gate end of the NMOS transistor Mn1 and one end of the capacitor Cntr1 and one end of the resistor R10, the source end of the NMOS transistor Mn1 is grounded, and the drain end of the NMOS transistor Mn1 is connected to the PMOS transistor The drain end of Mp3 and the drain end of the PMOS transistor Mp1 are connected to one end of the capacitor Cntr2 as the output end V1 of the low-noise transconductance amplifier circuit, and the gate end of the PMOS transistor Mp3 is connected to the other end of the capacitor C1 and one end of the resistor R9, The drain terminal of the PMOS transistor Mp3 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor Mp1 is connected to one end of the capacitor C6 and one end of the resistor R11, and the source end of the PMOS transistor Mp1 is connected to one end of the capacitor C5 and the capacitor C17. One end is connected to the a terminal of the inductor L5, the c terminal of the inductor L5 is connected to the power supply voltage VDD, the b terminal of the inductor L5 is connected to the other end of the capacitor C16 and the other end of the capacitor C6 is connected to the source end of the PMOS transistor Mp2, The gate end of the PMOS transistor Mp2 is connected to the other end of the capacitor C5 and one end of the resistor R12, the other end of the resistor R12 is connected to the other end of the resistor R11, and the drain end of the PMOS transistor Mp2 is connected to the other end of the capacitor Cntr1 The drain end of the PMOS transistor Mp4 is connected to the drain end of the NMOS transistor Mn2 as the output end V2 of the low-noise transconductance amplifier circuit, the source end of the PMOS transistor Mp4 is connected to the power supply voltage VDD, and the gate end of the PMOS transistor Mp4 is connected to the power supply voltage VDD. One end of the capacitor C4 is connected to one end of the resistor R13, the other end of the capacitor C4 is connected to the other end of the capacitor C17 and one end of the capacitor C3 as the input terminal Vin- of the low-noise transconductance amplifier circuit, and the other end of the capacitor C3 The gate terminal of the NMOS transistor Mn2 and the other end of the capacitor Cntr2 are connected to one end of the resistor R14, and the source terminal of the NMOS transistor Mn2 is grounded. 4. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the output terminals of the first mixer are respectively IFq+ and IFq-, and the input of the first mixer The terminal LO0 is connected to the output terminal V QO2 of the quadrature voltage-controlled oscillator QVCO through the capacitor C11, and the input terminal LO2 of the first mixer is connected to the output terminal V _QO1 of the quadrature voltage-controlled oscillator _QVCO through the capacitor C10, so The output terminals of the second mixer are respectively IFi+ and IFi-, the input terminal LO3 of the second mixer is connected with the output terminal V _QO3 of the quadrature voltage-controlled oscillator QVCO through a capacitor C9, and the second mixer The input terminal LO1 of the frequency converter is connected to the output terminal V _QO4 of the quadrature voltage-controlled oscillator QVCO through a capacitor C8. 5. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the first mixer and the second mixer have the same structure, including PMOS transistors M1, PMOS transistors M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, capacitor C _L1 , resistor R _L1 , resistor R _L2 , resistor R7 and resistor R8, and a comparator Opamp. 6. The CMOS current multiplexing type self-oscillating receiver front end according to claim 5, characterized in that, the grid end of the NMOS transistor M4 is connected to the grid end of the NMOS transistor M5 and one end of the resistor R7 is used as a mixer The input terminal V _LO+ of the NMOS transistor M4 is connected to the source terminal of the NMOS transistor M3 as Vmix+, the drain terminal of the NMOS transistor M4 is connected to the drain terminal of the PMOS transistor M1 and one end of the resistor _RL1 and the capacitor C _L1 One end of the PMOS transistor M1 is connected to the drain end of the NMOS transistor M6 as the output end IF+ of the mixer, the source end of the PMOS transistor M1 is connected to the power supply voltage VDD, the gate end of the PMOS transistor M1 is connected to the output end of the comparator Opamp and the PMOS The gate terminal of the tube M2 is connected, the positive terminal of the comparator Opamp is connected to the reference voltage vref, the negative terminal of the comparator Opamp is connected to the other end of the resistor _RL1 and one end of the resistor _RL2 , and the other end of the resistor _RL2 One end is connected to the drain end of the PMOS transistor M2 and the other end of the capacitor C _L1 is connected to the drain end of the NMOS transistor M3 as the output end IF- of the mixer, the source end of the PMOS transistor M2 is connected to the power supply voltage VDD, and the NMOS transistor M3 The gate terminal of the tube M3 is connected to one end of the gate terminal resistor R8 of the NMOS tube M6 as the input terminal V _LO- of the mixer, the other end of the resistor R8 is connected to the other end of the resistor R7, and the source of the NMOS tube M6 The terminal is connected to the source terminal of the NMOS transistor M5 as Vmix-. 7. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the quadrature voltage-controlled oscillator comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an NMOS transistor Mn3, an NMOS Tube Mn4, PMOS tube Mp5, PMOS tube Mp6, NMOS tube Mn5, NMOS tube Mn6, PMOS tube M7, NMOS tube M8, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, capacitor C7, capacitor C12 , capacitor C13, capacitor Cp1, capacitor Cp2, capacitor C14, capacitor C15, variable capacitor Cvar1, variable capacitor Cvar2, variable capacitor Cvar3 and variable capacitor Cvar4. 8. The front end of the CMOS current multiplexed self-oscillating receiver according to claim 7, wherein the a-terminal of the inductance L4 is connected to the input terminal V _Q1 , and the b-terminal of the inductance L4 is connected to the input terminal V _Q2 , The c terminal of the inductor L4 is connected to the drain terminal of the PMOS transistor M7 and the source terminal of the NMOS transistor M8 and the drain terminal of the NMOS transistor M8, the gate terminal of the NMOS transistor M8 is connected to the power supply voltage VDD, and the PMOS transistor M7 The gate terminal is connected to the bias voltage Vbp2, the source terminal of the PMOS transistor M7 is connected to one end of the capacitor C7 and the c-terminal of the inductance L3, the other end of the capacitor C7 is grounded, and the a-terminal of the inductance L3 is connected to the terminal a of the NMOS transistor Mn3 The source end is connected to the source end of the NMOS transistor Mn4 and the drain end of the PMOS transistor Mp5 and one end of the capacitor Cp1, the gate end of the NMOS transistor Mn3 is connected to the resistor R1 and one end of the capacitor C13, and the drain end of the NMOS transistor Mn3 is connected to One end of the capacitor C12, one end of the variable capacitor Cvar1, and the a-end of the inductor L1 are connected as the output end Vosc+ of the quadrature voltage-controlled oscillator, the c-terminal of the inductor L1 is connected to the power supply voltage VDD, and the b-terminal of the inductor L1 is connected to the NMOS The drain end of the tube Mn4 is connected to the other end of the capacitor C13 and one end of the variable capacitor Cvar2 as the output terminal Vosc- of the quadrature voltage-controlled oscillator, and the other end of the variable capacitor Cvar2 is connected to the other end of the variable capacitor Cvar1. The gate end of the NMOS transistor Mn4 is connected to the other end of the capacitor C12 and one end of the resistor R2, the other end of the resistor R2 is connected to the other end of the resistor R1, the b end of the inductor L3 is connected to the source end of the NMOS transistor Mn6 and the NMOS The source end of the tube Mn5 is connected to the drain end of the PMOS transistor Mp6 and one end of the capacitor Cp2, the gate end of the NMOS transistor Mn6 is connected to the resistor R6 and one end of the capacitor C14, and the drain end of the NMOS transistor Mn6 is connected to one end of the capacitor C15 One end of the variable capacitor Cvar4 is connected to the b end of the inductor L2 as the output end Voscq- of the quadrature voltage controlled oscillator, the c end of the inductor L2 is connected to the power supply voltage VDD, the a end of the inductor L1 is connected to the NMOS tube Mn5 The drain terminal is connected to the other end of the capacitor C14 and one end of the variable capacitor Cvar3 as the output terminal Voscq+ of the quadrature voltage controlled oscillator, the other end of the variable capacitor Cvar3 is connected to the other end of the variable capacitor Cvar4, and the NMOS tube Mn5 The gate end is connected to the other end of the capacitor C15 and one end of the resistor R5, the other end of the resistor R5 is connected to the other end of the resistor R6, and the gate end of the PMOS transistor Mp6 is connected to one end of the resistor R4 and the other end of the capacitor Cp1 , the source end of the PMOS transistor Mp6 is connected to the source end of the PMOS transistor Mp5 and the power supply voltage VDD, the gate end of the PMOS transistor Mp5 is connected to one end of the resistor R3 and the other end of the capacitor Cp2, and the other end of the resistor R3 Connect with the other end of resistor R4.

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