CN115632670A - CMOS current multiplexing type self-oscillation receiver front end - Google Patents

CMOS current multiplexing type self-oscillation receiver front end Download PDF

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CN115632670A
CN115632670A CN202211227474.0A CN202211227474A CN115632670A CN 115632670 A CN115632670 A CN 115632670A CN 202211227474 A CN202211227474 A CN 202211227474A CN 115632670 A CN115632670 A CN 115632670A
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resistor
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CN115632670B (en
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郭本青
樊润伍
廖星月
王海时
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Chengdu University of Information Technology
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16Multiple-frequency-changing
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183Long tailed pairs
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/372Noise reduction and elimination in amplifier
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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Abstract

本发明公开了CMOS电流复用型自振荡接收机前端,包括低噪声跨导放大电路和混频器,以及正交压控振荡器;所述低噪声跨导放大电路Gm的输入端分别为Vin+和Vin‑;所述混频器包括第一混频器和第二混频器;所述低噪声跨导放大电路Gm的输出端V1与第一混频器的输入端Vm1和第二混频器的输入端Vm3,以及正交压控振荡器QVCO的输入端VQ1连接,所述低噪声跨导放大电路Gm的输出端V2和第一混频器的输入端Vm2,与第二混频器的输入端Vm4和正交压控振荡器QVCO的输入端VQ2连接。本发明跨导器的电流被混频器、振荡器重复使用,显著降低了功耗。

Figure 202211227474

The invention discloses a front end of a CMOS current multiplexing type self-oscillating receiver, including a low-noise transconductance amplifying circuit, a mixer, and an orthogonal voltage-controlled oscillator; the input terminals of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-; the mixer includes a first mixer and a second mixer; the output V1 of the low-noise transconductance amplifying circuit Gm is mixed with the input terminal Vm1 of the first mixer and the second mixer The input terminal Vm3 of the device, and the input terminal V Q1 of the quadrature voltage-controlled oscillator QVCO are connected, the output terminal V2 of the low-noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer, and the second mixer The input terminal Vm4 of the oscillator is connected to the input terminal V Q2 of the quadrature voltage-controlled oscillator QVCO. The current of the transconductor of the present invention is reused by the mixer and the oscillator, thereby significantly reducing power consumption.

Figure 202211227474

Description

CMOS电流复用型自振荡接收机前端CMOS current multiplexed self-oscillating receiver front end

技术领域technical field

本发明涉及射频集成电路技术领域,具体为CMOS电流复用型自振荡接收机前端。The invention relates to the technical field of radio frequency integrated circuits, in particular to the front end of a CMOS current multiplexing type self-oscillating receiver.

背景技术Background technique

随着半导体集成电路的发展,以及无线通信的蓬勃发展,接收机前端电路不断的面对技术创新和性能提升,其中,低功耗的需求越发突出,同时注意到,正交信号产生对于直接变频接收机结构非常普遍应用着。回顾起来,常用的产生正交信号的方法包括使用模拟的多相滤波结构,或者数字的正交逻辑门分频结构、或者直接的正交耦合VCO结构;对于当前的毫米波宽带通信应用领域,前两种结构受限于技术瓶颈已经无法胜任,结果使得正交耦合振荡器成为少有的有效解决方案。其优越的功率和面积效率是吸引人的技术优势;不过传统的正交耦合振荡器存在相位噪声以及正交精度性能差的弊端。With the development of semiconductor integrated circuits and the vigorous development of wireless communication, the front-end circuit of the receiver is constantly facing technological innovation and performance improvement. Among them, the demand for low power consumption is becoming more and more prominent. Receiver structures are very commonly used. In retrospect, commonly used methods for generating quadrature signals include the use of analog polyphase filter structures, or digital quadrature logic gate frequency division structures, or direct quadrature coupling VCO structures; for current millimeter-wave broadband communication applications, The first two structures are limited by technical bottlenecks, which make the quadrature coupled oscillator a rare effective solution. Its superior power and area efficiency are attractive technical advantages; however, traditional quadrature coupled oscillators suffer from phase noise and poor quadrature accuracy performance.

传统技术中,低噪声放大器、混频器、和振荡器通常是模块化的设计方式,这意味着,在很大程度上,他们被设计成独立的模块,最终做连线组合。多年来,不断有创新设计正尝试将这些模块高度集成化,以降低接收机功耗的目的。典型代表如图1示,在现有的文献1中,其创新结构包含了振荡器,和混频器,其振荡器堆叠在混频器的输出负载上,共用了直流通路;该电路称为自振荡混频器。但是,振荡器的相位噪声和混频器的噪声指数存在折中问题,低相位噪声要求振荡器有足够的偏置电流,然而这样必然造成开关对贡献大得噪声,恶化混频器噪声指数,此外,该结构不具备正交性能,无法应用于主流直接变频接收机方案,为此,我们提出一种实用性更高的CMOS电流复用型自振荡接收机前端。In traditional technology, low-noise amplifiers, mixers, and oscillators are usually designed in a modular way, which means that, to a large extent, they are designed as independent modules that are eventually wired together. Over the years, there have been innovative designs trying to highly integrate these modules for the purpose of reducing receiver power consumption. A typical representative is shown in Figure 1. In the existing document 1, its innovative structure includes an oscillator and a mixer. The oscillator is stacked on the output load of the mixer and shares a DC path; the circuit is called self-oscillating mixer. However, there is a trade-off between the phase noise of the oscillator and the noise figure of the mixer. Low phase noise requires sufficient bias current for the oscillator. However, this will inevitably cause a large contribution to the noise of the switch and deteriorate the noise figure of the mixer. In addition, this structure does not have orthogonal performance and cannot be applied to mainstream direct conversion receiver solutions. Therefore, we propose a more practical CMOS current multiplexed self-oscillating receiver front end.

发明内容Contents of the invention

本发明的目的在于提供CMOS电流复用型自振荡接收机前端,解决了现有的问题。The purpose of the present invention is to provide a CMOS current multiplexing type self-oscillating receiver front end, which solves the existing problems.

为实现上述目的,本发明提供如下技术方案:CMOS电流复用型自振荡接收机前端,包括低噪声跨导放大电路和混频器,以及正交压控振荡器;To achieve the above object, the present invention provides the following technical solutions: CMOS current multiplexing type self-oscillating receiver front end, including a low-noise transconductance amplifier circuit and a mixer, and a quadrature voltage-controlled oscillator;

所述低噪声跨导放大电路Gm的输入端分别为Vin+和Vin-;The input ends of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-;

所述混频器包括第一混频器和第二混频器;The mixer includes a first mixer and a second mixer;

所述低噪声跨导放大电路Gm的输出端V1与第一混频器的输入端Vm1和第二混频器的输入端Vm3,以及正交压控振荡器QVCO的输入端VQ1连接,所述低噪声跨导放大电路Gm的输出端V2和第一混频器的输入端Vm2,与第二混频器的输入端Vm4和正交压控振荡器QVCO的输入端VQ2连接。The output terminal V1 of the low-noise transconductance amplifying circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, and the input terminal VQ1 of the quadrature voltage-controlled oscillator QVCO, so The output terminal V2 of the low-noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal VQ2 of the quadrature voltage-controlled oscillator QVCO .

优选的,所述低噪声跨导放大电路包括NMOS管Mn1、NMOS管Mn2、PMOS管Mp1、PMOS管Mp2、PMOS管Mp3、PMOS管Mp4、电容C1、电容C2、电容C3、电容C4、电容C5、电容C6、电容C16、电容C17、电容Cntr1、电容Cntr2、电感L5、电阻R9、电阻R10、电阻R11、电阻R12、电阻R13和电阻R14。Preferably, the low-noise transconductance amplifying circuit includes NMOS transistor Mn1, NMOS transistor Mn2, PMOS transistor Mp1, PMOS transistor Mp2, PMOS transistor Mp3, PMOS transistor Mp4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5 , capacitor C6, capacitor C16, capacitor C17, capacitor Cntr1, capacitor Cntr2, inductor L5, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13 and resistor R14.

优选的,所述电容C1的一端与电容C2的一端和电容C16的一端连接作为低噪声跨导放大电路的输入端Vin+,所述电容C2的另一端与NMOS管Mn1的栅端和电容Cntr1的一端和电阻R10的一端连接,所述NMOS管Mn1的源端接地,所述NMOS管Mn1的漏端与PMOS管Mp3的漏端和PMOS管Mp1的漏端与电容Cntr2的一端连接作为低噪声跨导放大电路的输出端V1,所述PMOS管Mp3的栅端与电容C1的另一端和电阻R9的一端连接,所述PMOS管Mp3的漏端接电源电压VDD,所述PMOS管Mp1的栅端与电容C6的一端和电阻R11的一端连接,所述PMOS管Mp1的源端与电容C5的一端和电容C17的一端和电感L5的a端连接,所述电感L5的c端与电源电压VDD连接,所述电感L5的b端与电容C16的另一端和电容C6的另一端与PMOS管Mp2的源端连接,所述PMOS管Mp2的栅端与电容C5的另一端和电阻R12的一端连接,所述电阻R12的另一端与电阻R11的另一端连接,所述PMOS管Mp2的漏端与电容Cntr1的另一端和PMOS管Mp4的漏端与NMOS管Mn2的漏端连接作为低噪声跨导放大电路的输出端V2,所述PMOS管Mp4的源端与电源电压VDD连接,所述PMOS管Mp4的栅端与电容C4的一端和电阻R13的一端连接,所述电容C4的另一端与电容C17的另一端和电容C3的一端连接作为低噪声跨导放大电路的输入端Vin-,所述电容C3的另一端与NMOS管Mn2的栅端和电容的Cntr2的另一端与电阻R14的一端连接,所述NMOS管Mn2的源端接地。Preferably, one end of the capacitor C1 is connected to one end of the capacitor C2 and one end of the capacitor C16 as the input terminal Vin+ of the low-noise transconductance amplifier circuit, and the other end of the capacitor C2 is connected to the gate terminal of the NMOS transistor Mn1 and the capacitor Cntr1 One end is connected to one end of the resistor R10, the source end of the NMOS transistor Mn1 is grounded, the drain end of the NMOS transistor Mn1 is connected to the drain end of the PMOS transistor Mp3 and the drain end of the PMOS transistor Mp1 is connected to one end of the capacitor Cntr2 as a low-noise crossover The output terminal V1 of the conduction amplifier circuit, the gate terminal of the PMOS transistor Mp3 is connected to the other end of the capacitor C1 and one end of the resistor R9, the drain terminal of the PMOS transistor Mp3 is connected to the power supply voltage VDD, and the gate terminal of the PMOS transistor Mp1 It is connected with one end of the capacitor C6 and one end of the resistor R11, the source end of the PMOS transistor Mp1 is connected with one end of the capacitor C5, one end of the capacitor C17 and the a end of the inductor L5, and the c end of the inductor L5 is connected with the power supply voltage VDD , the b end of the inductance L5 is connected to the other end of the capacitor C16 and the other end of the capacitor C6 is connected to the source end of the PMOS transistor Mp2, the gate end of the PMOS transistor Mp2 is connected to the other end of the capacitor C5 and one end of the resistor R12, The other end of the resistor R12 is connected to the other end of the resistor R11, the drain end of the PMOS transistor Mp2 is connected to the other end of the capacitor Cntr1 and the drain end of the PMOS transistor Mp4 is connected to the drain end of the NMOS transistor Mn2 as a low-noise transconductance amplifier The output terminal V2 of the circuit, the source terminal of the PMOS transistor Mp4 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor Mp4 is connected to one end of the capacitor C4 and one end of the resistor R13, and the other end of the capacitor C4 is connected to the capacitor C17 The other end of the capacitor C3 is connected to the input terminal Vin- of the low-noise transconductance amplifier circuit, the other end of the capacitor C3 is connected to the gate terminal of the NMOS transistor Mn2 and the other end of the capacitor Cntr2 is connected to one end of the resistor R14, The source end of the NMOS transistor Mn2 is grounded.

优选的,所述第一混频器的输出端分别为IFq+和IFq-,所述第一混频器的输入端LO0通过电容C11与正交压控振荡器QVCO的输出端VQO2连接,所述第一混频器的输入端LO2通过电容C10与正交压控振荡器QVCO的输出端VQO1连接,所述第二混频器的输出端分别为IFi+和IFi-,所述第二混频器的输入端LO3通过电容C9与正交压控振荡器QVCO的输出端VQO3连接,所述第二混频器的输入端LO1通过电容C8与正交压控振荡器QVCO的输出端VQO4连接。Preferably, the output terminals of the first mixer are respectively IFq+ and IFq-, and the input terminal LO0 of the first mixer is connected to the output terminal V QO2 of the quadrature voltage-controlled oscillator QVCO through a capacitor C11, so The input terminal LO2 of the first mixer is connected to the output terminal V QO1 of the quadrature voltage-controlled oscillator QVCO through the capacitor C10, the output terminals of the second mixer are IFi+ and IFi- respectively, and the second mixer The input terminal LO3 of the frequency mixer is connected to the output terminal V QO3 of the quadrature voltage-controlled oscillator QVCO through the capacitor C9, and the input terminal LO1 of the second mixer is connected to the output terminal V of the quadrature voltage-controlled oscillator QVCO through the capacitor C8. QO4 connection.

优选的,所述第一混频器、第二混频器结构均相同,包括PMOS管M1、PMOS管M2、NMOS管M3、NMOS管M4、NMOS管M5、NMOS管M6、电容CL1、电阻RL1、电阻RL2、电阻R7和电阻R8,以及比较器Opamp。Preferably, the structures of the first mixer and the second mixer are the same, including PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, capacitor C L1 , resistor R L1 , resistor R L2 , resistor R7 and resistor R8 , and comparator Opamp.

优选的,所述NMOS管M4的栅端与NMOS管M5的栅端连和电阻R7的一端接作为混频器的输入端VLO+,所述NMOS管M4的源端与NMOS管M3的源端连接作为Vmix+,所述NMOS管M4的漏端与PMOS管M1的漏端和电阻RL1的一端和电容CL1的一端和NMOS管M6的漏端连接作为混频器的输出端IF+,所述PMOS管M1的源端与电源电压VDD连接,所述PMOS管M1的栅端与比较器Opamp的输出端和PMOS管M2的栅端连接,所述比较器Opamp的正端接基准电压vref,所述比较器Opamp的负端与电阻RL1的另一端和电阻RL2的一端连接,所述电阻RL2的另一端与PMOS管M2的漏端和电容CL1的另一端和NMOS管M3的漏端连接作为混频器的输出端IF-,所述PMOS管M2的源端与电源电压VDD连接,所述NMOS管M3的栅端与NMOS管M6的栅端电阻R8的一端连接作为混频器的输入端VLO-,所述电阻R8的另一端与电阻R7的另一端连接,所述NMOS管M6的源端与NMOS管M5的源端连接作为Vmix-。Preferably, the gate terminal of the NMOS transistor M4 is connected to the gate terminal of the NMOS transistor M5 and one end of the resistor R7 is used as the input terminal V LO+ of the mixer, and the source terminal of the NMOS transistor M4 is connected to the source terminal of the NMOS transistor M3 Connected as Vmix+, the drain end of the NMOS transistor M4 is connected to the drain end of the PMOS transistor M1, one end of the resistor RL1, one end of the capacitor C L1 , and the drain end of the NMOS transistor M6 as the output end IF+ of the mixer. The source terminal of the PMOS transistor M1 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor M1 is connected to the output terminal of the comparator Opamp and the gate terminal of the PMOS transistor M2, and the positive terminal of the comparator Opamp is connected to the reference voltage vref, so The negative end of the comparator Opamp is connected to the other end of the resistor RL1 and one end of the resistor RL2 , and the other end of the resistor RL2 is connected to the drain end of the PMOS transistor M2, the other end of the capacitor C L1 and the drain of the NMOS transistor M3. The terminal is connected as the output terminal IF- of the mixer, the source terminal of the PMOS transistor M2 is connected to the power supply voltage VDD, the gate terminal of the NMOS transistor M3 is connected to one end of the gate terminal resistor R8 of the NMOS transistor M6 as a mixer The input terminal V LO- of the resistor R8 is connected to the other terminal of the resistor R7, and the source terminal of the NMOS transistor M6 is connected to the source terminal of the NMOS transistor M5 as Vmix-.

优选的,所述正交压控振荡器包括电感L1、电感L2、电感L3、电感L4、NMOS管Mn3、NMOS管Mn4、PMOS管Mp5、PMOS管Mp6、NMOS管Mn5、NMOS管Mn6、PMOS管M7、NMOS管M8、电阻R1、电阻R2、电阻R3、电阻R4、电阻R5、电阻R6、电容C7、电容C12、电容C13、电容Cp1、电容Cp2、电容C14、电容C15、变电容Cvar1、变电容Cvar2、变电容Cvar3和变电容Cvar4。Preferably, the quadrature voltage-controlled oscillator includes inductor L1, inductor L2, inductor L3, inductor L4, NMOS transistor Mn3, NMOS transistor Mn4, PMOS transistor Mp5, PMOS transistor Mp6, NMOS transistor Mn5, NMOS transistor Mn6, PMOS transistor M7, NMOS tube M8, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, capacitor C7, capacitor C12, capacitor C13, capacitor Cp1, capacitor Cp2, capacitor C14, capacitor C15, variable capacitor Cvar1, variable The capacitor Cvar2, the variable capacitor Cvar3 and the variable capacitor Cvar4.

优选的,所述电感L4的a端接输入端VQ1,所述电感L4的b端接输入端VQ2,所述电感L4的c端与PMOS管M7的漏端和NMOS管M8的源端和NMOS管M8的漏端连接,所述NMOS管M8的栅端与电源电压VDD连接,所述PMOS管M7的栅端接偏置电压Vbp2,所述PMOS管M7的源端与电容C7的一端和电感L3的c端连接,所述电容C7的另一端接地,所述电感L3的a端与NMOS管Mn3的源端和NMOS管Mn4的源端和PMOS管Mp5的漏端和电容Cp1的一端连接,所述NMOS管Mn3的栅端与电阻R1和电容C13的一端连接,所述NMOS管Mn3的漏端与电容C12的一端和变电容Cvar1的一端和电感L1的a端连接作为正交压控振荡器的输出端Vosc+,所述电感L1的c端接电源电压VDD,所述电感L1的b端与NMOS管Mn4的漏端与电容C13的另一端和变电容Cvar2的一端连接作为正交压控振荡器的输出端Vosc-,所述变电容Cvar2的另一端与变电容Cvar1的另一端连接,所述NMOS管Mn4的栅端与电容C12的另一端和电阻R2的一端连接,所述电阻R2的另一端与电阻R1的另一端连接,所述电感L3的b端与NMOS管Mn6的源端和NMOS管Mn5的源端和PMOS管Mp6的漏端和电容Cp2的一端连接,所述NMOS管Mn6的栅端与电阻R6和电容C14的一端连接,所述NMOS管Mn6的漏端与电容C15的一端和变电容Cvar4的一端和电感L2的b端连接作为正交压控振荡器的输出端Voscq-,所述电感L2的c端接电源电压VDD,所述电感L1的a端与NMOS管Mn5的漏端与电容C14的另一端和变电容Cvar3的一端连接作为正交压控振荡器的输出端Voscq+,所述变电容Cvar3的另一端与变电容Cvar4的另一端连接,所述NMOS管Mn5的栅端与电容C15的另一端和电阻R5的一端连接,所述电阻R5的另一端与电阻R6的另一端连接,所述PMOS管Mp6的栅端与电阻R4的一端和电容Cp1的另一端连接,所述PMOS管Mp6的源端与PMOS管Mp5的源端和电源电压VDD连接,所述PMOS管Mp5的栅端与电阻R3的一端和电容Cp2的另一端连接,所述电阻R3的另一端与电阻R4的另一端连接。Preferably, terminal a of the inductor L4 is connected to the input terminal V Q1 , terminal b of the inductor L4 is connected to the input terminal V Q2 , terminal c of the inductor L4 is connected to the drain terminal of the PMOS transistor M7 and the source terminal of the NMOS transistor M8 It is connected to the drain end of the NMOS transistor M8, the gate end of the NMOS transistor M8 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor M7 is connected to the bias voltage Vbp2, and the source end of the PMOS transistor M7 is connected to one end of the capacitor C7 It is connected to the c terminal of the inductance L3, the other end of the capacitor C7 is grounded, the a terminal of the inductance L3 is connected to the source terminal of the NMOS transistor Mn3, the source terminal of the NMOS transistor Mn4, the drain terminal of the PMOS transistor Mp5, and one end of the capacitor Cp1 connected, the gate end of the NMOS transistor Mn3 is connected to the resistor R1 and one end of the capacitor C13, and the drain end of the NMOS transistor Mn3 is connected to one end of the capacitor C12 and one end of the variable capacitor Cvar1 and the a end of the inductor L1 as an orthogonal voltage The output terminal Vosc+ of the controlled oscillator, the c terminal of the inductance L1 is connected to the power supply voltage VDD, the b terminal of the inductance L1 is connected to the drain terminal of the NMOS transistor Mn4, the other end of the capacitor C13 and one end of the variable capacitor Cvar2 as an orthogonal The output terminal Vosc- of the voltage controlled oscillator, the other end of the variable capacitor Cvar2 is connected to the other end of the variable capacitor Cvar1, the gate end of the NMOS transistor Mn4 is connected to the other end of the capacitor C12 and one end of the resistor R2, the The other end of the resistor R2 is connected to the other end of the resistor R1, and the b-end of the inductor L3 is connected to the source end of the NMOS transistor Mn6, the source end of the NMOS transistor Mn5, the drain end of the PMOS transistor Mp6, and one end of the capacitor Cp2. The gate end of the NMOS transistor Mn6 is connected to the resistor R6 and one end of the capacitor C14, and the drain end of the NMOS transistor Mn6 is connected to one end of the capacitor C15, one end of the variable capacitor Cvar4, and the b end of the inductor L2 as a quadrature voltage-controlled oscillator. The output terminal Voscq-, the c terminal of the inductance L2 is connected to the power supply voltage VDD, the a terminal of the inductance L1 is connected to the drain terminal of the NMOS transistor Mn5, the other end of the capacitor C14 and one end of the variable capacitor Cvar3 as an orthogonal voltage controlled oscillation The output terminal Voscq+ of the device, the other end of the variable capacitor Cvar3 is connected to the other end of the variable capacitor Cvar4, the gate end of the NMOS transistor Mn5 is connected to the other end of the capacitor C15 and one end of the resistor R5, and the other end of the resistor R5 One end is connected to the other end of the resistor R6, the gate end of the PMOS transistor Mp6 is connected to one end of the resistor R4 and the other end of the capacitor Cp1, the source end of the PMOS transistor Mp6 is connected to the source end of the PMOS transistor Mp5 and the power supply voltage VDD , the gate terminal of the PMOS transistor Mp5 is connected to one end of the resistor R3 and the other end of the capacitor Cp2, and the other end of the resistor R3 is connected to the other end of the resistor R4.

与现有技术相比,本发明的有益效果如下:Compared with the prior art, the beneficial effects of the present invention are as follows:

1、本发明跨导器的电流被混频器、振荡器重复使用,显著降低了功耗。1. The current of the transconductor of the present invention is reused by the mixer and the oscillator, which significantly reduces power consumption.

2、本发明的辅助正反馈交叉耦合结构提高了尾结点变压器的差模环路增益,使得正交振荡器的输出信号相位正交精度更为准确,相位噪声更低。2. The auxiliary positive feedback cross-coupling structure of the present invention improves the differential mode loop gain of the tail node transformer, making the phase quadrature accuracy of the output signal of the quadrature oscillator more accurate and the phase noise lower.

附图说明Description of drawings

图1是传统的自振荡混频器电路结构图;Fig. 1 is a circuit structure diagram of a traditional self-oscillating mixer;

图2是本发明前端架构图;Fig. 2 is a front-end architecture diagram of the present invention;

图3是本发明具体电路示意图;Fig. 3 is a schematic diagram of a specific circuit of the present invention;

图4是本发明的低噪声跨导放大电路示意图;Fig. 4 is a schematic diagram of a low-noise transconductance amplifier circuit of the present invention;

图5是本发明的混频器示意图;Fig. 5 is a schematic diagram of a mixer of the present invention;

图6是本发明的正交压控振荡器示意图;6 is a schematic diagram of a quadrature voltage-controlled oscillator of the present invention;

图7本发明的输入匹配特性S11示意图;Fig. 7 is a schematic diagram of the input matching characteristic S11 of the present invention;

图8是本发明的增益带宽示意图Fig. 8 is a schematic diagram of the gain bandwidth of the present invention

图9本发明的噪声系数示意图;Fig. 9 is a schematic diagram of the noise figure of the present invention;

图10是本发明的带内线性度示意图;Fig. 10 is a schematic diagram of in-band linearity of the present invention;

图11是本发明的正交振荡器的振荡频率示意图;Fig. 11 is a schematic diagram of the oscillation frequency of the quadrature oscillator of the present invention;

图12是本发明的相位噪声示意图;Fig. 12 is a schematic diagram of phase noise of the present invention;

图13是本发明的正交振荡器正交相位误差示意图;Fig. 13 is a schematic diagram of the quadrature phase error of the quadrature oscillator of the present invention;

图14是本发明的正交振荡器的差分相位误差示意图。FIG. 14 is a schematic diagram of the differential phase error of the quadrature oscillator of the present invention.

具体实施方式Detailed ways

下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.

具体实施案例一Specific implementation case one

如图1和图2所示,CMOS电流复用型自振荡接收机前端,包括低噪声跨导放大电路和混频器,以及正交压控振荡器;As shown in Figure 1 and Figure 2, the front end of the CMOS current multiplexed self-oscillating receiver includes a low-noise transconductance amplifier circuit, a mixer, and a quadrature voltage-controlled oscillator;

所述低噪声跨导放大电路Gm的输入端分别为Vin+和Vin-;The input ends of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-;

所述混频器包括第一混频器和第二混频器;The mixer includes a first mixer and a second mixer;

所述低噪声跨导放大电路Gm的输出端V1与第一混频器的输入端Vm1和第二混频器的输入端Vm3,以及正交压控振荡器QVCO的输入端VQ1连接,所述低噪声跨导放大电路Gm的输出端V2和第一混频器的输入端Vm2,与第二混频器的输入端Vm4和正交压控振荡器QVCO的输入端VQ2连接;The output terminal V1 of the low-noise transconductance amplifying circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, and the input terminal VQ1 of the quadrature voltage-controlled oscillator QVCO, so The output terminal V2 of the low-noise transconductance amplifying circuit Gm and the input terminal Vm2 of the first mixer are connected with the input terminal Vm4 of the second mixer and the input terminal VQ2 of the quadrature voltage-controlled oscillator QVCO ;

输入的射频信号由端口Vin+和端口Vin-双端输入,经过低噪声跨导放大电路转换为电流,经过混频器混频后得到有用的中频信号输出IFi+/-和IFq+/-,特别的,混频器的本振源由自振荡压控振荡器提供,并且振荡器、混频器的直流电流被跨导器重复使用,从而达到功耗降低效果;另外,基于超谐波耦合结构,采用了辅助交叉耦合结构,该振荡器能够提供高相位精度的本振信号。The input RF signal is input at both ends of the port Vin+ and port Vin-, and is converted into a current by a low-noise transconductance amplifier circuit, and then mixed by a mixer to obtain useful intermediate frequency signal output IFi+/- and IFq+/-, in particular, The local oscillator source of the mixer is provided by a self-oscillating voltage-controlled oscillator, and the DC current of the oscillator and the mixer is reused by the transconductor, so as to achieve the effect of reducing power consumption; in addition, based on the super-harmonic coupling structure, the With an auxiliary cross-coupling structure, the oscillator is able to provide a local oscillator signal with high phase accuracy.

参考图3,本发明的整体结构图得以清晰展示,CMOS电流复用型自振荡接收机前端,由低噪声跨导放大电路、混频器、正交压控振荡器组成;低噪声跨导器的偏置电流被混频器和振荡器复用,获得低功耗效果。With reference to Fig. 3, the overall structural diagram of the present invention can be shown clearly, and the front end of CMOS current multiplexing type self-oscillating receiver is made up of low-noise transconductance amplifying circuit, mixer, quadrature voltage-controlled oscillator; Low-noise transconductor The bias current is multiplexed by the mixer and oscillator for low power consumption.

就低噪声跨导器而言,其结构图如图4所示,它包含了电容交叉耦合的共栅极输入结构(Mp1/Mp2),用于提供输入阻抗匹配;又包含了互补共源输入级(Mn1/Mp3和Mn2/Mp4);互补共源级一方面提高电路的输入跨导,同时还可以部分消除共栅输入极的噪声,电容交叉耦合(C5、C6)又把共栅极晶体管的噪声输出减半;所以此结构很大程度上保证了电路的低噪声效果;另外,交叉耦合的中和电容(Cntr1、Cntr2)用于降低弥勒效应对输入匹配的不利影响。As far as the low-noise transconductor is concerned, its structure diagram is shown in Figure 4, which includes a capacitive cross-coupled common-gate input structure (Mp1/Mp2) to provide input impedance matching; it also includes a complementary common-source input stage (Mn1/Mp3 and Mn2/Mp4); on the one hand, the complementary common-source stage improves the input transconductance of the circuit, and at the same time, it can partially eliminate the noise of the common-gate input pole, and the capacitive cross-coupling (C5, C6) turns the common-gate transistor The noise output is halved; so this structure largely guarantees the low noise effect of the circuit; in addition, the cross-coupled neutralization capacitors (Cntr1, Cntr2) are used to reduce the adverse influence of the Miller effect on the input matching.

混频器电路在图5给出,基于经典吉尔伯特全差分结构,在其中频负载处使用了有源反馈结构;有源反馈结构采样负载电阻的共模电平,经过比较器的反馈控制晶体管栅极偏置,从而保证负载的直流电平偏置合适,获得好的线性度;同时,振荡器的偏置电流通过晶体管M7分流了跨导器的偏置电流,使得混频器获得了减小的偏置电流,减小的噪声输出,间接获得了电流注入的技术效果;进一步,电感L4用于谐振吸收混频器开关管的尾结点寄生电容,使得开关管的噪声充放电效应得以避免,也利于整体电路的低噪声效果。The mixer circuit is shown in Figure 5, based on the classic Gilbert fully differential structure, an active feedback structure is used at the intermediate frequency load; the active feedback structure samples the common-mode level of the load resistance, and is controlled by the feedback of the comparator Transistor gate bias, so as to ensure that the DC level of the load is properly biased and obtain good linearity; at the same time, the bias current of the oscillator shunts the bias current of the transconductor through the transistor M7, so that the mixer obtains a reduction The small bias current and reduced noise output indirectly obtain the technical effect of current injection; furthermore, the inductance L4 is used to resonantly absorb the parasitic capacitance of the tail node of the switch tube of the mixer, so that the noise charging and discharging effect of the switch tube can be eliminated. Avoidance is also beneficial to the low-noise effect of the overall circuit.

正交振荡器电路在图6展示,包含了两个主LC振荡器和一个辅助正反馈交叉耦合结构(Mp5/Mp6);具体地,两个LC振荡器在尾节点处使用了变压器(L3)的耦合结构;这样在保证该变压器在2f0频率下的反向耦合谐振(变压器自感与该节点处的寄生电容),就可以形成LC振荡器的f0频率下正交振荡,但是2f0频率信号幅度很弱,变压器耦合系数常常又小于1,这样在考虑到版图产生的失配,以及跨导器、混频器通过M7路径泄露的射频信号,对变压器产生的较强共模干扰,很可能破坏LC振荡器的f0频率下正交振荡,变成不希望的同向振荡。The quadrature oscillator circuit shown in Figure 6 consists of two main LC oscillators and an auxiliary positive feedback cross-coupled structure (Mp5/Mp6); specifically, the two LC oscillators use a transformer (L3) at the tail node The coupling structure; in this way, in order to ensure the reverse coupling resonance of the transformer at 2f0 frequency (transformer self-inductance and parasitic capacitance at this node), quadrature oscillation at the f0 frequency of the LC oscillator can be formed, but the 2f0 frequency signal amplitude It is very weak, and the coupling coefficient of the transformer is often less than 1. In this way, considering the mismatch generated by the layout, and the RF signal leaked by the transconductor and the mixer through the M7 path, the strong common-mode interference generated by the transformer is likely to damage the transformer. The quadrature oscillation at f0 frequency of the LC oscillator becomes undesired oscillation in the same direction.

为了解决这个问题,一方面,可以在变压器处设计一个正反馈环路,来适当提高尾结点的差模环路增益,从而改善LC振荡器的输出信号正交性;当然差模环路增益也不能过大,使得正反馈交叉耦合结构和变压器构成在2f0频率下的又一个振荡器,影响主LC振荡器晶体管的开启关断;具体地,可以通过调节控制偏置电压Vadj实现对差模环路增益的控制调谐;另一方面,通过M7路径添加滤波电容来克服跨导器混频器的射频信号泄露;在射频输入差分对版图失配情况下,必然存在射频口信号以共模方式干扰振荡器尾结点变压器的差模工作;当然混频器尾结点的2f0谐波频率信号则直接构成了振荡器尾结点变压器的共模干扰。针对这两种机制,可以添加两个电容M8,C7加以滤除;这里晶体管M8则充当了滤波电容的效果,虽然晶体管电容存在噪声和分线性缺点,但是这里晶体管M8位于共模路径,不会对混频器的输出产生影响,C7电容又可以吸收晶体管M8噪声和非线性对振荡器的干扰,正是得益于以上的这些设计策略,使得本发明的正交振荡器的精度得以提升和保证。In order to solve this problem, on the one hand, a positive feedback loop can be designed at the transformer to appropriately increase the differential-mode loop gain of the tail node, thereby improving the orthogonality of the output signal of the LC oscillator; of course, the differential-mode loop gain It cannot be too large, so that the positive feedback cross-coupling structure and the transformer constitute another oscillator at the frequency of 2f0, which affects the turn-on and turn-off of the main LC oscillator transistor; specifically, the differential mode can be realized by adjusting the control bias voltage Vadj Control and tuning of loop gain; on the other hand, add a filter capacitor through the M7 path to overcome the RF signal leakage of the transconductor mixer; in the case of RF input differential pair layout mismatch, there must be RF port signals in common mode Interfering with the differential-mode operation of the transformer at the tail node of the oscillator; of course, the 2f0 harmonic frequency signal at the tail node of the mixer directly constitutes the common-mode interference of the transformer at the tail node of the oscillator. For these two mechanisms, two capacitors M8 and C7 can be added to filter out; here the transistor M8 acts as a filter capacitor. Although the transistor capacitor has the disadvantages of noise and linearity, the transistor M8 is located in the common mode path and will not It has an impact on the output of the mixer, and the C7 capacitor can absorb the noise of the transistor M8 and the nonlinear interference to the oscillator. Thanks to the above design strategies, the accuracy of the quadrature oscillator of the present invention can be improved and improved. ensure.

注入锁定也是一个要考虑的技术问题,在文献2中,射频口的信号较强的情况下,是可以通过混频器晶体管的寄生电容耦合到中频负载的输出节点,从而可能造成该处的振荡器发生注入锁定现象,混频器无法工作在期望的中频频率处;对比而言,本发明的结构,射频口的较强信号可被两个电容M8,C7加以滤除,M7晶体管还可以起到一定的反向隔离效果,使得本发明更不容易发生注入锁定的现象。Injection locking is also a technical issue to be considered. In Document 2, when the signal of the radio frequency port is strong, it can be coupled to the output node of the intermediate frequency load through the parasitic capacitance of the mixer transistor, which may cause oscillation there Injection locking occurs in the mixer, and the mixer cannot work at the desired intermediate frequency; in contrast, with the structure of the present invention, the stronger signal of the radio frequency port can be filtered by two capacitors M8 and C7, and the M7 transistor can also act A certain reverse isolation effect is obtained, which makes the injection locking phenomenon less likely to occur in the present invention.

具体实施案例二Specific implementation case two

本实施例提供的一种电流复用自振荡直接变频接收机前端电路采用65nm标准CMOS工艺设计实现。The front-end circuit of a current multiplexing self-oscillating direct-conversion receiver provided in this embodiment is designed and realized by using a 65nm standard CMOS process.

电路中仅混频器的中频负载晶体管(M1/M2)采用250nm长沟道结构以降低闪烁噪声,其它晶体管都使用60nm长度获得好的射频性能;电源电压为1.2V,差分跨导器消耗电流为4.6mA*2,整体功耗12mW,混频器单个晶体管的偏置电流为128uA,工模路径中M7的电流为3.3mA,辅助交叉单元耦合消耗电流0.3mA,共栅输入级偏置电流0.6mA,电容C7取15pF,晶体管M8等效电容为200pF;基于以上的优化偏置电流,得以获取电路模拟性能,结果如下。In the circuit, only the intermediate frequency load transistor (M1/M2) of the mixer adopts a 250nm long channel structure to reduce flicker noise, and the other transistors use a 60nm length to obtain good RF performance; the power supply voltage is 1.2V, and the differential transconductor consumes current is 4.6mA*2, the overall power consumption is 12mW, the bias current of a single transistor of the mixer is 128uA, the current of M7 in the working mode path is 3.3mA, the auxiliary cross unit coupling consumes 0.3mA, and the bias current of the common gate input stage 0.6mA, the capacitor C7 is 15pF, and the equivalent capacitance of the transistor M8 is 200pF; based on the above optimized bias current, the circuit simulation performance can be obtained, and the results are as follows.

图7给出了电路的输入匹配特性S11的模拟结果,可以看出,在7.7-9.8GHz频带范围内S11均小于-10dB;Figure 7 shows the simulation results of the input matching characteristic S11 of the circuit. It can be seen that S11 is less than -10dB in the 7.7-9.8GHz frequency band;

图8给出了电路的增益带宽的模拟结果,3dB带宽约为50MHz,在低频处,增益高达34.8dB;Figure 8 shows the simulation results of the gain bandwidth of the circuit, the 3dB bandwidth is about 50MHz, and the gain is as high as 34.8dB at low frequencies;

图9给出了电路的噪声系数NF的模拟结果,可以看出,在1MHz到100MHz内,噪声系数都低于3dB。且闪烁噪声拐角在400KHz附近;Figure 9 shows the simulation results of the noise figure NF of the circuit. It can be seen that the noise figure is lower than 3dB from 1MHz to 100MHz. And the flicker noise corner is around 400KHz;

图10给出了电路的三阶交调输入IP3的模拟结果,为-19.5dBm;Figure 10 shows the simulation result of the third-order intermodulation input IP3 of the circuit, which is -19.5dBm;

图11给出了电路的正交振荡器输出波形,四路信号的频率都为8.5215GHz,调节振荡器的调谐电容可以对频率做一定范围的改变,这里不再给出图示;Figure 11 shows the output waveform of the quadrature oscillator of the circuit. The frequency of the four signals is 8.5215 GHz. Adjusting the tuning capacitor of the oscillator can change the frequency within a certain range, and no illustration is given here;

图12给出了电路的相位噪声的模拟结果,在0.1MHz到1MHz频率范围内,相位噪声从-80dBc/Hz降到-108dBc/Hz,得益于振荡器辅助的交叉耦合结构,以及CLASS C配置(避免主振荡器晶体管进入深度三极管区,而导致的LC谐振网络有载Q值得退化),相位噪声获得了良好水平;Figure 12 shows the simulation results of the phase noise of the circuit. In the frequency range of 0.1MHz to 1MHz, the phase noise drops from -80dBc/Hz to -108dBc/Hz, thanks to the oscillator-assisted cross-coupling structure, and CLASS C configuration (avoiding the main oscillator transistor entering the deep triode region, resulting in the degradation of the loaded Q value of the LC resonant network), the phase noise has achieved a good level;

图13给出了正交振荡器的正交端口之间的270°相位误差模拟结果,通过图示延时曲线得知其相位正交误差约在2°以内,其稳定时间约8ns。仿真也表明,在不使用辅助交叉耦合结构下,所得到的正交误差在5°左右,这里不再给出单独的图示,越低的正交误差意味着接收机可以在基带获得更好的解调信噪比;Figure 13 shows the simulation results of the 270° phase error between the quadrature ports of the quadrature oscillator. It can be seen from the delay curve that the phase quadrature error is within 2° and the stabilization time is about 8 ns. The simulation also shows that without using the auxiliary cross-coupling structure, the obtained quadrature error is about 5°, no separate illustration is given here, the lower the quadrature error means that the receiver can obtain better The demodulation signal-to-noise ratio;

图14给出了电路的正交振荡器差分端口的180°相位误差的模拟结果,延时曲线显示单个振荡器有好的差分性能,且稳定时间在1ns以内。Figure 14 shows the simulation results of the 180° phase error of the differential port of the quadrature oscillator of the circuit. The delay curve shows that a single oscillator has good differential performance, and the stabilization time is within 1ns.

表1给出了本发明和以往文献的性能综合对比,可以看到,表明上消耗功率相同,但是本发明结构提供了IQ的双通道接收方式,比对比文献实现同样的双通道接收,节约了一半功率,使得本发明非常有竞争力;在关键的电学指标上,如增益,噪声/相位噪声,本发明也获得了压倒性的技术优势,即便是线性度,如果用输出的IP3(OIP3)来衡量,本发明也有显著优势;对比文献需要6个电感,占用大得面积;本发明要5个电感/变压器,降低了芯片的面积、成本,基于以上的对比和讨论,整体上本发明提出了一种电流复用型正交接收机前端;振荡器、混频器的电流被跨导器重复使用,高度集成的电路结构显著降低了功耗、乃至简化了偏置电路;包含辅助交叉耦合结构的正交振荡器则提供了更为准确的相位精度,更低的相位噪声。Table 1 has provided the comprehensive comparison of the performance of the present invention and previous documents, and it can be seen that the upper consumption power is the same, but the structure of the present invention provides a dual-channel reception mode of IQ, which realizes the same dual-channel reception than the comparison document, saving Half the power makes this invention very competitive; on key electrical indicators, such as gain, noise/phase noise, this invention has also obtained overwhelming technical advantages, even if it is linearity, if you use the output IP3 (OIP3) To measure, the present invention also has significant advantages; the comparative literature requires 6 inductors, which takes up a large area; the present invention requires 5 inductors/transformers, which reduces the area and cost of the chip. Based on the above comparison and discussion, the present invention proposes on the whole A current-multiplexing quadrature receiver front-end is developed; the current of the oscillator and the mixer is reused by the transconductor, and the highly integrated circuit structure significantly reduces power consumption and even simplifies the bias circuit; includes auxiliary cross-coupling The quadrature oscillator of the structure provides more accurate phase precision and lower phase noise.

表1综合性能对比Table 1 Comprehensive performance comparison

Figure BDA0003880488420000101
Figure BDA0003880488420000101

其中,参考文献1和2均为【Stanley S.K.Ho;Carlos E.Saavedra“A Low-NoiseSelf-Oscillating Mixer Using a Balanced VCO Load,”IEEE Transactions onCircuits and Systems,vol.58,no.8,pp.1705–1712,Feb.2011.】。Among them, references 1 and 2 are [Stanley S.K.Ho; Carlos E.Saavedra "A Low-Noise Self-Oscillating Mixer Using a Balanced VCO Load," IEEE Transactions on Circuits and Systems, vol.58, no.8, pp.1705 –1712, Feb. 2011.].

Claims (8)

1.CMOS电流复用型自振荡接收机前端,其特征在于,包括低噪声跨导放大电路和混频器,以及正交压控振荡器;1. The CMOS current multiplexing type self-oscillating receiver front end is characterized in that it includes a low-noise transconductance amplifier circuit and a mixer, and a quadrature voltage-controlled oscillator; 所述低噪声跨导放大电路Gm的输入端分别为Vin+和Vin-;The input ends of the low-noise transconductance amplifying circuit Gm are respectively Vin+ and Vin-; 所述混频器包括第一混频器和第二混频器;The mixer includes a first mixer and a second mixer; 所述低噪声跨导放大电路Gm的输出端V1与第一混频器的输入端Vm1和第二混频器的输入端Vm3,以及正交压控振荡器QVCO的输入端VQ1连接,所述低噪声跨导放大电路Gm的输出端V2和第一混频器的输入端Vm2,与第二混频器的输入端Vm4和正交压控振荡器QVCO的输入端VQ2连接。The output terminal V1 of the low-noise transconductance amplifying circuit Gm is connected to the input terminal Vm1 of the first mixer and the input terminal Vm3 of the second mixer, and the input terminal VQ1 of the quadrature voltage-controlled oscillator QVCO, so The output terminal V2 of the low-noise transconductance amplifier circuit Gm and the input terminal Vm2 of the first mixer are connected to the input terminal Vm4 of the second mixer and the input terminal VQ2 of the quadrature voltage-controlled oscillator QVCO . 2.根据权利要求1所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述低噪声跨导放大电路包括NMOS管Mn1、NMOS管Mn2、PMOS管Mp1、PMOS管Mp2、PMOS管Mp3、PMOS管Mp4、电容C1、电容C2、电容C3、电容C4、电容C5、电容C6、电容C16、电容C17、电容Cntr1、电容Cntr2、电感L5、电阻R9、电阻R10、电阻R11、电阻R12、电阻R13和电阻R14。2. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the low-noise transconductance amplifying circuit comprises NMOS transistor Mn1, NMOS transistor Mn2, PMOS transistor Mp1, PMOS transistor Mp2, PMOS transistor Tube Mp3, PMOS tube Mp4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C16, capacitor C17, capacitor Cntr1, capacitor Cntr2, inductor L5, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13 and resistor R14. 3.根据权利要求1所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述电容C1的一端与电容C2的一端和电容C16的一端连接作为低噪声跨导放大电路的输入端Vin+,所述电容C2的另一端与NMOS管Mn1的栅端和电容Cntr1的一端和电阻R10的一端连接,所述NMOS管Mn1的源端接地,所述NMOS管Mn1的漏端与PMOS管Mp3的漏端和PMOS管Mp1的漏端与电容Cntr2的一端连接作为低噪声跨导放大电路的输出端V1,所述PMOS管Mp3的栅端与电容C1的另一端和电阻R9的一端连接,所述PMOS管Mp3的漏端接电源电压VDD,所述PMOS管Mp1的栅端与电容C6的一端和电阻R11的一端连接,所述PMOS管Mp1的源端与电容C5的一端和电容C17的一端和电感L5的a端连接,所述电感L5的c端与电源电压VDD连接,所述电感L5的b端与电容C16的另一端和电容C6的另一端与PMOS管Mp2的源端连接,所述PMOS管Mp2的栅端与电容C5的另一端和电阻R12的一端连接,所述电阻R12的另一端与电阻R11的另一端连接,所述PMOS管Mp2的漏端与电容Cntr1的另一端和PMOS管Mp4的漏端与NMOS管Mn2的漏端连接作为低噪声跨导放大电路的输出端V2,所述PMOS管Mp4的源端与电源电压VDD连接,所述PMOS管Mp4的栅端与电容C4的一端和电阻R13的一端连接,所述电容C4的另一端与电容C17的另一端和电容C3的一端连接作为低噪声跨导放大电路的输入端Vin-,所述电容C3的另一端与NMOS管Mn2的栅端和电容的Cntr2的另一端与电阻R14的一端连接,所述NMOS管Mn2的源端接地。3. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein one end of the capacitor C1 is connected with one end of the capacitor C2 and one end of the capacitor C16 as an input of a low-noise transconductance amplifier circuit Terminal Vin+, the other end of the capacitor C2 is connected to the gate end of the NMOS transistor Mn1 and one end of the capacitor Cntr1 and one end of the resistor R10, the source end of the NMOS transistor Mn1 is grounded, and the drain end of the NMOS transistor Mn1 is connected to the PMOS transistor The drain end of Mp3 and the drain end of the PMOS transistor Mp1 are connected to one end of the capacitor Cntr2 as the output end V1 of the low-noise transconductance amplifier circuit, and the gate end of the PMOS transistor Mp3 is connected to the other end of the capacitor C1 and one end of the resistor R9, The drain terminal of the PMOS transistor Mp3 is connected to the power supply voltage VDD, the gate terminal of the PMOS transistor Mp1 is connected to one end of the capacitor C6 and one end of the resistor R11, and the source end of the PMOS transistor Mp1 is connected to one end of the capacitor C5 and the capacitor C17. One end is connected to the a terminal of the inductor L5, the c terminal of the inductor L5 is connected to the power supply voltage VDD, the b terminal of the inductor L5 is connected to the other end of the capacitor C16 and the other end of the capacitor C6 is connected to the source end of the PMOS transistor Mp2, The gate end of the PMOS transistor Mp2 is connected to the other end of the capacitor C5 and one end of the resistor R12, the other end of the resistor R12 is connected to the other end of the resistor R11, and the drain end of the PMOS transistor Mp2 is connected to the other end of the capacitor Cntr1 The drain end of the PMOS transistor Mp4 is connected to the drain end of the NMOS transistor Mn2 as the output end V2 of the low-noise transconductance amplifier circuit, the source end of the PMOS transistor Mp4 is connected to the power supply voltage VDD, and the gate end of the PMOS transistor Mp4 is connected to the power supply voltage VDD. One end of the capacitor C4 is connected to one end of the resistor R13, the other end of the capacitor C4 is connected to the other end of the capacitor C17 and one end of the capacitor C3 as the input terminal Vin- of the low-noise transconductance amplifier circuit, and the other end of the capacitor C3 The gate terminal of the NMOS transistor Mn2 and the other end of the capacitor Cntr2 are connected to one end of the resistor R14, and the source terminal of the NMOS transistor Mn2 is grounded. 4.根据权利要求1所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述第一混频器的输出端分别为IFq+和IFq-,所述第一混频器的输入端LO0通过电容C11与正交压控振荡器QVCO的输出端VQO2连接,所述第一混频器的输入端LO2通过电容C10与正交压控振荡器QVCO的输出端VQO1连接,所述第二混频器的输出端分别为IFi+和IFi-,所述第二混频器的输入端LO3通过电容C9与正交压控振荡器QVCO的输出端VQO3连接,所述第二混频器的输入端LO1通过电容C8与正交压控振荡器QVCO的输出端VQO4连接。4. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the output terminals of the first mixer are respectively IFq+ and IFq-, and the input of the first mixer The terminal LO0 is connected to the output terminal V QO2 of the quadrature voltage-controlled oscillator QVCO through the capacitor C11, and the input terminal LO2 of the first mixer is connected to the output terminal V QO1 of the quadrature voltage-controlled oscillator QVCO through the capacitor C10, so The output terminals of the second mixer are respectively IFi+ and IFi-, the input terminal LO3 of the second mixer is connected with the output terminal V QO3 of the quadrature voltage-controlled oscillator QVCO through a capacitor C9, and the second mixer The input terminal LO1 of the frequency converter is connected to the output terminal V QO4 of the quadrature voltage-controlled oscillator QVCO through a capacitor C8. 5.根据权利要求1所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述第一混频器、第二混频器结构均相同,包括PMOS管M1、PMOS管M2、NMOS管M3、NMOS管M4、NMOS管M5、NMOS管M6、电容CL1、电阻RL1、电阻RL2、电阻R7和电阻R8,以及比较器Opamp。5. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the first mixer and the second mixer have the same structure, including PMOS transistors M1, PMOS transistors M2, NMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, capacitor C L1 , resistor R L1 , resistor R L2 , resistor R7 and resistor R8, and a comparator Opamp. 6.根据权利要求5所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述NMOS管M4的栅端与NMOS管M5的栅端连和电阻R7的一端接作为混频器的输入端VLO+,所述NMOS管M4的源端与NMOS管M3的源端连接作为Vmix+,所述NMOS管M4的漏端与PMOS管M1的漏端和电阻RL1的一端和电容CL1的一端和NMOS管M6的漏端连接作为混频器的输出端IF+,所述PMOS管M1的源端与电源电压VDD连接,所述PMOS管M1的栅端与比较器Opamp的输出端和PMOS管M2的栅端连接,所述比较器Opamp的正端接基准电压vref,所述比较器Opamp的负端与电阻RL1的另一端和电阻RL2的一端连接,所述电阻RL2的另一端与PMOS管M2的漏端和电容CL1的另一端和NMOS管M3的漏端连接作为混频器的输出端IF-,所述PMOS管M2的源端与电源电压VDD连接,所述NMOS管M3的栅端与NMOS管M6的栅端电阻R8的一端连接作为混频器的输入端VLO-,所述电阻R8的另一端与电阻R7的另一端连接,所述NMOS管M6的源端与NMOS管M5的源端连接作为Vmix-。6. The CMOS current multiplexing type self-oscillating receiver front end according to claim 5, characterized in that, the grid end of the NMOS transistor M4 is connected to the grid end of the NMOS transistor M5 and one end of the resistor R7 is used as a mixer The input terminal V LO+ of the NMOS transistor M4 is connected to the source terminal of the NMOS transistor M3 as Vmix+, the drain terminal of the NMOS transistor M4 is connected to the drain terminal of the PMOS transistor M1 and one end of the resistor RL1 and the capacitor C L1 One end of the PMOS transistor M1 is connected to the drain end of the NMOS transistor M6 as the output end IF+ of the mixer, the source end of the PMOS transistor M1 is connected to the power supply voltage VDD, the gate end of the PMOS transistor M1 is connected to the output end of the comparator Opamp and the PMOS The gate terminal of the tube M2 is connected, the positive terminal of the comparator Opamp is connected to the reference voltage vref, the negative terminal of the comparator Opamp is connected to the other end of the resistor RL1 and one end of the resistor RL2 , and the other end of the resistor RL2 One end is connected to the drain end of the PMOS transistor M2 and the other end of the capacitor C L1 is connected to the drain end of the NMOS transistor M3 as the output end IF- of the mixer, the source end of the PMOS transistor M2 is connected to the power supply voltage VDD, and the NMOS transistor M3 The gate terminal of the tube M3 is connected to one end of the gate terminal resistor R8 of the NMOS tube M6 as the input terminal V LO- of the mixer, the other end of the resistor R8 is connected to the other end of the resistor R7, and the source of the NMOS tube M6 The terminal is connected to the source terminal of the NMOS transistor M5 as Vmix-. 7.根据权利要求1所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述正交压控振荡器包括电感L1、电感L2、电感L3、电感L4、NMOS管Mn3、NMOS管Mn4、PMOS管Mp5、PMOS管Mp6、NMOS管Mn5、NMOS管Mn6、PMOS管M7、NMOS管M8、电阻R1、电阻R2、电阻R3、电阻R4、电阻R5、电阻R6、电容C7、电容C12、电容C13、电容Cp1、电容Cp2、电容C14、电容C15、变电容Cvar1、变电容Cvar2、变电容Cvar3和变电容Cvar4。7. The CMOS current multiplexing type self-oscillating receiver front end according to claim 1, wherein the quadrature voltage-controlled oscillator comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an NMOS transistor Mn3, an NMOS Tube Mn4, PMOS tube Mp5, PMOS tube Mp6, NMOS tube Mn5, NMOS tube Mn6, PMOS tube M7, NMOS tube M8, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, capacitor C7, capacitor C12 , capacitor C13, capacitor Cp1, capacitor Cp2, capacitor C14, capacitor C15, variable capacitor Cvar1, variable capacitor Cvar2, variable capacitor Cvar3 and variable capacitor Cvar4. 8.根据权利要求7所述的CMOS电流复用型自振荡接收机前端,其特征在于,所述电感L4的a端接输入端VQ1,所述电感L4的b端接输入端VQ2,所述电感L4的c端与PMOS管M7的漏端和NMOS管M8的源端和NMOS管M8的漏端连接,所述NMOS管M8的栅端与电源电压VDD连接,所述PMOS管M7的栅端接偏置电压Vbp2,所述PMOS管M7的源端与电容C7的一端和电感L3的c端连接,所述电容C7的另一端接地,所述电感L3的a端与NMOS管Mn3的源端和NMOS管Mn4的源端和PMOS管Mp5的漏端和电容Cp1的一端连接,所述NMOS管Mn3的栅端与电阻R1和电容C13的一端连接,所述NMOS管Mn3的漏端与电容C12的一端和变电容Cvar1的一端和电感L1的a端连接作为正交压控振荡器的输出端Vosc+,所述电感L1的c端接电源电压VDD,所述电感L1的b端与NMOS管Mn4的漏端与电容C13的另一端和变电容Cvar2的一端连接作为正交压控振荡器的输出端Vosc-,所述变电容Cvar2的另一端与变电容Cvar1的另一端连接,所述NMOS管Mn4的栅端与电容C12的另一端和电阻R2的一端连接,所述电阻R2的另一端与电阻R1的另一端连接,所述电感L3的b端与NMOS管Mn6的源端和NMOS管Mn5的源端和PMOS管Mp6的漏端和电容Cp2的一端连接,所述NMOS管Mn6的栅端与电阻R6和电容C14的一端连接,所述NMOS管Mn6的漏端与电容C15的一端和变电容Cvar4的一端和电感L2的b端连接作为正交压控振荡器的输出端Voscq-,所述电感L2的c端接电源电压VDD,所述电感L1的a端与NMOS管Mn5的漏端与电容C14的另一端和变电容Cvar3的一端连接作为正交压控振荡器的输出端Voscq+,所述变电容Cvar3的另一端与变电容Cvar4的另一端连接,所述NMOS管Mn5的栅端与电容C15的另一端和电阻R5的一端连接,所述电阻R5的另一端与电阻R6的另一端连接,所述PMOS管Mp6的栅端与电阻R4的一端和电容Cp1的另一端连接,所述PMOS管Mp6的源端与PMOS管Mp5的源端和电源电压VDD连接,所述PMOS管Mp5的栅端与电阻R3的一端和电容Cp2的另一端连接,所述电阻R3的另一端与电阻R4的另一端连接。8. The front end of the CMOS current multiplexed self-oscillating receiver according to claim 7, wherein the a-terminal of the inductance L4 is connected to the input terminal V Q1 , and the b-terminal of the inductance L4 is connected to the input terminal V Q2 , The c terminal of the inductor L4 is connected to the drain terminal of the PMOS transistor M7 and the source terminal of the NMOS transistor M8 and the drain terminal of the NMOS transistor M8, the gate terminal of the NMOS transistor M8 is connected to the power supply voltage VDD, and the PMOS transistor M7 The gate terminal is connected to the bias voltage Vbp2, the source terminal of the PMOS transistor M7 is connected to one end of the capacitor C7 and the c-terminal of the inductance L3, the other end of the capacitor C7 is grounded, and the a-terminal of the inductance L3 is connected to the terminal a of the NMOS transistor Mn3 The source end is connected to the source end of the NMOS transistor Mn4 and the drain end of the PMOS transistor Mp5 and one end of the capacitor Cp1, the gate end of the NMOS transistor Mn3 is connected to the resistor R1 and one end of the capacitor C13, and the drain end of the NMOS transistor Mn3 is connected to One end of the capacitor C12, one end of the variable capacitor Cvar1, and the a-end of the inductor L1 are connected as the output end Vosc+ of the quadrature voltage-controlled oscillator, the c-terminal of the inductor L1 is connected to the power supply voltage VDD, and the b-terminal of the inductor L1 is connected to the NMOS The drain end of the tube Mn4 is connected to the other end of the capacitor C13 and one end of the variable capacitor Cvar2 as the output terminal Vosc- of the quadrature voltage-controlled oscillator, and the other end of the variable capacitor Cvar2 is connected to the other end of the variable capacitor Cvar1. The gate end of the NMOS transistor Mn4 is connected to the other end of the capacitor C12 and one end of the resistor R2, the other end of the resistor R2 is connected to the other end of the resistor R1, the b end of the inductor L3 is connected to the source end of the NMOS transistor Mn6 and the NMOS The source end of the tube Mn5 is connected to the drain end of the PMOS transistor Mp6 and one end of the capacitor Cp2, the gate end of the NMOS transistor Mn6 is connected to the resistor R6 and one end of the capacitor C14, and the drain end of the NMOS transistor Mn6 is connected to one end of the capacitor C15 One end of the variable capacitor Cvar4 is connected to the b end of the inductor L2 as the output end Voscq- of the quadrature voltage controlled oscillator, the c end of the inductor L2 is connected to the power supply voltage VDD, the a end of the inductor L1 is connected to the NMOS tube Mn5 The drain terminal is connected to the other end of the capacitor C14 and one end of the variable capacitor Cvar3 as the output terminal Voscq+ of the quadrature voltage controlled oscillator, the other end of the variable capacitor Cvar3 is connected to the other end of the variable capacitor Cvar4, and the NMOS tube Mn5 The gate end is connected to the other end of the capacitor C15 and one end of the resistor R5, the other end of the resistor R5 is connected to the other end of the resistor R6, and the gate end of the PMOS transistor Mp6 is connected to one end of the resistor R4 and the other end of the capacitor Cp1 , the source end of the PMOS transistor Mp6 is connected to the source end of the PMOS transistor Mp5 and the power supply voltage VDD, the gate end of the PMOS transistor Mp5 is connected to one end of the resistor R3 and the other end of the capacitor Cp2, and the other end of the resistor R3 Connect with the other end of resistor R4.
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