CN115632653A - Phase discrimination method, phase discriminator, clock recovery module, ethernet chip and vehicle - Google Patents

Phase discrimination method, phase discriminator, clock recovery module, ethernet chip and vehicle Download PDF

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Publication number
CN115632653A
CN115632653A CN202211309902.4A CN202211309902A CN115632653A CN 115632653 A CN115632653 A CN 115632653A CN 202211309902 A CN202211309902 A CN 202211309902A CN 115632653 A CN115632653 A CN 115632653A
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current
value
decision value
input signal
phase
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王万亭
王振国
刘超
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Beijing Neuron Network Technology Co ltd
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Beijing Neuron Network Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

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Abstract

The invention discloses a phase discrimination method, a phase discriminator, a clock recovery module, an Ethernet chip and a vehicle. The method comprises the following steps: acquiring a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relation between a pre-established weight coefficient and a decision value range; calculating a current weighted decision value under the current clock cycle according to the target weight coefficient and the current decision value, and generating a current error value under the current clock cycle according to the current weighted decision value; and calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock period and the delay error value. By the technical scheme, the phase deviation corresponding to the input signal can be accurately calculated, and the accuracy of the input signal is improved.

Description

Phase discrimination method, phase discriminator, clock recovery module, ethernet chip and vehicle
Technical Field
The invention relates to the technical field of vehicle-mounted communication, in particular to a phase discrimination method, a phase discriminator, a clock recovery module, an Ethernet chip and a vehicle.
Background
When a signal transmitted by a host vehicle is received from the vehicle, an input signal is generally acquired by means of a/D sampling, however, the phase of the input signal may be deviated due to the influence of noise and the like during sampling.
In the prior art, a digital phase detector is usually used to process an input signal to obtain a corresponding phase result, but when a multi-level pulse amplitude modulation system is adopted as a master device, since levels and phases corresponding to error values generated by different levels are not linearly related, if the digital phase detector in the prior art is used to calculate a phase difference of the input signal generated by the multi-level pulse amplitude modulation system, a large difference exists between the actual phase difference and the phase difference. Therefore, how to accurately calculate the phase deviation corresponding to the input signal, and improve the accuracy of the input signal is a problem to be solved urgently at present.
Disclosure of Invention
The invention provides a phase discrimination method, a phase discriminator, a clock recovery module, an Ethernet chip and a vehicle, which can solve the problem of low accuracy of phase deviation calculation corresponding to input signals.
According to an aspect of the present invention, there is provided a phase detection method, including:
acquiring a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relation between a pre-established weight coefficient and a decision value range;
calculating a current weighted decision value under the current clock cycle according to the target weight coefficient and the current decision value, and generating a current error value under the current clock cycle according to the current weighted decision value;
and calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock period and the delay error value.
According to another aspect of the present invention, there is provided a phase detector including:
the table look-up circuit is used for acquiring a target weight coefficient corresponding to the current decision value of the current input signal according to a mapping relation between the pre-established weight coefficient and the decision value range;
the current weighted decision value calculating circuit is used for calculating a current weighted decision value in the current clock period according to the target weight coefficient and the current decision value;
a current error value calculation circuit for generating a current error value in a current clock cycle according to the current weighted decision value;
and the phase error calculation circuit is used for calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock cycle and the delay error value.
According to another aspect of the present invention, there is provided a clock recovery module including: the phase detector, the loop filter, the loop amplifier and the voltage-controlled oscillator; the phase discriminator is connected with the loop filter, the loop filter is connected with the loop amplifier, the loop amplifier is connected with the voltage-controlled oscillator, and the voltage-controlled oscillator is connected with the phase discriminator;
the phase discriminator is used for calculating the phase deviation corresponding to the current input signal to obtain the error voltage containing the phase deviation;
the loop filter is used for filtering high-frequency components in the error voltage to obtain a control voltage;
the loop amplifier is used for enhancing the control voltage to obtain a voltage pulse signal;
and the voltage-controlled oscillator is used for generating an output voltage signal according to the voltage pulse signal.
According to another aspect of the present invention, there is provided an ethernet port physical layer PHY chip, including:
the clock recovery module is used for judging a current input signal acquired in a current clock period to obtain a voltage pulse signal corresponding to the current input signal;
and the analog circuit module is used for adjusting the current input signal according to the voltage pulse signal corresponding to the current input signal to obtain a recovery data signal matched with the voltage signal sent by the main equipment.
According to another aspect of the present invention, there is provided a vehicle including:
an Ethernet chip, at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the phase detection method according to any of the embodiments of the present invention.
According to the technical scheme of the embodiment of the invention, a target weight coefficient corresponding to a current decision value of a current input signal is obtained according to a mapping relation between a pre-established weight coefficient and a decision value range; calculating a current weighted decision value under the current clock cycle according to the target weight coefficient and the current decision value, and generating a current error value under the current clock cycle according to the current weighted decision value; and finally, calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock cycle and the delay error value.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a phase detector provided in the prior art;
fig. 2 is a flowchart of a phase detection method according to an embodiment of the present invention;
fig. 3 is a flowchart of a phase detection method according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a phase detector according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an alternative phase detector according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of a clock recovery module according to a fourth embodiment of the present invention;
fig. 7 is a schematic structural diagram of an ethernet port physical layer PHY chip according to a fifth embodiment of the present invention;
fig. 8 is a schematic structural diagram of a vehicle implementing the phase detection method of the embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," "third," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In order to ensure the phase accuracy of an input signal sampled from a vehicle, a digital phase detector is generally used in the prior art to perform operation processing on sampled data to obtain a phase result of the input signal. Fig. 1 is a schematic structural diagram of a phase detector in the prior art. The working principle of the digital phase discriminator is as follows: firstly, judging sampling data to generate a judgment value; and after obtaining the decision value, subtracting the decision value from the sampling data to obtain an error value, delaying the error value and the decision value by one clock cycle to obtain a delay decision value and a delay error value, and finally outputting = decision value x delay error value-delay decision value x error value of the digital phase discriminator.
However, when the master device adopts the multilevel pulse amplitude modulation system, since the levels and the phases corresponding to the error values generated by different levels are not linearly related, if the digital phase detector in the prior art is used to calculate the phase difference of the input signal generated by the multilevel pulse amplitude modulation system, there will be a large difference from the actual phase difference.
Therefore, in order to solve the problem of low accuracy of calculating the phase deviation corresponding to the input signal, the embodiment of the invention provides a phase discrimination method, so that the phase deviation corresponding to the input signal is accurately calculated, and the accuracy of the input signal is improved.
Example one
Fig. 2 is a flowchart of a phase detection method according to an embodiment of the present invention, where the present embodiment is applicable to a case where a phase deviation corresponding to an input signal is accurately calculated, and the method may be implemented by a phase detector, which may be implemented in a hardware and/or software manner, and the phase detector may be configured in a vehicle. As shown in fig. 2, the method includes:
s110, acquiring a target weight coefficient corresponding to the current decision value of the current input signal according to a mapping relation between the pre-established weight coefficient and the decision value range.
The input signal may refer to an analog electrical signal obtained by a/D sampling. Each input signal is usually signed fixed point data which is generally expressed by binary complement codes and has m + n bits in total; m bits on the left side of the data are integer bits, including a sign bit; the remaining n bits are decimal bits. The current input signal may refer to an input signal acquired at a current clock cycle. The decision value may refer to a corresponding decision threshold obtained after the input signal is subjected to a preset decision condition. The current decision value may refer to a decision threshold corresponding to the current input signal.
The pre-established weight coefficient may refer to a weight value pre-set according to the magnitude between the decision values. Generally, the larger the amplitude of the decision value is, the larger the corresponding weight coefficient is; conversely, the smaller the amplitude of the decision value is, the smaller the corresponding weight coefficient is. The mapping relationship may refer to a correspondence relationship between each decision value and the weight coefficient. The target weight coefficient may refer to a weight coefficient corresponding to the current decision value.
In an optional implementation manner, before obtaining a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relationship between a pre-established weight coefficient and a decision value range, the method may further include: and judging the current input signal acquired under the current clock period according to preset judgment conditions to generate a current judgment value under the current clock period. The preset decision condition may refer to a preset condition for performing numerical determination on the current input signal, and may be, for example, a decision threshold divided according to a numerical range of each current input signal; or may be a decision threshold divided according to the level type of the level pulse amplitude modulation system employed by the master device. The embodiments of the present invention are not limited in this regard. Therefore, the corresponding current decision value can be matched for each current input signal, and an effective basis can be provided for subsequent operation.
And S120, calculating a current weighted decision value in the current clock cycle according to the target weight coefficient and the current decision value, and generating a current error value in the current clock cycle according to the current weighted decision value.
The weighted decision value may refer to a calculation value obtained after performing weighted calculation on the decision value. The current weighted decision value may refer to a calculation value obtained after the current decision value and the target weight coefficient are weighted.
Wherein the error value may refer to a deviation between the decision value and the input signal. The current error value may refer to a deviation between the current decision value and the current input signal.
And S130, calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock cycle and the delay error value.
The delay weighted decision value may refer to a weighted decision value of a previous clock cycle corresponding to the input signal. The delay error value may refer to an error value of a last clock cycle corresponding to the input signal. The phase deviation may refer to a phase difference that may exist between the current input signal and the real input signal, and may be generally embodied in the form of a voltage signal.
According to the technical scheme of the embodiment of the invention, a target weight coefficient corresponding to a current decision value of a current input signal is obtained according to a mapping relation between a pre-established weight coefficient and a decision value range; calculating a current weighted decision value under the current clock cycle according to the target weight coefficient and the current decision value, and generating a current error value under the current clock cycle according to the current weighted decision value; and finally, calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock cycle and the delay error value.
Example two
Fig. 3 is a flowchart of a phase detection method according to a second embodiment of the present invention, where the present embodiment is refined based on the above-mentioned embodiment, and in the present embodiment, the refining is specifically performed on an operation of calculating a current weighted decision value in a current clock cycle according to a target weight coefficient and a current decision value, and specifically may include: performing product calculation on the target weight coefficient and the current decision value to obtain a current weighted decision value in the current clock cycle; and, the operation of generating the current error value in the current clock cycle according to the current weighted decision value is refined, which may specifically include: and calculating the difference between the current decision value and the current input signal to obtain the current error value in the current clock period.
As shown in fig. 3, the method includes:
s210, judging the current input signal acquired in the current clock cycle according to preset judgment conditions, and generating a current judgment value in the current clock cycle.
Specifically, a current input signal in a current clock cycle is obtained, and a decision value corresponding to the current input signal is divided according to a preset decision condition, so as to obtain a current decision value corresponding to the current clock cycle.
S220, acquiring a target weight coefficient corresponding to the current decision value of the current input signal according to a mapping relation between the pre-established weight coefficient and the decision value range.
Specifically, after the current decision value is obtained, the weight coefficient matching the current decision value is found out as the target weight coefficient in the weight coefficient mapping relationship established in advance.
And S230, performing product calculation on the target weight coefficient and the current decision value to obtain the current weighted decision value in the current clock cycle.
Specifically, after the target weight coefficient is obtained, the product operation may be performed on the current decision value and the target weight coefficient to obtain the current weighted decision value, so that the magnitude of the influence of different decision levels on the phase of the input signal may be fully reflected.
S240, calculating a difference value between the current decision value and the current input signal to obtain a current error value in the current clock cycle.
Specifically, after the current decision value is obtained, a difference between the current input signal and the current decision value is calculated as a current error value.
And S250, performing product operation on the current weighted decision value and the delay error value to obtain a first product result.
Wherein the first product result may refer to a product result of the current weighted decision value and the delay error value.
And S260, performing product operation on the delay weighted decision value and the current error value to obtain a second product result.
Wherein the second product result may refer to a product result of the delayed weighted decision value and the current error value.
And S270, calculating the difference value of the first product result and the second product result to obtain the phase deviation corresponding to the current input signal.
Specifically, after the first multiplication result and the second multiplication result are calculated, in the embodiment of the present invention, a difference between the first multiplication result and the second multiplication result may be used as the phase offset corresponding to the current input signal.
According to the technical scheme of the embodiment of the invention, the current input signal acquired in the current clock cycle is judged through the preset judgment condition, and the current judgment value in the current clock cycle is generated; acquiring a target weight coefficient corresponding to a current decision value of the current input signal according to a mapping relation between a pre-established weight coefficient and a decision value range; then, the target weight coefficient and the current decision value are subjected to product calculation to obtain a current weighted decision value in the current clock period; calculating the difference between the current decision value and the current input signal to obtain the current error value in the current clock period; performing product operation on the current weighting judgment value and the delay error value to obtain a first product result; performing product operation on the delay weighted decision value and the current error value to obtain a second product result; and finally, performing difference calculation on the first product result and the second product result to obtain a phase deviation corresponding to the current input signal, wherein the current decision value is matched with the weight coefficient corresponding to the current input signal, and the current error value of the current input signal can be accurately calculated according to the weight coefficient, so that the problem of low calculation accuracy of the current error value caused by only depending on the current decision value is solved, the problem of low calculation accuracy of the phase deviation corresponding to the input signal is solved, the phase deviation corresponding to the input signal is accurately calculated, and the accuracy of the input signal is improved.
In an alternative embodiment, for example, where the host vehicle uses a 5-level pulse amplitude modulation system, the 5-level is-2, -1, 0, +1, +2. The A/D converter outputs a current input signal per clock, the current input signal is a 6-bit binary fixed-point signed number, the left 3 bits are integers including the leftmost 1-bit sign bit, and the right 3 bits are decimals. Each current input signal constitutes a sequence of input signals. For example, the sampling values are 7, and binary representation of the input signal sequence is {6' b010111,6' b001011,6' b111110,6' b101101,6' b001101,6' b011011,6' b110100}. All values other than the input signal sequence were 6' b000000. The input signal sequence is converted into a 10-ary representation as: {+2.875,+1.375, -0.25, -2.625,+1.625,+3.375, -1.5}. The phase discrimination method specifically can be as follows:
first, each current input signal in the input signal sequence is decided. For example, the decision threshold may be divided according to the value range of each current input signal, and the division may be used as a preset decision condition. Specifically, the preset determination condition may be: if the current input signal is greater than or equal to 1.5, setting the current decision value to be +2; if the current input signal is greater than or equal to 0.5 and less than 1.5, setting the current decision value to be +1; if the current input signal is greater than or equal to-0.5 and less than 0.5, setting the current decision value to 0; if the current input signal is greater than or equal to-1.5 and less than-0.5, setting the current decision value to-1; if the current input signal is less than-1.5, the current decision value is set to-2. By determining the input sequence converted into the 10-ary system according to the preset determination condition, the obtained current determination value sequence may be: {+2,+1,0, -2,+2,+2, -1}.
Further, after obtaining the current decision value sequence, performing difference calculation on the current input signal in the input sequence and the current decision value in the current decision value sequence one by one to obtain a corresponding current error value sequence: {+0.875,+0.375, -0.25, -0.625, -0.375,+1.375, -0.5}.
Further, the mapping relationship between the pre-established weight coefficient and the decision value range, for example, when the current decision value is +2, the corresponding target weight coefficient is set to 0.6; when the current decision value is +1, the corresponding target weight coefficient is set to 1.0; when the current decision value is 0, the corresponding target weight coefficient is set to 1.0; when the current judgment value is-1, the corresponding target weight coefficient is set to be 1.1; when the current decision value is-2, the corresponding target weight coefficient is set to 0.5. Then, the target weight coefficient sequence composed of the target weight coefficients corresponding to the current errors in the current error value sequence may be: {0.6,1.0,1.0,0.5,0.6,0.6,1.1}.
Further, the target weight coefficients in the target weight coefficient sequence and the current decision values in the current decision value sequence are multiplied one by one to obtain a current weighted decision value sequence consisting of the current weighted decision values: {1.2,1.0,0, -1.0,1.2,1.2, -1.1}.
Further, a delay weighting decision value of a clock cycle before the current weighting decision value is obtained, and it is noted that, if the current weighting decision value before the first current weighting decision value is 0, a delay weighting decision value sequence formed by each delay weighting decision value may be: {0,1.2,1.0,0, -1.0,1.2,1.2}. Similarly, the delay error value of the previous clock cycle of the current error value is obtained, and the delay error value sequence formed by the delay error values may be: {0,+0.875,+0.375, -0.25, -0.625, -0.375,+1.375}.
Finally, according to the formula: output result = current weighted decision value-delayed weighted decision value-current error value, resulting in an output result sequence corresponding to the input signal sequence: {0,0.425,0.25,0.25, -1.125, -2.1, -0.9125}. Thereby, a phase deviation corresponding to the current input signal can be obtained.
EXAMPLE III
Fig. 4 is a schematic structural diagram of a phase detector according to a third embodiment of the present invention. As shown in fig. 4, the phase detector includes: a table look-up circuit 310, a current weighted decision value calculation circuit 320, a current error value calculation circuit 330 and a phase error calculation circuit 340;
the table look-up circuit 310 is configured to obtain a target weight coefficient corresponding to a current decision value according to a mapping relationship between a pre-established weight coefficient and a decision value range;
a current weighted decision value calculating circuit 320, configured to calculate a current weighted decision value in a current clock cycle according to the target weight coefficient and the current decision value;
a current error value calculation circuit 330, configured to calculate a current error value in a current clock cycle according to the current decision value and the current input signal;
the phase error calculation circuit 340 is configured to calculate a phase deviation corresponding to the current input signal according to the current weighted decision value, the current error value, the delay weighted decision value in the previous clock cycle, and the delay error value.
According to the technical scheme of the embodiment of the invention, the table look-up circuit 310 is used for acquiring a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relation between the pre-established weight coefficient and a decision value range; the current weighted decision value calculating circuit 320 is configured to calculate a current weighted decision value in a current clock cycle according to the target weight coefficient and the current decision value; the current error value calculating circuit 330 is configured to generate a current error value in a current clock cycle according to the current weighted decision value; finally, the phase error calculation circuit 340 is used for calculating the phase deviation corresponding to the current input signal according to the current weighting decision value, the current error value, the delay weighting decision value in the previous clock cycle and the delay error value.
Optionally, the table look-up circuit 310 is specifically a memory with a pre-established mapping relationship between the weight coefficient and the decision value range;
and the memory is used for carrying out address mapping according to the input current decision value, acquiring a target mapping address matched with the current decision value, and acquiring and outputting a target weight coefficient from the target mapping address.
In the embodiment of the present invention, the target mapping address may refer to a storage address where a target weight coefficient matched with the current decision value is located.
Optionally, the current weighted decision value calculating circuit 320 is specifically a first multiplier, and the current error value calculating circuit 330 is specifically a first subtractor;
the first multiplier is used for performing product calculation on the target weight coefficient and the current decision value to obtain a current weighted decision value in the current clock cycle;
and the first subtracter is used for calculating the difference between the current decision value and the current input signal to obtain the current error value in the current clock period.
Optionally, the phase error calculation circuit 340 may specifically include:
the first delayer is used for acquiring a delay weighted decision value in the previous clock cycle;
the second delayer is used for obtaining a delay error value in the previous clock cycle;
the second multiplier is used for carrying out product operation on the current weighting judgment value and the delay error value to obtain a first product result;
the third multiplier is used for carrying out product operation on the delay weighted decision value and the current error value to obtain a second product result;
and the second subtracter is used for calculating the difference value of the first product result and the second product result to obtain the phase deviation corresponding to the current input signal.
Optionally, the phase detector may further include: and the decision circuit is used for deciding the current input signal acquired in the current clock cycle according to the preset decision condition and generating a current decision value in the current clock cycle.
The phase detector provided by the embodiment of the invention can execute the phase detection method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Fig. 5 is a schematic structural diagram of an alternative phase detector according to an embodiment of the present invention. Specifically, the decision circuit is connected with the table look-up circuit and a first multiplier, the first multiplier is connected with a first delayer and a second multiplier, and the first delayer is connected with a third multiplier; the current error value calculation circuit is connected with the second delayer and the third multiplier; the second multiplier and the third multiplier are connected with the subtracter, and the phase deviation corresponding to the current input signal is output.
Example four
Fig. 6 is a schematic structural diagram of a clock recovery module according to a fourth embodiment of the present invention. As shown in fig. 6, the clock recovery module includes: phase detector 410, loop filter 420, loop amplifier 430, and voltage controlled oscillator 440; the phase detector 410 is connected with the loop filter 420, the loop filter 420 is connected with the loop amplifier 430, the loop amplifier 430 is connected with the voltage-controlled oscillator 440, and the voltage-controlled oscillator 440 is connected with the phase detector 410;
the phase discriminator 410 is configured to calculate a phase deviation corresponding to a current input signal, and obtain an error voltage including the phase deviation;
the loop filter 420 is configured to filter a high-frequency component in the error voltage to obtain a control voltage;
a loop amplifier 430 for enhancing the control voltage to obtain a voltage pulse signal;
the voltage controlled oscillator 440 is used for generating an output voltage signal according to the voltage pulse signal.
In this embodiment, the error voltage may refer to a voltage corresponding to the current input signal, including a phase deviation. The control voltage may refer to a voltage for power control of the voltage controlled oscillator 440. The voltage pulse signal may refer to a control voltage after voltage amplification. The output voltage signal may refer to a phase error voltage generated by comparing the voltage pulse signal with a phase error of the current input signal such that the frequency of the voltage controlled oscillator 440 is identical to the current input signal rate.
It is noted that the voltage controlled oscillator 440 is done in the non-digital portion and the phase detector 410, the loop filter 420, and the loop amplifier 430 are done in the digital portion. Usually, the recovery of the current input signal needs to be realized according to the voltage pulse signal obtained by the digital part.
EXAMPLE five
Fig. 7 is a schematic structural diagram of a Port Physical Layer (PHY) chip according to a fifth embodiment of the present invention. As shown in fig. 7, the ethernet PHY chip includes:
the clock recovery module 510 is configured to determine a current input signal acquired in a current clock cycle, so as to obtain a voltage pulse signal corresponding to the current input signal;
the analog circuit module 520 is configured to adjust the current input signal according to the voltage pulse signal corresponding to the current input signal, and obtain a recovered data signal matched with the voltage signal sent by the master device.
In an embodiment of the present invention, the recovered data signal may refer to an input signal after the potential difference adjustment. Therefore, the phase difference adjustment of the input signals can be realized, and the accuracy of the input signals is ensured.
EXAMPLE six
Fig. 8 is a schematic structural diagram of a vehicle according to an embodiment of the present invention, as shown in fig. 8, the vehicle includes an ethernet chip 650, a processor 610, a memory 620, an input device 630, and an output device 640; the number of processors 610 in the vehicle may be one or more, and one processor 610 is taken as an example in fig. 8; the processor 610, the memory 620, the input device 630, the output device 640, and the ethernet chip 650 in the vehicle may be connected by a bus or other means, and the bus connection is exemplified in fig. 8. The ethernet chip 650 may be an ethernet PHY chip.
The memory 620 is used as a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the phase detection method in the embodiments of the present invention (e.g., the decision circuit 310, the look-up table circuit 320, the current weighted decision value calculation circuit 330, the current error value calculation circuit 340, and the phase error calculation circuit 350 in the phase detector). The processor 610 executes software programs, instructions and modules stored in the memory 620 to perform various functional applications and data processing of the vehicle, i.e., to implement the phase detection method described above.
The memory 620 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 620 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 620 may further include memory located remotely from the processor 610, which may be connected to the vehicle over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 630 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the vehicle. The output device 640 may include a display device such as a display screen.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A phase discrimination method, comprising:
acquiring a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relation between a pre-established weight coefficient and a decision value range;
calculating a current weighted decision value under the current clock cycle according to the target weight coefficient and the current decision value, and generating a current error value under the current clock cycle according to the current weighted decision value;
and calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock period and the delay error value.
2. The method of claim 1, wherein calculating a current weighted decision value at a current clock cycle based on the target weight coefficient and the current decision value comprises:
performing product calculation on the target weight coefficient and the current decision value to obtain a current weighted decision value in the current clock period;
generating a current error value in a current clock cycle according to the current weighted decision value, including:
and performing difference calculation on the current decision value and the current input signal to obtain a current error value in the current clock period.
3. The method of claim 1, wherein calculating a phase offset corresponding to the current input signal based on the current weighted decision value, the current error value, the delayed weighted decision value in the previous clock cycle, and the delayed error value comprises:
performing product operation on the current weighting judgment value and the delay error value to obtain a first product result;
performing product operation on the delay weighted decision value and the current error value to obtain a second product result;
and calculating the difference value of the first product result and the second product result to obtain the phase deviation corresponding to the current input signal.
4. The method of claim 1, further comprising, before the obtaining a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relationship between a pre-established weight coefficient and a decision value range, the method further comprising:
and judging the current input signal acquired in the current clock period according to preset judgment conditions to generate a current judgment value in the current clock period.
5. A phase detector, comprising:
the table look-up circuit is used for acquiring a target weight coefficient corresponding to a current decision value of a current input signal according to a mapping relation between a pre-established weight coefficient and a decision value range;
the current weighted decision value calculating circuit is used for calculating a current weighted decision value in the current clock period according to the target weight coefficient and the current decision value;
a current error value calculation circuit for generating a current error value in a current clock cycle according to the current weighted decision value;
and the phase error calculation circuit is used for calculating the phase deviation corresponding to the current input signal according to the current weighting judgment value, the current error value, the delay weighting judgment value in the previous clock cycle and the delay error value.
6. A phase detector as claimed in claim 5, characterized in that said look-up table circuit is embodied as a memory having a pre-established mapping relationship between weight coefficients and decision value ranges built therein;
and the memory is used for carrying out address mapping according to the input current judgment value, acquiring a target mapping address matched with the current judgment value, and acquiring and outputting a target weight coefficient from the target mapping address.
7. The phase detector of claim 5, wherein the current weighted decision value calculation circuit is specifically a first multiplier, and the current error value calculation circuit is specifically a first subtractor;
the first multiplier is used for performing product calculation on the target weight coefficient and the current decision value to obtain the current weight decision value in the current clock cycle;
and the first subtracter is used for calculating the difference between the current decision value and the current input signal to obtain the current error value in the current clock period.
8. The phase detector of claim 5, wherein the phase error calculation circuit specifically comprises:
the first delayer is used for acquiring a delay weighted decision value in the previous clock cycle;
the second delayer is used for obtaining a delay error value in the previous clock cycle;
the second multiplier is used for carrying out product operation on the current weighting judgment value and the delay error value to obtain a first product result;
the third multiplier is used for carrying out product operation on the delay weighted decision value and the current error value to obtain a second product result;
and the second subtracter is used for calculating the difference value of the first multiplication result and the second multiplication result to obtain the phase deviation corresponding to the current input signal.
9. A clock recovery module, comprising: the phase detector, the loop filter, the loop amplifier and the voltage-controlled oscillator; the phase discriminator is connected with the loop filter, the loop filter is connected with the loop amplifier, the loop amplifier is connected with the voltage-controlled oscillator, and the voltage-controlled oscillator is connected with the phase discriminator;
the phase discriminator is used for calculating the phase deviation corresponding to the current input signal to obtain the error voltage containing the phase deviation;
the loop filter is used for filtering high-frequency components in the error voltage to obtain a control voltage;
the loop amplifier is used for enhancing the control voltage to obtain a voltage pulse signal;
and the voltage-controlled oscillator is used for generating an output voltage signal according to the voltage pulse signal.
10. An ethernet port physical layer PHY chip, comprising:
the clock recovery module is used for judging a current input signal acquired in a current clock period to obtain a voltage pulse signal corresponding to the current input signal;
and the analog circuit module is used for adjusting the current input signal according to the voltage pulse signal corresponding to the current input signal to obtain a recovery data signal matched with the voltage signal sent by the main equipment.
11. A vehicle, characterized by comprising:
an Ethernet chip, at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the phase detection method of any of claims 1-4.
CN202211309902.4A 2022-10-25 2022-10-25 Phase discrimination method, phase discriminator, clock recovery module, ethernet chip and vehicle Pending CN115632653A (en)

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