CN117255141A

CN117255141A - Method, device, equipment and storage medium for recovering oversampled data

Info

Publication number: CN117255141A
Application number: CN202311130392.9A
Authority: CN
Inventors: 刘育才
Original assignee: Shanghai Anlu Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co ltd
Priority date: 2023-09-04
Filing date: 2023-09-04
Publication date: 2023-12-19

Abstract

The invention discloses a method, a device, equipment and a storage medium for recovering oversampling data, which are characterized in that serial data are converted into the oversampling data, the oversampling data are subjected to delay processing to obtain first delay oversampling data, and the first delay oversampling data and the oversampling data are spliced to obtain first oversampling spliced data; sliding comparison is carried out on the first oversampling spliced data and the first binary string sequence data to obtain jump edge information of the oversampling data, and mapping processing is carried out on the jump edge information to obtain jump edge positions; inputting the jump edge position into an edge information shaping circuit for shaping treatment to obtain an edge position; according to the edge position, calculating the sampling position of the over-sampling data, and carrying out sampling processing on the over-sampling data based on the sampling position to obtain effective sampling data; inputting the effective sampling data into a bit width conversion circuit, and outputting fixed bit width effective data; compared with the prior art, the technical scheme of the invention can improve the accuracy of oversampling data recovery.

Description

Method, device, equipment and storage medium for recovering oversampled data

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for recovering oversampled data.

Background

In some protocols, although the line rate is within the working range of SERDES, the data is burst type and there is a strict requirement for data recovery time, such as GPON protocol (1.244 Gbps, etc.), while CDR circuit locking inside SERDES requires a certain time, which is often difficult to meet, so that the data can be recovered quickly using an oversampling circuit in FPGA.

In burst data mode, if the SERDES sampling clock is stable and not homologous to the serial data, the edge position and sampling position will change incrementally or decrementally when there is data, and when there is data from 0, the sampling position will also remain unchanged at the end of the last data, but the edge position has changed by multiple values, so the first few cycles of data may be sampled incorrectly; likewise, when the sampling clock is unstable, the change direction of the edge position is irregular, and the requirements on the data recovery module are more strict; some protocols (GPON) require locking data within a limited preamble length, so there is a strict requirement on the data recovery time of the oversampled data recovery logic in this case.

In the prior art, when the SERDES is used in a low-rate scene, a method for recovering original data from oversampled data is also generally adopted, but after the output parallel oversampled data is shifted by 1bit, the data edges are searched by adopting a two-to-two exclusive OR mode, and edge misjudgment is easily caused when a signal is poor or a sampling clock is dithered, so that the accuracy in the subsequent data recovery is lower.

Disclosure of Invention

The invention aims to solve the technical problems that: provided are a method, a device, equipment and a storage medium for recovering oversampled data, which improve the accuracy of the recovery of the oversampled data.

In order to solve the above technical problems, the present invention provides a method for recovering oversampled data, including:

converting the received serial data into oversampled data, carrying out delay processing on the oversampled data to obtain first delay oversampled data, and splicing the first delay oversampled data and the oversampled data to obtain first oversampled spliced data;

sliding comparison is carried out on the first oversampling spliced data and preset first binary string sequence data to obtain jump edge information of the oversampling data, and mapping processing is carried out on the jump edge information to obtain jump edge positions;

Inputting the jump edge position into an edge information shaping circuit so that the edge information shaping circuit carries out shaping treatment on the jump edge position to obtain an edge position;

according to the edge position, calculating a sampling position of the over-sampling data, and carrying out sampling processing on the over-sampling data based on the sampling position to obtain effective sampling data;

and inputting the valid sampling data into a bit width conversion circuit so that the bit width conversion circuit outputs fixed bit width valid data.

In one possible implementation manner, the sliding comparison is performed on the first oversampled spliced data and preset first binary string sequence data to obtain jump edge information of the oversampled data, which specifically includes:

acquiring the sequence length of preset first binary string sequence data, and selecting a plurality of data segments from the first oversampled spliced data according to a preset sequence based on the sequence length;

comparing each data segment with the first binary string sequence data respectively, if the data segment is the same as the first binary string sequence data, considering that a first data bit in the current data segment has a jump edge of the oversampling data, and assigning the first data bit to be 1, otherwise, considering that the first data bit in the current data segment does not have the jump edge of the oversampling data, and assigning the first data bit to be 0;

And assigning data to the first data bit corresponding to each data segment to obtain jump edge information of the oversampling data.

In one possible implementation manner, mapping the jump edge information to obtain a jump edge position specifically includes:

performing granularity division processing on the jump edge information so as to divide the jump edge information into a plurality of jump edge granularity segments;

comparing each jump edge granularity section with a plurality of preset second binary string sequence data respectively, and determining the phase position of the jump edge in each jump edge granularity section according to a comparison result;

and integrating all the phase positions to obtain the jump edge position of the oversampled data.

In one possible implementation, before the jump edge position is input to the edge information shaping circuit, the method further includes:

and extracting a jump edge position section from the jump edge position, comparing the jump edge position section with a plurality of pieces of third binary string sequence data respectively, if the third binary string sequence data which are the same as the jump edge position section exist, carrying out delay processing on the jump edge position to obtain a first delay jump edge position, and updating the first delay jump edge position into a current jump edge position.

In one possible implementation manner, the jump edge position is input into an edge information shaping circuit, so that the edge information shaping circuit performs shaping processing on the jump edge position to obtain an edge position, and the method specifically includes:

inputting the jump edge position into an edge information shaping circuit, so that the edge information shaping circuit delays the jump edge position to obtain a second delay jump edge position, and delays the second delay jump edge position to obtain a third delay jump edge position;

adding 1 to the second delay jump edge position and the third delay jump edge position respectively to obtain a second adding delay jump edge position and a third adding delay jump edge position;

and if the second and one delay jump edge positions are the same as the third delay jump edge positions, or the third and one delay jump edge positions are the same as the second delay jump edge positions, the jump edge is considered to swing in an invalid way, and the jump edge positions are taken as edge positions.

In one possible implementation manner, calculating the sampling position of the oversampled data according to the edge position specifically includes:

Setting a preset phase offset value, acquiring a current sampling position, subtracting the current sampling position from the edge position, and adding the phase offset value to obtain a sampling phase offset value;

and judging whether the sampling phase offset value is 0, if so, directly taking the current sampling position as a sampling position, otherwise, adjusting the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampling data.

In one possible implementation manner, the adjusting the current sampling position according to the sampling phase offset value specifically includes:

setting a first sampling phase shift threshold, a second sampling phase shift threshold and a third sampling phase shift threshold;

when the sampling phase offset value is not smaller than the first sampling phase offset threshold value, subtracting 1 from the current sampling position to obtain a first adjustment position, and updating the first adjustment position to the current sampling position;

when the sampling phase offset value is not smaller than the second sampling phase offset threshold value and smaller than the first sampling phase offset threshold value, subtracting 2 from the current sampling position to obtain a second adjustment position, and updating the second adjustment position to the current sampling position;

When the sampling phase offset value is determined to be larger than the third sampling phase offset threshold and smaller than the second sampling phase offset threshold, adding 2 to the current sampling position to obtain a third adjustment position, and updating the third adjustment position to the current sampling position;

and when the sampling phase offset value is not larger than the third sampling phase offset threshold value, adding 1 to the current sampling position to obtain a fourth adjustment position, and updating the fourth adjustment position to the current sampling position.

In one possible implementation manner, the sampling processing is performed on the oversampled data based on the sampling position to obtain valid sampling data, which specifically includes:

delay processing is carried out on the oversampling data to obtain second delay oversampling data, third delay oversampling data and fourth delay oversampling data;

extracting first sampling data from the second delay oversampling data, extracting second sampling data from the fourth delay oversampling data, and splicing the first sampling data, the third sampling data and the third delay oversampling data to obtain second oversampling spliced data;

Performing delay processing on the sampling position to obtain a current sampling position and an upper clock period sampling position;

when the current sampling position is determined to be at a preset first range position, extracting a plurality of groups of first effective data sets from the second oversampling spliced data according to the current sampling position, adding all effective data in each group of first effective data sets to obtain a plurality of groups of first effective data sums, if the first effective data sums are larger than preset effective data and a threshold value, determining that the first effective data obtained by sampling in the first effective data and the corresponding effective data sets is 1, otherwise, determining that the first effective data obtained by sampling in the first effective data and the corresponding first effective data sets is 0, and integrating the first effective data corresponding to all the first effective data sets to obtain first effective sampling data;

when the sampling position of the upper clock period is determined to be at a preset first target position and the current sampling position is 0, extracting a plurality of groups of second effective data sets from the second oversampling spliced data according to the sampling position of the upper clock period, adding all effective data in each group of second effective data sets to obtain a plurality of groups of second effective data sums, if the sum of the second effective data is greater than a preset effective data and a threshold value, determining that the second effective data obtained by sampling in the second effective data and the corresponding effective data sets is 1, otherwise, determining that the second effective data obtained by sampling in the second effective data and the corresponding second effective data sets is 0, and integrating the second sampling data and the second effective data corresponding to all the second effective data sets to obtain second effective sampling data;

When the upper clock period sampling position is determined to be at a preset second target position and the current sampling position is 1, extracting a plurality of groups of third effective data sets from the second oversampling spliced data according to the upper clock period sampling position, wherein the difference between the number of the third effective data sets and the number of the second effective data sets is 1;

and adding all the effective data in each group of third effective data sets to obtain a plurality of groups of third effective data sums, if the third effective data sums are larger than preset effective data and a threshold value, determining that the third effective data obtained by sampling in the third effective data sets and the corresponding effective data sets is 1, otherwise, determining that the third effective data obtained by sampling in the third effective data sets and the corresponding effective data sets is 0, and integrating the second effective data corresponding to all the third effective data sets to obtain third effective sampling data.

In one possible implementation manner, the valid sampling data is input into a bit width conversion circuit, so that the bit width conversion circuit outputs fixed bit width valid data, and specifically includes:

setting a shift register;

acquiring the effective data length of the effective data, inputting the effective data into the shift register, moving out the effective data length data from the shift register, and updating the shift register;

Setting a counter, recording the effective data quantity in the shift register based on the counter, and extracting and outputting the effective data with the fixed bit width from the shift register based on the data bit corresponding to the effective data quantity when the effective data quantity is not smaller than the preset fixed bit width.

The invention also provides a device for recovering the oversampled data, which comprises: the device comprises a sampling data splicing module, a sampling data sliding comparison module, an edge information shaping module, a sampling position calculation module and a fixed bit width effective data output module;

the sampling data splicing module is used for converting received serial data into oversampling data, carrying out delay processing on the oversampling data to obtain first delay oversampling data, and splicing the first delay oversampling data and the oversampling data to obtain first oversampling splicing data;

the sampling data sliding comparison module is used for carrying out sliding comparison on the first oversampling spliced data and preset first binary string sequence data to obtain jump edge information of the oversampling data, and carrying out mapping processing on the jump edge information to obtain jump edge positions;

The edge information shaping module is used for inputting the jump edge position into the edge information shaping circuit so that the edge information shaping circuit carries out shaping treatment on the jump edge position to obtain an edge position;

the sampling position calculation module is used for calculating the sampling position of the over-sampling data according to the edge position, and carrying out sampling processing on the over-sampling data based on the sampling position to obtain effective sampling data;

the fixed bit width valid data output module is used for inputting the valid sampling data into the bit width conversion circuit so that the bit width conversion circuit outputs the fixed bit width valid data.

In a possible implementation manner, the sliding comparison module for sampling data is configured to perform sliding comparison on the first oversampled spliced data and preset first binary string sequence data to obtain jump edge information of the oversampled data, and specifically includes:

In a possible implementation manner, the sample data sliding comparison module is configured to map the jump edge information to obtain a jump edge position, and specifically includes:

In one possible implementation manner, the edge information shaping module is configured to, before inputting the jump edge position to the edge information shaping circuit, further include:

In one possible implementation manner, the edge information shaping module is configured to input the jump edge position into an edge information shaping circuit, so that the edge information shaping circuit performs shaping processing on the jump edge position to obtain an edge position, and specifically includes:

In one possible implementation manner, the sampling position calculating module is configured to calculate, according to the edge position, a sampling position of the oversampled data, and specifically includes:

In one possible implementation manner, the sampling position calculating module is configured to adjust the current sampling position according to the sampling phase offset value, and specifically includes:

In one possible implementation manner, the sampling position calculating module is configured to perform sampling processing on the oversampled data based on the sampling position to obtain valid sampling data, and specifically includes:

In one possible implementation manner, the fixed bit width valid data output module is configured to input the valid sampling data into a bit width conversion circuit, so that the bit width conversion circuit outputs fixed bit width valid data, and specifically includes:

Setting a shift register;

The invention also provides a terminal device comprising a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the method for recovering oversampled data according to any one of the above when executing the computer program.

The invention also provides a computer readable storage medium comprising a stored computer program, wherein the computer program when run controls a device in which the computer readable storage medium is located to perform the method for recovering oversampled data according to any one of the above.

Compared with the prior art, the method, the device, the equipment and the storage medium for recovering the oversampled data have the following beneficial effects:

the method comprises the steps of converting received serial data into oversampling data, carrying out delay processing on the oversampling data to obtain first delay oversampling data, and splicing the first delay oversampling data with the oversampling data to obtain first oversampling spliced data; sliding comparison is carried out on the first oversampling spliced data and the first binary string sequence data to obtain jump edge information of the oversampling data, and mapping processing is carried out on the jump edge information to obtain jump edge positions; inputting the jump edge position into an edge information shaping circuit for shaping treatment to obtain an edge position; according to the edge position, calculating the sampling position of the over-sampling data, and carrying out sampling processing on the over-sampling data based on the sampling position to obtain effective sampling data; inputting the effective sampling data into a bit width conversion circuit, and outputting fixed bit width effective data; compared with the prior art, the technical scheme of the invention splices the first delay oversampling data with the oversampling data to obtain the first oversampling spliced data, and compares the first oversampling spliced data with the first binary string sequence data in a sliding manner to obtain jump edge information, so that irregular jump of the data jump edge and misjudgment of data jitter in the middle of the oversampling data can be effectively filtered, and the accuracy of subsequent oversampling data recovery is improved.

Drawings

FIG. 1 is a flow chart of an embodiment of a method for recovering oversampled data in accordance with the present invention;

fig. 2 is a schematic structural diagram of an embodiment of an apparatus for recovering oversampled data according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Embodiment 1, referring to fig. 1, fig. 1 is a flow chart of an embodiment of a method for recovering oversampled data provided in the present invention, as shown in fig. 1, the method includes steps 101 to 103, specifically as follows:

step 101: and converting the received serial data into oversampled data, carrying out delay processing on the oversampled data to obtain first delay oversampled data, and splicing the first delay oversampled data and the oversampled data to obtain first oversampled spliced data.

In one embodiment, the serial data is subjected to an oversampling process by using an oversampler, and the oversampler is preferably a high-speed SERDES circuit.

Specifically, the rate of the original serial data is 1.24416Gbps, the rate of the high-speed SERDES circuit is configured to be 9.95328Gbps and is 8 times of that of the serial data, so that each effective data is repeatedly sampled 8 times, a data interface to be sent to a user side is set to be 32 bits, the sampling clock is 4.97664GHz inside the high-speed SERDES circuit, and finally the parallel oversampled data data_in [31:0] and the synchronous clock clk thereof are output, and the format of the parallel oversampled data data_in [31:0] is AAAA_AAAA_BBBB_BBBBC_CCCC_DDDD_DDDD and A, B, C, D is 4 original serial data respectively.

In an embodiment, the over-sampled data is delayed to obtain first delayed over-sampled data, and the first delayed over-sampled data and the over-sampled data are spliced to obtain first over-sampled spliced data.

Specifically, the first delayed oversampling data data_din_1dly [31:0] is obtained by cycling the oversampling data data_in [31:0]1 clk, the data before and after delay are spliced to obtain the first oversampling spliced data data_tmp_1dly [63:0], wherein the first oversampling spliced data data_tmp_1dly= { the first delayed oversampling data data_din_1dly, and the oversampling data data_din }.

Step 102: and performing sliding comparison on the first oversampling spliced data and preset first binary string sequence data to obtain jump edge information of the oversampling data, and performing mapping processing on the jump edge information to obtain jump edge positions.

Specifically, a sequence length of preset first binary string sequence data is obtained, and a plurality of data segments are selected from the first oversampled spliced data according to a preset sequence based on the sequence length; comparing each data segment with the first binary string sequence data respectively, if the data segment is the same as the first binary string sequence data, considering that a first data bit in the current data segment has a jump edge of the oversampling data, and assigning the first data bit to be 1, otherwise, considering that the first data bit in the current data segment does not have the jump edge of the oversampling data, and assigning the first data bit to be 0; and assigning data to the first data bit corresponding to each data segment to obtain jump edge information of the oversampling data.

Preferably, the preset first binary string sequence data is 4' b0001, where 4 represents the sequence length of the first binary string, 0001 is the first binary string itself, and b indicates that this is a binary string.

As an example of sliding comparison between the first oversampled spliced data and the preset first binary string sequence data in this embodiment, whether the current bit position is a data jump edge is compared by sliding, if yes, the current bit position is recorded as 1, otherwise, the current bit position is recorded as 0. The comparison method is as follows:

1) The first data segment data_tmp_1dly [3:0] is obtained by taking 4 bits upwards from 0bit of the first delayed oversampled data data_tmp_1dly, the first data segment is compared with the first binary string sequence data 4' b0001, if the first data segment and the first binary string sequence data are equal, the bit0 position of the first data bit in the current data segment is considered to be a jump edge of original data, the data_edge_2dly [0] register is assigned to be 1, namely the first data bit is assigned to be 1, and otherwise, the first data bit is assigned to be 0.

2) The second data segment data_tmp_1dly [4:1] is obtained by taking 4 bits upwards from 1bit of the first delayed oversampled data data_tmp_1dly, the second data segment is compared with the first binary string sequence data 4' b0001, if the first data segment and the first binary string sequence data are equal, the bit1 position of the first data bit in the current data segment is considered to be a jump edge of original data, the data_edge_2dly [1] register is assigned to be 1, namely the first data bit is assigned to be 1, and otherwise, the first data bit is assigned to be 0.

3) And 4 bits are upwards fetched from 2 bits of the first delay oversampling data data_tmp_1dly to obtain a third data segment data_tmp_1dly [5:2], the third data segment is compared with the first binary string sequence data 4' b0001, if the first data segment and the first binary string sequence data are equal, the bit2 position of the first data bit in the current data segment is considered to be a jump edge of original data, the data_edge_2dly [2] register is assigned to be 1, namely the first data bit is assigned to be 1, and otherwise, the first data bit is assigned to be 0.

4) Similarly, the thirty-second data segment data_tmp_1dly is obtained by taking up 4 bits from 31 bits of the first delayed oversampled data data_tmp_1dly [34:31], the thirty-second data segment is compared with the first binary string sequence data 4' b0001, if the thirty-second data segment and the first binary string sequence data are equal, the first data bit31 position in the current data segment is considered to be a jump edge of the original data, and the result is recorded in a data_edge_2dly [31] register, so far, jump edge information in 32bit data of the current clock cycle is obtained.

In one embodiment, the parallel oversampled data A is delayed by 1 parallel clock cycle to obtain data A1. The A and the A1 are spliced to obtain parallel oversampling data with 2 times bit width, a jump edge is found in a sliding comparison mode of using sequence values and current data, irregular jump of the data jump edge can be effectively filtered, and false judgment probability of data jitter in the middle of the oversampling data is reduced; the situation that the data edges are found in a mode of exclusive OR of every two after parallel data output by a high-speed SERDES circuit are shifted by 1bit in the prior art is avoided, and edge misjudgment is easily caused when signals are poor or sampling clocks are dithered is avoided.

Specifically, granularity division processing is carried out on the jump edge information so that the jump edge information is divided into a plurality of jump edge granularity segments; comparing each jump edge granularity section with a plurality of preset second binary string sequence data respectively, and determining the phase position of the jump edge in each jump edge granularity section according to a comparison result; and integrating all the phase positions to obtain the jump edge position of the oversampled data.

Preferably, eight times of oversampling processing is performed on the data when oversampling is performed, so that when granularity division processing is performed on the jump edge information, the jump edge information data_edge_2dly [31:0] is segmented according to 8bit granularity, and four jump edge granularity segments are obtained, namely data_edge_2dly [7:0], data_edge_2dly [15:8], data_edge_2dly [23:16] and data_edge_2dly [31:24]; each bit in the granularity can be considered as a data phase, whether a jump edge exists in each granularity is judged respectively, and if the jump edge exists, the phase of the jump edge is determined.

Preferably, the predetermined plurality of second binary string sequence data are 8'b0000_0001, 8'b0000_0010, 8'b0000_0100, 8'b0000_1000, 8'b0001_000?, 8'b0010_00??, 8'b0100_0??? and 8'b1000_????; wherein, "?" means that the data of no interest is 0 or 1.

As an example of the jump edge position of the oversampled data in this embodiment, 1) the jump edge granularity segment data_edge_2dly [7:0] is compared with the second binary string sequence data 8' b0000_0001, and if equal, the jump edge is considered to be in the 0 th phase, and edge_offset_3dly [2:0] is assigned to 0.

2) The jump edge granularity data_edge_2dly [7:0] is compared with the second binary string sequence data 8' b0000_0010, if the jump edges are equal, the jump edge is considered to be in the 1 st phase, and the edge_offset_3dly [2:0] is assigned as 1.

3) The jump edge granularity segment data_edge_2dly [7:0] is compared with the second binary string sequence data 8'b0000_0100, if the jump edge granularity segment data_edge_2dly [7:0] is equal to the second binary string sequence data 8' b0000_0100, the jump edge is considered to be in the 2 nd phase, and the jump edge position edge_offset_3dly [2:0] is assigned to be 2.

4) The jump edge granularity segment data_edge_2dly [7:0] is compared with the second binary string sequence data 8' b0000_1000, if the jump edges are equal, the jump edges are considered to be in the 3 rd phase, and the jump edge position edge_offset_3dly [2:0] is assigned to be 3.

5) Will the transition be along the granularity segment data_edge_2dly [7:0] and the second binary string sequence data 8' b0001_000? If the two phases are equal, the jump edge is considered to be at the 4 th phase, and the jump edge position edge_offset_3dly [2:0] is assigned to be 4.

6) The jump edge granularity segment data_edge_2dly [7:0] is compared with the second binary string sequence data 8'b0010_00??, if the jump edge granularity segment data_edge_2dly [7:0] is equal to the second binary string sequence data 8' b0010_00, the jump edge is considered to be in the 5 th phase, and the jump edge position edge_offset_3dly [2:0] is assigned to be 5.

7) And comparing the jump edge granularity segment data_edge_2dly [7:0] with the second binary string sequence data 8'b0100_0???, if the jump edge granularity segment data_edge_2dly [7:0] and the second binary string sequence data 8' b0100_0 are equal, considering that the jump edge is in the 6 th phase, and assigning the jump edge position edge_offset_3dly [2:0] to be 6.

8) And comparing the jump edge granularity segment data_edge_2dly [7:0] with the second binary string sequence data 8 'b1000????_and if the jump edge granularity segment data_edge_2dly [7:0] and the second binary string sequence data 8' b1000_are equal, considering that the jump edge is in the 7 th phase, and assigning the jump edge position edge_offset_3dly [2:0] to be 7.

Similarly, the jump edge granularity segment data_edge_2dly [15:8], the jump edge granularity segment data_edge_2dly [23:16], and the jump edge granularity segment data_edge_2dly [31:24] are respectively compared according to the method, and jump edge positions edge_offset_3dly [5:3], jump edge positions edge_offset_3dly [8:6], and jump edge positions edge_offset_3dly [11:9] are respectively obtained.

In one embodiment, the edge position edge_offset_3dly [2:0], the edge position edge_offset_3dly [5:3], the edge position edge_offset_3dly [8:6], and the edge position edge_offset_3dly [11:9] are integrated to obtain the edge position edge_offset_3dly of the oversampled data.

Step 103: and inputting the jump edge position into an edge information shaping circuit so that the edge information shaping circuit carries out shaping treatment on the jump edge position to obtain an edge position.

In an embodiment, before the step of inputting the jump edge position to the edge information shaping circuit, the method further includes extracting a jump edge position segment from the jump edge position, comparing the jump edge position segment with a plurality of third binary string sequence data respectively, if the third binary string sequence data identical to the jump edge position segment exists, performing delay processing on the jump edge position to obtain a first delay jump edge position, and updating the first delay jump edge position to be a current jump edge position.

Preferably, the plurality of third binary string sequence data comprises 4'b0001, 4'b001?, 4'b01?? and 4'b1???

Preferably, the first 4 bit values in the jump edge position are extracted to obtain the jump edge position segment data_edge_3dly [3:0].

As an example of comparing the edge position segments with the plurality of third binary string sequence data, respectively, in this embodiment, if the edge position segment data_edge_3dly [3:0] is 4' b0001, the edge position edge_offset_3dly [2:0] is delayed by 1 clk period to be assigned to edge_offset_4dly.

If the jump is 4'b001? along the position segment data_edge_3dly [3:0 ]? The edge position edge_offset_3dly [5:3] is delayed by 1 clk period and assigned to the current edge position edge_offset_4dly.

If the edge position segment data_edge_3dly [3:0] is 4'b01??, the edge position edge_offset_3dly [8:6] is delayed by 1 clk period and assigned to the current edge position edge_offset_4dly.

If the edge position segment data_edge_3dly [3:0] is 4'b1???, the edge position edge_offset_3dly [11:9] is delayed by 1 clk period and assigned to the current edge position edge_offset_4dly.

If no bit in the transition edge position segment data_edge_3dly [3:0] is 1, the current transition edge position edge_offset_4dly is kept unchanged.

In an embodiment, after the jump edge position edge_offset_4dly contained in the oversampled data is obtained, but since some high-speed SERDES circuits do not use CDRs, the sampling clock cannot be completely locked to a fixed frequency point, i.e., the sampling clock can shake within a range, which is set to ±400ppm in this embodiment; therefore, the obtained data edge may repeatedly jump between 2 data, if the repeated jump of the edge just causes the sampling position to swing between the 0 th phase and the 7 th phase, the insertion or deletion of multi-bit data is easy to occur in a short time, and the subsequent data error code is caused. It is necessary to filter out such invalid edge transition information by an edge information shaping circuit.

In one embodiment, the jump edge position is input into an edge information shaping circuit, so that the edge information shaping circuit delays the jump edge position to obtain a second delay jump edge position; and carrying out delay processing on the second delay jump edge position to obtain a third delay jump edge position.

Preferably, the edge position edge_offset_4dly is delayed by 1 clk period to obtain a second delay edge position edge_offset_5dly, and the second delay edge position edge_offset_5dly is delayed by 1 clk period to obtain a third delay edge position edge_offset_6dly.

In one embodiment, whether the delay jump edge position swings is determined by comparing whether the delay jump edge position at the current moment is equal to the delay jump edge position at the last moment, and the edge position is determined based on the swinging result.

Specifically, adding 1 to the second delay jump edge position and the third delay jump edge position to obtain a second adding one delay jump edge position and a third adding one delay jump edge position; and if the second and one delay jump edge positions are the same as the third delay jump edge positions, or the third and one delay jump edge positions are the same as the second delay jump edge positions, the jump edge is considered to swing in an invalid way, and the jump edge positions are taken as edge positions.

Specifically, whether the third delay jump edge position is equal to the second delay jump edge position or not is judged, whether the second delay jump edge position is equal to the jump edge position or not is judged, if the third delay jump edge position is equal to the second delay jump edge position and equal to the jump edge position, the jump edge state is considered to be stable, the current jump edge position is updated, and the updated jump edge position is taken as an edge position.

Preferably, when comparing whether the delay jump edge position at the current moment and the delay jump edge position at the last moment are equal, except for the two cases, the edge is considered to be normal jump, the current jump edge position is updated, and the updated jump edge position is taken as the edge position.

As an example of comparing whether the delay jump edge position at the current time is equal to the delay jump edge position at the previous time and judging whether the delay jump edge position swings in this embodiment: 1) If the current clock cycle edge position and the last clock cycle are equal and equal to the last clock cycle, i.e. the third delay transition edge position edge_offset_6dly is equal to the second delay transition edge position edge_offset_5dly and equal to the transition edge position edge_offset_4dly. At the moment, the edge position is considered to be kept unchanged for 3 periods and is stable, and at the moment, the jump edge information is normally updated to the current jump edge position edge_offset_7dly; the current jump edge position edge_offset_7dly is a jump edge position obtained after filtering according to the second delay jump edge position edge_offset_5dly and the third delay jump edge position edge_offset_6dly.

2) If the value of the edge position of the upper clock cycle plus 1 is equal to the upper clock cycle, or the value of the edge position of the upper clock cycle plus 1 is equal to the upper clock cycle. I.e. the third delay jump edge position edge_offset_6dly plus 1 is equal to the second delay jump edge position edge_offset_5dly, or the second delay jump edge position edge_offset_5dly plus 1 is equal to the third delay jump edge position edge_offset_6dly. At the moment, the jump edge is considered to swing in an invalid mode, and the current jump edge position edge_offset_7dly is kept unchanged;

3) The rest of the cases consider the edge as a normal transition, and the transition edge information is updated normally to the current transition edge position edge_offset_7dly.

In one embodiment, by using the edge information shaping circuit, invalid edge information of left and right continuous jump can be filtered, so that the frequency of data insertion and deletion is reduced, and the data jitter and error rate are reduced; meanwhile, edge positions are obtained through direct mapping according to the edge information, so that the edge position information can be obtained quickly, and the logic progression and convergence time sequence can be reduced conveniently.

Step 104: and calculating the sampling position of the over-sampling data according to the edge position, and sampling the over-sampling data based on the sampling position to obtain effective sampling data.

In one embodiment, a predetermined phase offset value is set.

Specifically, the phase offset value of the sampling is set to 4 or N/2 (N is an oversampling multiple), that is, when the transition edge position is in the nth phase (n=0 to 7), the sampling position is in n+n/2.

In one embodiment, a current sampling position is obtained, the current sampling position is subtracted from the edge position, and the phase offset value is added to obtain a sampling phase offset value; and judging whether the sampling phase offset value is 0, if so, directly taking the current sampling position as a sampling position, otherwise, adjusting the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampling data.

Specifically, subtracting the current sampling position from the edge position and adding a preset phase offset value to obtain a sampling phase offset value ph_delta, if the sampling phase offset value is 0, indicating that the current sampling position is exactly at the position farthest from the jump edge position, and at the moment, not needing to adjust the sampling position; if the operation result is not 0, it indicates that the current sampling position is not optimal, and the current sampling position should be adjusted to make the operation result be 0.

In an embodiment, when the current sampling position is adjusted according to the sampling phase offset value, a first sampling phase offset threshold value, a second sampling phase offset threshold value and a third sampling phase offset threshold value are set; when the sampling phase offset value is not smaller than the first sampling phase offset threshold value, subtracting 1 from the current sampling position to obtain a first adjustment position, and updating the first adjustment position to the current sampling position; when the sampling phase offset value is not smaller than the second sampling phase offset threshold value and smaller than the first sampling phase offset threshold value, subtracting 2 from the current sampling position to obtain a second adjustment position, and updating the second adjustment position to the current sampling position; when the sampling phase offset value is determined to be larger than the third sampling phase offset threshold and smaller than the second sampling phase offset threshold, adding 2 to the current sampling position to obtain a third adjustment position, and updating the third adjustment position to the current sampling position; and when the sampling phase offset value is not larger than the third sampling phase offset threshold value, adding 1 to the current sampling position to obtain a fourth adjustment position, and updating the fourth adjustment position to the current sampling position.

Preferably, the first sampling phase shift threshold is set to 6, the second sampling phase shift threshold is set to 4, and the third sampling phase shift threshold is set to 2.

Specifically, the current sampling position is adjusted in steps according to the magnitude of the sampling phase offset value, as follows:

1) If the sampling phase offset value is greater than or equal to the first sampling phase offset threshold value 6, subtracting 1 from the current sampling position, otherwise judging the next condition;

2) If the sampling phase offset value is greater than or equal to the second sampling phase offset threshold value 4 and is smaller than the first sampling phase offset threshold value 6, subtracting 2 from the current sampling position, otherwise judging the next condition;

3) If the sampling phase offset value is greater than the third sampling phase offset threshold value 2 and less than the second sampling phase offset threshold value 4, adding 2 to the current sampling position, otherwise judging the next condition;

4) If the sampling phase offset value is less than or equal to the third sampling phase offset threshold value 2, adding 1 to the current sampling position;

5) Returning the adjusted sampling position to the current sampling position, subtracting the current sampling position from the edge position, and adding the phase offset value to obtain a sampling phase offset value; and judging whether the sampling phase offset value is 0.

In an embodiment, a hierarchical negative feedback sampling position calculating circuit is adopted, a preset sampling position is subtracted from an edge position to obtain a phase difference value, the larger the phase difference value is, the larger the step is when the next sampling position is regulated, otherwise, the step is reduced, the rapid convergence can be achieved, the convergence timing is convenient, the rapid locking of data can be achieved, and the misjudgment probability of the sampling position is reduced.

In one embodiment, since the process of calculating the sampling position requires approximately M clock cycles, the obtained sampling position corresponds to the data delayed by M cycles; and based on the above, performing delay processing on the oversampled data to obtain second delay oversampled data, third delay oversampled data and fourth delay oversampled data.

Specifically, the parallel oversampling data data_din output by the high-speed SERDES circuit is delayed to m+1 clock cycles, and the second delay oversampling data data_din_ (M-1) dly, the third delay oversampling data data_din_mdly, and the fourth delay oversampling data data_din_ (m+1) dly are obtained.

In an embodiment, the first sampling data is extracted from the second delayed oversampling data, and the second sampling data is extracted from the fourth delayed oversampling data, and the first sampling data, the third sampling data and the third delayed oversampling data are spliced to obtain second oversampled spliced data.

Specifically, the first bit of sampling data is extracted from the fourth delay oversampling data as first sampling data data_din_ (M+1) dly [0], the last bit of sampling data is extracted from the fourth delay oversampling data as second sampling data data_din_ (M-1) dly [31], and the first sampling data data_din_ (M+1) dly [0], the third delay oversampling data data_din_Mdly [31:0] and the second sampling data data_din_ (M-1) dly [31] are spliced to obtain second oversampling spliced data data_sample_din [33:0]. When each value is taken, 3 bits are continuously taken from the first 1bit of the sampling position, and the bit width can ensure that the lower standard value cannot overflow each time data is taken.

In an embodiment, the sampling position is delayed to obtain a current sampling position and an up-clock period sampling position.

Specifically, the sampling position smp_pos_f is delayed by 2 clock cycles to obtain the current sampling position samp_loc_1dly and the upper clock cycle sampling position samp_loc_2dly, respectively.

In one embodiment, in order to improve the accuracy of judgment during data sampling, multi-bit data is sampled, and a final result is obtained by adopting a majority judgment mode, so that the bit error rate can be optimized when the signal quality is bad; meanwhile, when the sampling position jumps from 7 to 0 or from 0 to 7, the circuit needs to insert 1bit and delete 1bit data, respectively.

Specifically, when the current sampling position is determined to be at a preset first range position, a plurality of groups of first effective data sets are extracted from the second oversampled spliced data according to the current sampling position, all effective data in each group of first effective data sets are added to obtain a plurality of groups of first effective data sums, if the first effective data sums are larger than preset effective data and a threshold value, the first effective data obtained by sampling in the first effective data and the corresponding effective data sets is determined to be 1, otherwise, the first effective data obtained by sampling in the first effective data and the corresponding first effective data sets is determined to be 0, and the first effective data corresponding to all the first effective data sets are integrated to obtain first effective sampling data.

Preferably, the position of the first range is preset to be a certain integer from 1 to 6, and the preset valid data and the threshold value are 2; and if the current sampling position X is a certain integer from 1 to 6, taking out the first effective data set data_sample_din [ 0X 8+X+2:0X 8+X ], and obtaining the 3-bit effective data. Adding the 3bit data, judging that the first effective data obtained by sampling is 1 if the first effective data sum is more than or equal to 2, otherwise, considering that the first effective data obtained by sampling is 0; and similarly, extracting the effective data in the first effective data set data_sample_din [1 x 8+X+2:1 x 8+X ], the first effective data set data_sample_din [2 x 8+X+2:2 x 8+X ] and the first effective data set data_sample_din [3 x 8+X+2:3 x 8+X ]. The first valid sampling data output in the current clock cycle is 4bit valid data.

Specifically, when the sampling position of the upper clock period is determined to be at a preset first target position and the current sampling position is 0, extracting a plurality of groups of second effective data sets from the second oversampling spliced data according to the sampling position of the upper clock period, adding all effective data in each group of second effective data sets to obtain a plurality of groups of second effective data sums, if the second effective data sums are greater than a preset effective data and a threshold value, determining that the second effective data obtained by sampling in the second effective data and the corresponding effective data sets is 1, otherwise, determining that the second effective data obtained by sampling in the second effective data and the corresponding second effective data sets is 0, and integrating the second sampled data and the second effective data corresponding to all the second effective data sets to obtain second effective sampled data.

Preferably, if the sampling position of the previous clock cycle is 7 and the sampling position of the current clock cycle is 0, 1bit of valid data is considered to exist between the two valid data, at this time, the 0 th bit data of the fourth delay oversampling data data_din_ (m+1) dly is taken out to obtain 1bit of valid data, and then 4 bits of valid data are taken out in the data_sample_din [33:0] according to the above steps, namely, the second valid sampling data output in the current clock cycle is 5 bits of valid data.

Specifically, when the sampling position of the upper clock period is determined to be at a preset second target position and the current sampling position is 1, extracting a plurality of groups of third effective data sets from the second oversampling spliced data according to the sampling position of the upper clock period, wherein the difference between the number of the third effective data sets and the number of the second effective data sets is 1; and adding all the effective data in each group of third effective data sets to obtain a plurality of groups of third effective data sums, if the third effective data sums are larger than preset effective data and a threshold value, determining that the third effective data obtained by sampling in the third effective data sets and the corresponding effective data sets is 1, otherwise, determining that the third effective data obtained by sampling in the third effective data sets and the corresponding effective data sets is 0, and integrating the second effective data corresponding to all the third effective data sets to obtain third effective sampling data.

Preferably, the second target position is preset to be 0, if the sampling position of the previous clock cycle is 0 and the sampling position of the current clock cycle is 1, the two valid data samples are considered to be repeated, and 1bit data needs to be discarded. At this time, the valid data in the first valid data set data_sample_din [0×8+x+2:0×8+x ], the first valid data set data_sample_din [1×8+x+2:1×8+x ], and the first valid data set data_sample_din [2×8+x+2:2×8+x ] are extracted according to the above steps, that is, the third valid sample data output in the current clock cycle is 3bit valid data.

Step 105: and inputting the valid sampling data into a bit width conversion circuit so that the bit width conversion circuit outputs fixed bit width valid data.

In one embodiment, since valid sample data output per clock cycle may be 3bit, 4bit, and 5bit, it is necessary to convert it into fixed bit width valid data output; preferably, the fixed bit width valid data is 8bit data.

In one embodiment, a shift register is provided; preferably, a 12bit wide shift register data_shift [11:0] is provided.

In one embodiment, the effective data length of the effective data is obtained, the effective data is input into the shift register, the effective data length is shifted out from the shift register, and the shift register is updated.

Specifically, when the effective data length of the obtained effective data is 3 bits, the effective data is shifted into the shift register from a low level, and the effective data length shifted out from the high level of the shift register is several data, namely, the high 3 bits of the shift register are shifted out.

Specifically, when the effective data length of the obtained effective data is 4 bits, the effective data is shifted into the shift register from a low level, and the effective data length shifted out from the high level of the shift register is several data, namely the high 4 bits of the shift register are shifted out.

Specifically, when the effective data length of the obtained effective data is 5 bits, the effective data is shifted into the shift register from a low level, and the effective data length shifted out from the high level of the shift register is several data, namely, the high 5 bits data of the shift register is shifted out.

In one embodiment, a counter is set, based on the counter, the effective data amount in the shift register is recorded, and when the effective data amount is not smaller than a preset fixed bit width, based on the data bit corresponding to the effective data amount, the fixed bit width effective data is extracted and output from the shift register.

Specifically, a counter bit_cnt is set to record the number of valid data in the shift register. When the number of the effective data recorded by the counter bit_cnt is smaller than 8, if 3 bits of effective data are moved in, adding 3 to the number of the effective data recorded by the counter bit_cnt; if the effective data of 4 bits is moved in, adding 4 to the number of the effective data recorded by the counter bit_cnt; if the 5bit valid data is moved in, the number of valid data recorded by the counter bit_cnt is increased by 5. When the number of the effective data recorded by the counter bit_cnt is more than or equal to 8, if 3 bits of effective data are moved in, the number of the effective data recorded by the counter bit_cnt is reduced by 5; if the effective data of 4 bits is moved in, the number of the effective data recorded by the counter bit_cnt is reduced by 4; if 5 bits of valid data are moved in, the number of valid data recorded by the counter bit_cnt is reduced by 3. When the number of the effective data recorded by the counter bit_cnt is more than or equal to 8, the 8bit data is downwards fetched from the bit represented by the current numerical value of the counter bit_cnt in the shift register data_shift, and meanwhile, the data effective signal is pulled high, namely, the 8bit effective data is output when the data effective signal is high.

Embodiment 2, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of an apparatus for recovering oversampled data provided in the present invention, and as shown in fig. 2, the apparatus includes a sample data splicing module 201, a sample data sliding comparing module 202, an edge information shaping module 203, a sample position calculating module 204, and a fixed bit width valid data outputting module 205, which are specifically as follows:

the sampled data splicing module 201 is configured to convert received serial data into oversampled data, delay the oversampled data to obtain first delayed oversampled data, and splice the first delayed oversampled data and the oversampled data to obtain first oversampled spliced data.

The sample data sliding comparison module 202 is configured to perform sliding comparison on the first oversampled spliced data and preset first binary string sequence data to obtain jump edge information of the oversampled data, and perform mapping processing on the jump edge information to obtain a jump edge position.

The edge information shaping module 203 is configured to input the jump edge position to an edge information shaping circuit, so that the edge information shaping circuit performs shaping processing on the jump edge position to obtain an edge position.

The sampling position calculating module 204 is configured to calculate a sampling position of the oversampled data according to the edge position, and sample the oversampled data based on the sampling position to obtain effective sampling data.

The fixed bit width valid data output module 205 is configured to input the valid sampling data into a bit width conversion circuit, so that the bit width conversion circuit outputs fixed bit width valid data.

In an embodiment, the sliding comparison module 202 for sampling data is configured to perform sliding comparison on the first oversampled spliced data and preset first binary string sequence data to obtain jump edge information of the oversampled data, and specifically includes: acquiring the sequence length of preset first binary string sequence data, and selecting a plurality of data segments from the first oversampled spliced data according to a preset sequence based on the sequence length; comparing each data segment with the first binary string sequence data respectively, if the data segment is the same as the first binary string sequence data, considering that a first data bit in the current data segment has a jump edge of the oversampling data, and assigning the first data bit to be 1, otherwise, considering that the first data bit in the current data segment does not have the jump edge of the oversampling data, and assigning the first data bit to be 0; and assigning data to the first data bit corresponding to each data segment to obtain jump edge information of the oversampling data.

In an embodiment, the sample data sliding comparison module 202 is configured to map the jump edge information to obtain a jump edge position, and specifically includes: performing granularity division processing on the jump edge information so as to divide the jump edge information into a plurality of jump edge granularity segments; comparing each jump edge granularity section with a plurality of preset second binary string sequence data respectively, and determining the phase position of the jump edge in each jump edge granularity section according to a comparison result; and integrating all the phase positions to obtain the jump edge position of the oversampled data.

In one embodiment, the edge information shaping module 203 is configured to, before inputting the jump edge position to the edge information shaping circuit, further include: and extracting a jump edge position section from the jump edge position, comparing the jump edge position section with a plurality of pieces of third binary string sequence data respectively, if the third binary string sequence data which are the same as the jump edge position section exist, carrying out delay processing on the jump edge position to obtain a first delay jump edge position, and updating the first delay jump edge position into a current jump edge position.

In an embodiment, the edge information shaping module 203 is configured to input the jump edge position to an edge information shaping circuit, so that the edge information shaping circuit performs shaping processing on the jump edge position to obtain an edge position, and specifically includes: inputting the jump edge position into an edge information shaping circuit, so that the edge information shaping circuit delays the jump edge position to obtain a second delay jump edge position, and delays the second delay jump edge position to obtain a third delay jump edge position; adding 1 to the second delay jump edge position and the third delay jump edge position respectively to obtain a second adding delay jump edge position and a third adding delay jump edge position; and if the second and one delay jump edge positions are the same as the third delay jump edge positions, or the third and one delay jump edge positions are the same as the second delay jump edge positions, the jump edge is considered to swing in an invalid way, and the jump edge positions are taken as edge positions.

In one embodiment, the sampling position calculating module 204 is configured to calculate, according to the edge position, a sampling position of the oversampled data, and specifically includes: setting a preset phase offset value, acquiring a current sampling position, subtracting the current sampling position from the edge position, and adding the phase offset value to obtain a sampling phase offset value; and judging whether the sampling phase offset value is 0, if so, directly taking the current sampling position as a sampling position, otherwise, adjusting the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampling data.

In one embodiment, the sampling position calculating module 204 is configured to adjust the current sampling position according to the sampling phase offset value, and specifically includes: setting a first sampling phase shift threshold, a second sampling phase shift threshold and a third sampling phase shift threshold; when the sampling phase offset value is not smaller than the first sampling phase offset threshold value, subtracting 1 from the current sampling position to obtain a first adjustment position, and updating the first adjustment position to the current sampling position; when the sampling phase offset value is not smaller than the second sampling phase offset threshold value and smaller than the first sampling phase offset threshold value, subtracting 2 from the current sampling position to obtain a second adjustment position, and updating the second adjustment position to the current sampling position; when the sampling phase offset value is determined to be larger than the third sampling phase offset threshold and smaller than the second sampling phase offset threshold, adding 2 to the current sampling position to obtain a third adjustment position, and updating the third adjustment position to the current sampling position; and when the sampling phase offset value is not larger than the third sampling phase offset threshold value, adding 1 to the current sampling position to obtain a fourth adjustment position, and updating the fourth adjustment position to the current sampling position.

In one embodiment, the sampling position calculating module 204 is configured to perform sampling processing on the oversampled data based on the sampling position to obtain effective sampled data, and specifically includes: delay processing is carried out on the oversampling data to obtain second delay oversampling data, third delay oversampling data and fourth delay oversampling data; extracting first sampling data from the second delay oversampling data, extracting second sampling data from the fourth delay oversampling data, and splicing the first sampling data, the third sampling data and the third delay oversampling data to obtain second oversampling spliced data; performing delay processing on the sampling position to obtain a current sampling position and an upper clock period sampling position; when the current sampling position is determined to be at a preset first range position, extracting a plurality of groups of first effective data sets from the second oversampling spliced data according to the current sampling position, adding all effective data in each group of first effective data sets to obtain a plurality of groups of first effective data sums, if the first effective data sums are larger than preset effective data and a threshold value, determining that the first effective data obtained by sampling in the first effective data and the corresponding effective data sets is 1, otherwise, determining that the first effective data obtained by sampling in the first effective data and the corresponding first effective data sets is 0, and integrating the first effective data corresponding to all the first effective data sets to obtain first effective sampling data; when the sampling position of the upper clock period is determined to be at a preset first target position and the current sampling position is 0, extracting a plurality of groups of second effective data sets from the second oversampling spliced data according to the sampling position of the upper clock period, adding all effective data in each group of second effective data sets to obtain a plurality of groups of second effective data sums, if the sum of the second effective data is greater than a preset effective data and a threshold value, determining that the second effective data obtained by sampling in the second effective data and the corresponding effective data sets is 1, otherwise, determining that the second effective data obtained by sampling in the second effective data and the corresponding second effective data sets is 0, and integrating the second sampling data and the second effective data corresponding to all the second effective data sets to obtain second effective sampling data; when the upper clock period sampling position is determined to be at a preset second target position and the current sampling position is 1, extracting a plurality of groups of third effective data sets from the second oversampling spliced data according to the upper clock period sampling position, wherein the difference between the number of the third effective data sets and the number of the second effective data sets is 1; and adding all the effective data in each group of third effective data sets to obtain a plurality of groups of third effective data sums, if the third effective data sums are larger than preset effective data and a threshold value, determining that the third effective data obtained by sampling in the third effective data sets and the corresponding effective data sets is 1, otherwise, determining that the third effective data obtained by sampling in the third effective data sets and the corresponding effective data sets is 0, and integrating the second effective data corresponding to all the third effective data sets to obtain third effective sampling data.

In one embodiment, the fixed bit width valid data output module 205 is configured to input the valid sampling data into a bit width conversion circuit, so that the bit width conversion circuit outputs the fixed bit width valid data, and specifically includes: setting a shift register; acquiring the effective data length of the effective data, inputting the effective data into the shift register, moving out the effective data length data from the shift register, and updating the shift register; setting a counter, recording the effective data quantity in the shift register based on the counter, and extracting and outputting the effective data with the fixed bit width from the shift register based on the data bit corresponding to the effective data quantity when the effective data quantity is not smaller than the preset fixed bit width.

It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to the corresponding process in the foregoing method embodiment for the specific working process of the above-described apparatus, which is not described in detail herein.

It should be noted that the above embodiment of the apparatus for recovering oversampled data is merely illustrative, where the modules described as separate components may or may not be physically separated, and components displayed as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

On the basis of the embodiment of the method for recovering oversampled data, another embodiment of the present invention provides an apparatus for recovering oversampled data, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, where the processor executes the computer program to implement the method for recovering oversampled data according to any one of the embodiments of the present invention.

Illustratively, in this embodiment the computer program may be partitioned into one or more modules, which are stored in the memory and executed by the processor to perform the present invention. The one or more modules may be a series of computer program instruction segments capable of performing a specific function for describing the execution of the computer program in the terminal device for the recovery of oversampled data.

The over-sampled data recovery terminal device can be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server and the like. The recovery terminal device for the oversampled data may include, but is not limited to, a processor, a memory.

The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, which is a control center of the over-sampled data recovery terminal device, connecting the various parts of the entire over-sampled data recovery terminal device using various interfaces and lines.

The memory may be used to store the computer program and/or the module, and the processor may implement various functions of the oversampled data recovery terminal device by running or executing the computer program and/or the module stored in the memory and invoking the data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the cellular phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.

On the basis of the embodiment of the method for recovering oversampled data, another embodiment of the present invention provides a storage medium, where the storage medium includes a stored computer program, and when the computer program runs, the device where the storage medium is controlled to execute the method for recovering oversampled data according to any one of the embodiments of the present invention.

In this embodiment, the storage medium is a computer-readable storage medium, and the computer program includes computer program code, where the computer program code may be in a source code form, an object code form, an executable file, or some intermediate form, and so on. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

In summary, according to the method, the device, the equipment and the storage medium for recovering the oversampled data, the received serial data are converted into the oversampled data, the oversampled data are subjected to delay processing to obtain first delay oversampled data, and the first delay oversampled data and the oversampled data are spliced to obtain first oversampled spliced data; sliding comparison is carried out on the first oversampling spliced data and the first binary string sequence data to obtain jump edge information of the oversampling data, and mapping processing is carried out on the jump edge information to obtain jump edge positions; inputting the jump edge position into an edge information shaping circuit for shaping treatment to obtain an edge position; according to the edge position, calculating the sampling position of the over-sampling data, and carrying out sampling processing on the over-sampling data based on the sampling position to obtain effective sampling data; inputting the effective sampling data into a bit width conversion circuit, and outputting fixed bit width effective data; compared with the prior art, the technical scheme of the invention splices the first delay oversampling data with the oversampling data to obtain the first oversampling spliced data, and compares the first oversampling spliced data with the first binary string sequence data in a sliding manner to obtain jump edge information, so that irregular jump of the data jump edge and misjudgment of data jitter in the middle of the oversampling data can be effectively filtered, and the accuracy of subsequent oversampling data recovery is improved.

The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and substitutions should also be considered as being within the scope of the present invention.

Claims

1. A method for recovering oversampled data, comprising:

2. The method for recovering oversampled data according to claim 1, wherein sliding comparing the first oversampled spliced data with a preset first binary string sequence data to obtain jump edge information of the oversampled data, specifically comprising:

3. The method for recovering oversampled data according to claim 1, wherein mapping the jump edge information to obtain a jump edge position, specifically comprises:

4. The method for recovering oversampled data as recited in claim 1, wherein before inputting the transition edge position to the edge information shaping circuit, further comprising:

5. The method for recovering oversampled data as claimed in claim 4, wherein the step of inputting the step edge position to an edge information shaping circuit, so that the edge information shaping circuit performs shaping processing on the step edge position to obtain an edge position, comprises:

6. The method for recovering oversampled data in accordance with claim 1, wherein calculating a sampling position of the oversampled data based on the edge position, in particular comprises:

7. The method for recovering oversampled data in accordance with claim 6, wherein adjusting the current sampling position in accordance with the sampling phase offset value comprises:

8. The method for recovering oversampled data according to claim 1, wherein the step of sampling the oversampled data based on the sampling position to obtain effective sampled data comprises:

9. The method for recovering oversampled data in accordance with claim 1, wherein inputting the valid sample data into a bit width conversion circuit, such that the bit width conversion circuit outputs fixed bit width valid data, comprises:

Setting a shift register;

10. An apparatus for recovering oversampled data, comprising: the device comprises a sampling data splicing module, a sampling data sliding comparison module, an edge information shaping module, a sampling position calculation module and a fixed bit width effective data output module;

11. A terminal device comprising a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the method of recovering oversampled data according to any one of claims 1 to 9 when the computer program is executed.

12. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored computer program, wherein the computer program, when run, controls a device in which the computer readable storage medium is located to perform the method of recovering oversampled data according to any one of claims 1 to 9.