CN115632041A - TMV structure, preparation method thereof and packaging structure - Google Patents

TMV structure, preparation method thereof and packaging structure Download PDF

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Publication number
CN115632041A
CN115632041A CN202211127322.3A CN202211127322A CN115632041A CN 115632041 A CN115632041 A CN 115632041A CN 202211127322 A CN202211127322 A CN 202211127322A CN 115632041 A CN115632041 A CN 115632041A
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layer
wiring
layers
seed
hole
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CN202211127322.3A
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CN115632041B (en
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杨鲁东
甘志华
吴雷
于长存
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Beijing Qixing Huachuang Microelectronics Co ltd
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Beijing Qixing Huachuang Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The application relates to the technical field of microelectronic packaging, in particular to a TMV structure, a preparation method thereof and a packaging structure, wherein the TMV structure comprises a substrate, a plurality of first wiring layers, an insulating layer, a plurality of seed layers and a plurality of second wiring layers; a plurality of first wiring layers are arranged on the substrate at intervals; the insulating layer covers the substrate and the first wiring layers, and is provided with through holes so as to expose one end of each first wiring layer; the plurality of seed layers are arranged on the surface of the insulating layer and distributed at intervals, and the seed layers correspond to and are connected with the exposed end parts of the first wiring layer one by one; the second wiring layers correspond to the seed layers one by one and cover the seed layers. The method has the effect that the through hole with smaller diameter can be processed without the help of more advanced laser processing equipment, and the interconnection with higher density can be realized.

Description

TMV structure, preparation method thereof and packaging structure
Technical Field
The application relates to the technical field of microelectronic chip packaging, in particular to a TMV structure, a preparation method thereof and a packaging structure.
Background
The market demands for miniaturization, low power consumption and high performance of devices push the development of microelectronic packaging technology. Recent rapid development of portable consumer electronics has put higher demands on integration, light weight, and low delay of packaging. Vertical interconnects are a key technology for achieving 3D high density interconnects in wafer level packaging. Common vertical interconnect structures are TSV (Through Silicon Via), TGV (Through Glass Via), and TMV (Through Molding Via). The TMV has the advantages of lowest manufacturing cost, shortest process flow and lowest technical difficulty. Through holes can be directly formed through a laser ablation mode, and the through holes are filled with conductive materials through subsequent sputtering and electroplating, so that the interlayer interconnection can be realized. But limited by the thermal effect of laser, the conventional laser is difficult to realize a through hole with the diameter of less than 50 μm, and compared with TSV and TGV, the hole diameter of TMV is larger, so that the conventional laser is difficult to apply to the occasions of high-density interconnection. The picosecond femtosecond laser capable of manufacturing the TMV through hole with smaller aperture is limited by the power of a laser light source, the processing speed is too slow, and the large-scale application is difficult.
Disclosure of Invention
In order to improve the TMV interconnection density, the application provides a TMV structure, a preparation method thereof and a packaging structure.
The TMV structure and the preparation method and the packaging structure thereof adopt the following technical scheme:
in one aspect, a TMV structure comprises:
a substrate;
a plurality of first wiring layers arranged on the substrate at intervals;
the insulating layer covers the substrate and the first wiring layers, and is provided with through holes, and one end of each first wiring layer is exposed by each through hole; and the number of the first and second groups,
and the conductive circuit layers are formed on the surface of the insulating layer and extend into the through hole, are distributed at intervals, correspond to the first wiring layers one by one, and are connected with the exposed end parts of the first wiring layers.
By adopting the technical scheme, the plurality of conductive circuit layers correspond to the plurality of first wiring layers one by one and are connected with each other, and the through holes are patterned, so that one through hole can realize the connection of a plurality of circuits. Compared with the traditional method that the conducting material is filled in one through hole and only one line can be connected, the method has the advantages that the through hole is connected with multiple lines, the through hole with the smaller diameter can be processed without the aid of more advanced laser processing equipment, interconnection with higher density can be achieved, and the interconnection density of the TMV vertical structure is remarkably improved. Compared with the picosecond femtosecond laser device and the method for manufacturing the narrower through hole to realize high-density interconnection, the requirement on the laser device is lower, the efficiency of laser drilling is higher, the processing difficulty is reduced, and the processing cost is reduced.
Optionally, the conductive line layer includes a seed layer and a second wiring layer;
the seed layers are arranged on the surface of the insulating layer and distributed at intervals, and the seed layers correspond to the first wiring layers one by one and are connected with the exposed end parts; the second wiring layers correspond to the seed layers one by one and are formed on the surfaces of the seed layers.
By adopting the technical scheme and the arrangement of the seed layer, the electroplating of the second wiring layer is smoothly carried out.
Optionally, the through hole is narrow at the bottom and wide at the top, and an inclined plane inclining outwards is formed.
By adopting the technical scheme, the seed layer and the second wiring layer are conveniently arranged on the side wall of the insulating layer provided with the through hole, and the processing time is shortened.
In a second aspect, the present application also relates to a method for preparing a TMV structure, comprising the steps of:
s1: providing a substrate, and arranging a plurality of first wiring layers arranged at intervals on the substrate;
s2: covering an insulating layer on the substrate and the first wiring layer;
s3: forming a through hole in the insulating layer to expose one end of each of the first wiring layers;
s4: and forming a plurality of conducting circuit layers arranged at intervals in the surface of the insulating layer and the through hole, wherein the conducting circuit layers correspond to the first wiring layers one to one and are connected with the exposed end parts.
By adopting the technical scheme, the second wiring layers are in one-to-one correspondence and connection with the conducting circuit layers, and the through hole is patterned, so that the connection of multiple lines can be realized by one through hole, the interconnection density of the TMV vertical structure is obviously improved, the processing difficulty is reduced, and the processing cost is reduced.
Optionally, in step S2, the substrate and the first wiring layer are plastically packaged by using liquid resin, so as to form the insulating layer.
By adopting the technical scheme, the curing agent is added into the liquid resin, and the liquid resin is heated, so that the liquid resin can be cured, an insulating effect is achieved, and the processing is simple.
Optionally, in step S2, a dry film or a prepreg is laminated on the substrate and the first wiring layer to form the insulating layer.
By adopting the technical scheme, the dry film or the prepreg is heated, so that the dry film or the prepreg can be cured, an insulating effect is achieved, and the processing is simple.
Optionally, in step S3, the through hole is formed by mechanical drilling or laser drilling.
By adopting the technical scheme, the insulating layer can be drilled by controlling the drilling depth, so that the first wiring layer is prevented from being etched.
Optionally, in step S3, the through hole is narrow at the bottom and wide at the top, and an inclined plane inclined outwards is formed.
By adopting the technical scheme, the seed layer and the second wiring layer can be conveniently arranged on the side wall of the insulating layer provided with the through hole.
Optionally, step S4 includes the following steps:
s41: seed layers are formed on the surface of the insulating layer and in the through hole;
s42: forming a plurality of second wiring layers arranged at intervals on the seed layer by using a pattern electroplating method, wherein the second wiring layers correspond to the first wiring layers one by one and are connected with the exposed end parts; and the number of the first and second groups,
s43: and removing the seed layer except the second wiring layer.
By adopting the technical scheme and the arrangement of the seed layer, the electroplating of the second wiring layer is smoothly carried out.
Optionally, step S5 specifically includes the following steps:
s421: electroplating a conductive layer on the seed layer, wherein the conductive layer covers the seed layer;
s422: the pattern area of the conducting layer, which needs to be reserved, is a pattern area, and the pattern area is covered by photoresist; and the number of the first and second groups,
s423: and etching the parts of the conducting layer except the pattern area by using an etching process, etching the photoresist in the pattern area, and forming the second wiring layer on the conducting layer of the pattern area.
By adopting the technical scheme, the whole conductive layer is plated on the seed layer, the pattern area is covered by the photoetching process, the conductive layer and the seed layer outside the pattern area are etched by the etching process to form the final metalized pattern, and the position of the photoresist is arranged according to the pattern area, so that the difficulty of the electroplating process can be reduced.
Optionally, step S5 specifically includes the following steps:
s424: the pattern area of the seed layer which needs to be reserved is a pattern area, and photoresist is used for covering the part of the seed layer except the pattern area;
s425: electroplating a conductive layer on the pattern region on the seed layer; and the number of the first and second groups,
s426: and etching the photoresist and the seed layer except the pattern area by using an etching process, and forming the second wiring layer on the left conductive layer of the pattern area.
By adopting the technical scheme, the parts except the pattern area are firstly covered by the photoetching process, then the conducting layer is electroplated in the pattern area to form the metalized pattern, and the photoresist and the seed layer outside the pattern area are removed by the etching process, so that the etching amount of the circuit can be reduced, and the method is suitable for the pattern with a narrower circuit.
In a third aspect, the present application also relates to a package structure comprising a TMV structure as described in any of the above.
By adopting the technical scheme, the plurality of second wiring layers correspond to the plurality of first wiring layers one to one and are connected with the first wiring layers, and the through holes are patterned, so that the connection of a plurality of lines can be realized by one through hole, the interconnection density of the TMV vertical structure is obviously improved, the processing difficulty is reduced, and the processing cost is reduced.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the plurality of second wiring layers correspond to and are connected with the plurality of first wiring layers one by one, and the through holes are patterned, so that the connection of a plurality of lines is realized through one through hole, the interconnection with higher density can be realized, and the interconnection density of the TMV vertical structure is obviously improved.
2. Compared with the picosecond femtosecond laser device and the method for manufacturing the narrower through hole to realize high-density interconnection, the requirement on the laser device is lower, the efficiency of laser drilling is higher, the processing difficulty is reduced, and the processing cost is reduced.
3. The through hole on the insulating layer is narrow down and wide up, forms the inclined plane that leans out, and the seed layer of being convenient for and second wiring layer arrange on the insulating layer is equipped with the lateral wall of through hole, shorten process time.
Drawings
FIG. 1 is a schematic structural diagram of a TMV structure in example 1 of the present application;
fig. 2 is a schematic structural view of a TMV structure (insulating layer is hidden) shown in example 1;
FIG. 3 is a schematic structural diagram of a TMV structure in example 2 of the present application;
FIGS. 4 to 10 are schematic flow charts of the process for preparing the TMV structure in example 3 of the present application;
fig. 11 to 13 are schematic flow charts of step S42 in the method for preparing a TMV structure in example 4 of the present application.
Description of reference numerals: 1. a substrate; 11. a through hole; 2. a first wiring layer; 3. an insulating layer; 4. a seed layer; 5. a second wiring layer; 100. photoresist; 200. and a conductive layer.
Detailed Description
The present application is described in further detail below with reference to fig. 1.
The embodiment of the application discloses a TMV structure and a packaging structure, wherein the packaging structure comprises the TMV structure, and the TMV structure is specifically explained below.
Example 1
Referring to fig. 1, the tmv structure includes a substrate 1, a plurality of first wiring layers 2, an insulating layer 3, a plurality of seed layers 4, and a plurality of conductive line layers.
The substrate 1 may be a substrate or other mounting board, the substrate may be a ceramic substrate, a resin substrate, a glass substrate, or other materials capable of forming a conductive circuit on the surface, and the first wiring layer 2 may be made of metal such as copper and aluminum, or may be made of a conductive material filled with metal particles.
Referring to fig. 1 and 2, a plurality of first wiring layers 2 are arranged on a substrate 1 at intervals, an insulating layer 3 covers the substrate 1 and the first wiring layers 2, a through hole communicated with the first wiring layers 2 is formed at the bottom of the substrate 1, and a conductive material is filled in the through hole, so that the first wiring layers 2 and conductive parts below the substrate 1 can be electrically connected.
The insulating layer 3 is provided with a through hole 11 so that one end of each first wiring layer 2 is exposed. The through holes 11 include, but are not limited to, circular holes, anisotropic holes, or polygonal holes having a circular cross section, and only one end of each first wiring layer 2 needs to be exposed, and the shape of the through holes 11 in the cross section is not limited. In the present embodiment, the through-hole 11 is arranged in a circular shape in cross section.
A plurality of conducting circuit layers are formed on the surface of the insulating layer 3 and extend into the through hole 11, the conducting circuit layers are distributed at intervals, correspond to the first wiring layers 2 one by one and are connected with the exposed end parts of the first wiring layers 2, and the conducting circuit layers are in circuit communication with the first wiring layers one by one.
The plurality of seed layers 4 are arranged on the surface of the insulating layer 3, the surface of the insulating layer 3 comprises the top surface of the insulating layer 3 and the side wall provided with the through hole 11, the plurality of seed layers 4 are distributed at intervals, and the seed layers 4 correspond to the first wiring layers 2 one by one and are connected with the exposed end parts.
The second wiring layers 5 correspond to the seed layers 4 one by one and are formed on the surface of the seed layer 4, and the material of the second wiring layers 5 may be copper, aluminum, or other conductive material deposited on the surface by electroplating. The seed layer 4 provides a good conductive layer, and allows the plating of the second wiring layer 5 to be smoothly performed.
The through hole 11 may be a straight cylinder, so that the sidewall of the insulating layer 3 where the through hole 11 is disposed is vertically disposed, and the seed layer 4 and the second wiring layer 5 may also be plated on the sidewall of the insulating layer 3 where the through hole 11 is disposed. In the present embodiment, the through hole 11 is narrow at the bottom and wide at the top, and forms an inclined plane inclined outward, so that the seed layer 4 and the second wiring layer 5 are deposited on the sidewall of the insulating layer 3 where the through hole 11 is formed, and the processing time is shortened. It should be noted that, in the package structure, the remaining void in the through hole 11 may be filled with an insulating material.
The second wiring layer 5 is connected with the first wiring layer 2 through the seed layer 4, the plurality of second wiring layers 5 are in one-to-one correspondence with and connected with the plurality of first wiring layers 2, and the through holes 11 are patterned, so that one through hole 11 can realize the connection of a plurality of lines. Compared with the traditional method that the conducting material is filled in one through hole 11, and the connection of one line can only be realized, the connection of multiple lines is realized through one through hole 11 in the application, the through hole 11 with smaller diameter can be processed without the help of more advanced laser processing equipment, the interconnection with higher density can be realized, and the interconnection density of the TMV vertical structure is obviously improved. Compared with the picosecond femtosecond laser device and the method for manufacturing the narrower through hole 11 to realize high-density interconnection, the requirement on the laser device is lower, the efficiency of laser drilling is higher, the processing difficulty is reduced, and the processing cost is reduced.
Example 2
Referring to fig. 3, embodiment 2 is different from embodiment 1 in that the through-hole 11 is arranged in a long bar shape in cross section.
Referring to fig. 4 to 13, an embodiment of the present application further discloses a method for preparing a TMV structure.
Example 3
The preparation method of the TMV structure comprises the following steps:
s1: referring to fig. 4, a substrate 1 is provided, a plurality of first wiring layers 2 arranged at intervals are arranged on the substrate 1, and the positions and the number of the first wiring layers 2 can be set according to actual needs.
S2: referring to fig. 5, an insulating layer 3 is covered on a substrate 1 and a first wiring layer 2.
The insulating layer 3 can be formed by applying a curable resin composition such as various conventionally known thermosetting resin compositions or photocurable and thermosetting resin compositions, or by laminating a dry film or a prepreg. Preferably, the insulating layer 3 is coated on the surfaces of the substrate 1 and the first wiring layer 2 by dry film lamination or liquid resin molding.
S3: referring to fig. 6, a through hole 11 is opened in the insulating layer 3 so as to expose one end of each first wiring layer 2, and specifically, the through hole 11 is opened by mechanical drilling or laser drilling. The shape and size of the through hole 11 are set according to the arrangement position of the first wiring layer 2. The through holes 11 include, but are not limited to, circular holes, anisotropic holes, and polygonal holes having a circular cross section, and only one end of each first wiring layer 2 needs to be exposed, and the shape of the through holes 11 in the cross section is not limited.
Preferably, the through hole 11 is narrow at the bottom and wide at the top, forming an inclined plane inclined outwards, so that the seed layer 4 and the second wiring layer 5 can be deposited on the side wall of the insulating layer 3 where the through hole 11 is located.
S4: a plurality of conducting circuit layers arranged at intervals are formed on the surface of the insulating layer 3 and in the through holes 11, and the conducting circuit layers correspond to the first wiring layers 2 one to one and are connected with the exposed end portions.
Specifically, the method comprises the following steps:
s41: referring to fig. 7, the seed layer 4 is formed on the surface of the insulating layer 3 and in the through-hole 11, and the seed layer 4 for enabling electroplating may be prepared by chemical plating, sputtering, or evaporation.
S42: a plurality of second wiring layers 5 are formed on the seed layer 4 at intervals by a pattern plating method, and the second wiring layers 5 are in one-to-one correspondence with the first wiring layers 2 and are connected to the exposed end portions.
Specifically, step S5 includes the following steps:
s421: referring to fig. 8, a conductive layer 200 is plated on the seed layer 4, the conductive layer 200 covering all the seed layer 4;
s422: referring to fig. 9, a pattern region to be reserved in the conductive layer 200 is a pattern region, and a region to be etched away is a non-wiring region, the pattern region is covered by the photoresist 100, and the photoresist 100 may be a solid photoresist 100 or a liquid photoresist 100, and the surface of the conductive layer 200 is patterned to selectively shield the pattern region on the conductive layer 200.
S423: referring to fig. 10, a portion of the non-wiring region of the conductive layer 200 other than the pattern region is etched by an etching process, the photoresist 100 in the pattern region is etched, and the second wiring layer 5 is formed on the conductive layer 200 in the pattern region by wet etching or dry etching.
The whole conductive layer 200 is firstly electroplated on the seed layer 4, the material of the conductive layer 200 can be copper, aluminum and other materials which can be deposited on the surface in an electroplating mode, then the pattern area is covered by a photoetching process, the conductive layer 200 and the seed layer 4 outside the pattern area are etched by the etching process to form a final metallization pattern, the position of the photoresist 100 is arranged according to the pattern area by adopting a mode of firstly electroplating and then patterning, and the difficulty of the electroplating process can be reduced.
S43: the seed layer 4 other than the second wiring layer 5 is removed, and wet etching or dry etching may be employed.
Example 4
Embodiment 4 differs from embodiment 3 in that step S42 specifically includes the following steps:
s424: referring to fig. 11, a part of the non-wiring region of the seed layer 4 except for the pattern region is covered by a photoresist 100, and the photoresist 100 may be a solid photoresist 100 or a liquid photoresist 100, and the surface of the seed layer 4 is patterned to selectively shield the non-wiring region on the seed layer 4.
S425: referring to fig. 12, a conductive layer 200 is plated on the pattern region on the seed layer 4.
S426: referring to fig. 13, the photoresist 100 and the seed layer 4 in the non-wiring region except for the pattern region are etched by an etching process, and the conductive layer 200 of the remaining pattern region may be formed into the second wiring layer 5 by wet etching or dry etching.
The parts except the pattern area are covered by the photoetching process, then the conducting layer 200 is electroplated in the pattern area to form a metalized pattern, the photoresist 100 and the seed layer 4 outside the pattern area are removed by the etching process in a mode of firstly patterning and then electroplating, the etching amount of the circuit can be reduced, and the method is suitable for the pattern with a narrower circuit.
The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: equivalent changes in structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims (10)

1. A TMV structure, comprising:
a substrate (1);
a plurality of first wiring layers (2) arranged on the substrate (1) at intervals;
the insulating layer (3) covers the substrate (1) and the first wiring layers (2), through holes (11) are formed in the insulating layer (3), and one end of each first wiring layer (2) is exposed out of each through hole (11); and the number of the first and second groups,
and the conductive circuit layers are formed on the surface of the insulating layer (3) and extend into the through hole (11), are distributed at intervals, correspond to the first wiring layers (2) one by one, and are connected with the exposed end parts of the first wiring layers (2).
2. The TMV structure according to claim 1, wherein the electrically conductive line layer comprises a seed layer (4) and a second wiring layer (5);
the seed layers (4) are arranged on the surface of the insulating layer (3), the seed layers (4) are distributed at intervals, and the seed layers (4) correspond to the first wiring layers (2) one by one and are connected with the exposed end parts; the second wiring layers (5) correspond to the seed layers (4) one by one and are formed on the surfaces of the seed layers (4).
3. TMV structure according to claim 1 or 2, characterized in that the through-hole (11) is narrow at the bottom and wide at the top, forming an inclined plane sloping outwards.
4. A preparation method of a TMV structure is characterized by comprising the following steps:
s1: providing a substrate (1), and arranging a plurality of first wiring layers (2) arranged at intervals on the substrate (1);
s2: covering an insulating layer (3) on the substrate (1) and the first wiring layer (2);
s3: forming a through hole (11) in the insulating layer (3) to expose one end of each of the first wiring layers (2);
s4: and forming a plurality of conducting circuit layers arranged at intervals on the surface of the insulating layer (3) and in the through hole (11), wherein the conducting circuit layers correspond to the first wiring layers (2) one to one and are connected with the exposed end parts.
5. The method for manufacturing a TMV structure according to claim 4, wherein in step S2, the substrate (1) and the first wiring layer (2) are plastically molded by using a liquid resin to form the insulating layer (3); and/or the presence of a gas in the gas,
in step S2, a dry film or a prepreg is laminated on the substrate (1) and the first wiring layer (2) to form the insulating layer (3).
6. The method for preparing a TMV structure according to claim 4, wherein in step S3, the through hole (11) is drilled by mechanical drilling or laser drilling; and/or the presence of a gas in the atmosphere,
in the step S3, the through hole (11) is arranged to be narrow at the bottom and wide at the top, and an inclined plane inclining outwards is formed.
7. The method for preparing a TMV structure according to claim 4, wherein step S4 comprises the steps of:
s41: forming a seed layer (4) on the surface of the insulating layer (3) and in the through hole (11);
s42: forming a plurality of second wiring layers (5) arranged at intervals on the seed layer (4) by using a pattern electroplating method, wherein the second wiring layers (5) correspond to the first wiring layers (2) one by one and are connected with the exposed end parts; and the number of the first and second groups,
s43: removing the seed layer (4) except the second wiring layer (5).
8. The method for preparing a TMV structure according to claim 7, wherein step S42 specifically comprises the steps of:
s421: -electroplating a conductive layer (200) on the seed layer (4), the conductive layer (200) covering the seed layer (4);
s422: the pattern area of the conducting layer (200) which needs to be reserved is a pattern area, and the pattern area of the conducting layer (200) is covered by photoresist (100); and the number of the first and second groups,
s423: and etching the part of the conductive layer (200) except the pattern area by using an etching process, etching the photoresist (100) in the pattern area, and forming the second wiring layer (5) on the conductive layer (200) of the left pattern area.
9. The method for preparing a TMV structure according to claim 7, wherein step S42 specifically comprises the steps of:
s424: the pattern area of the seed layer (4) which needs to be reserved is a pattern area, and photoresist (100) is used for covering the part of the seed layer (4) except the pattern area;
s425: electroplating a conductive layer (200) on the pattern region on the seed layer (4); and the number of the first and second groups,
s426: and etching the photoresist (100) and the seed layer (4) except the pattern area by using an etching process, and forming the second wiring layer (5) by the conducting layer (200) of the pattern area which is left.
10. A package structure comprising a TMV structure according to any of claims 1 to 3.
CN202211127322.3A 2022-09-16 2022-09-16 TMV structure, preparation method thereof and packaging structure Active CN115632041B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1836325A (en) * 2003-06-16 2006-09-20 谢尔卡斯有限公司 Methods and apparatus for packaging integrated circuit devices
JP2009252766A (en) * 2008-04-01 2009-10-29 Shinko Electric Ind Co Ltd Method of manufacturing wiring board
CN103151327A (en) * 2013-03-29 2013-06-12 日月光半导体制造股份有限公司 Semiconductor packaging piece and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1836325A (en) * 2003-06-16 2006-09-20 谢尔卡斯有限公司 Methods and apparatus for packaging integrated circuit devices
JP2009252766A (en) * 2008-04-01 2009-10-29 Shinko Electric Ind Co Ltd Method of manufacturing wiring board
CN103151327A (en) * 2013-03-29 2013-06-12 日月光半导体制造股份有限公司 Semiconductor packaging piece and manufacturing method thereof

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