CN115631776A - Phase change memory unit structure, phase change memory array and driving method - Google Patents
Phase change memory unit structure, phase change memory array and driving method Download PDFInfo
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- CN115631776A CN115631776A CN202211143725.7A CN202211143725A CN115631776A CN 115631776 A CN115631776 A CN 115631776A CN 202211143725 A CN202211143725 A CN 202211143725A CN 115631776 A CN115631776 A CN 115631776A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Abstract
The invention relates to a phase change memory unit structure, a phase change memory array and a driving method, wherein the phase change memory unit structure comprises a first phase change device, a second phase change device, a first gating device, a second gating device and a third gating device; the first end of the first phase change device is connected with a first bit line, and the first end of the second phase change device is connected with a second bit line; the second end of the first phase change device, the drain of the first gating device and the drain of the third gating device are connected together; the second end of the second phase change device, the drain of the second gating device and the source of the third gating device are connected together; the grid electrode of the first gating device and the grid electrode of the second gating device are connected together to be used as a word line of the phase change memory unit, the grid electrode of the third gating device is connected with the gating line, and the source electrode of the first gating device and the source electrode of the second gating device are both grounded. The invention can reduce the cost of the phase change memory chip.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a phase change memory cell structure, a phase change memory array and a driving method thereof.
Background
A Phase Change Memory (PCM) is a novel resistance change type nonvolatile semiconductor memory, which takes a chalcogenide compound material as a storage medium and realizes data storage by utilizing different resistance states of a nano-sized phase change material in a polycrystalline state (the material is in a low resistance state) and an amorphous state (the material is in a high resistance state). Phase change memory is considered as a new memory, and is considered as the next generation memory with the most potential development because of its characteristics of fast read/write speed, high erasable durability, long information retention time, low power consumption, non-volatility, etc., and especially these characteristics of phase change memory become more and more prominent with the reduction of the processing technology and the size of memory cells to the order of nanometers.
A conventional phase change memory adopts a 1T1R (1-Transistor-1-Resistor) cell structure, as shown in fig. 1, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is adopted as a gate Transistor by most enterprises with a mature process and low cost, and becomes a classical PCM cell structure, but in order to meet a required current density, a circuit design usually adopts a larger size, but the 1T1R cell structure cannot achieve a very high storage density, which undoubtedly increases the cost of a chip.
Disclosure of Invention
The invention aims to provide a phase change memory unit structure, a phase change memory array and a driving method, which are used for reducing the cost of a phase change memory chip.
The technical scheme adopted by the invention for solving the technical problems is as follows: providing a phase change memory unit structure, which comprises a first phase change device, a second phase change device, a first gating device, a second gating device and a third gating device; the first end of the first phase change device is connected with a first bit line, and the first end of the second phase change device is connected with a second bit line; the second end of the first phase change device, the drain of the first gating device and the drain of the third gating device are connected together; the second end of the second phase change device, the drain of the second gating device and the source of the third gating device are connected together; the grid electrode of the first gating device and the grid electrode of the second gating device are connected together to serve as a word line of the phase change memory unit, the grid electrode of the third gating device is connected with a gating line, and the source electrode of the first gating device and the source electrode of the second gating device are both grounded.
The first phase change device and the second phase change device are identical.
The first gating device and the second gating device are identical in size.
The first gating device, the second gating device and the third gating device are all NMOS tubes.
The technical scheme adopted by the invention for solving the technical problems is as follows: the phase change memory array comprises M multiplied by N phase change memory unit structures, wherein the M multiplied by N phase change memory unit structures are arranged in a matrix array form, word lines of the phase change memory unit structures in the same row are shared, gate lines of the phase change memory unit structures in the same row are shared, first bit lines and second bit lines of the phase change memory unit structures in the same column are shared, and each bit line is provided with a transmission gate.
The technical scheme adopted by the invention for solving the technical problems is as follows: the writing driving method of the phase change memory array is applied, the transmission gates of the word lines, the gate lines and the bit lines connected with the target phase change memory unit are started, the writing programming current pulse is applied to the bit line where the target phase change memory unit is located, and the writing programming current is driven by the first gating device, the second gating device and the third gating device together.
The technical scheme adopted by the invention for solving the technical problem is as follows: the read driving method applying the phase change memory array is provided, the transmission gates of the word lines and the bit lines connected with the target phase change memory unit are opened, the resistance value of the target phase change memory unit is read through ohm's law, and finally the resistance value is converted into the corresponding digital logic value.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention reduces the current flowing through a single NMOS tube under the condition of ensuring the same current driving capability of a single phase change memory unit, thereby reducing the size of the NMOS tube, and compared with the traditional 1T1R, the unit area can be reduced by 15 percent, thereby reducing the cost of a phase change memory chip.
Drawings
FIG. 1 is a schematic diagram of a prior art memory cell of 1T1R structure;
FIG. 2 is a schematic diagram of a 3T2R type phase change memory cell structure according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a memory array having a plurality of 3T2R type phase change memory cell structures according to a second embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention can be made by those skilled in the art after reading the teaching of the present invention, and these equivalents also fall within the scope of the claims appended to the present application.
The first embodiment of the present invention relates to a phase change memory cell structure, as shown in fig. 2, including a first phase change device R1, a second phase change device R2, a first gate device M1, a second gate device M2, and a third gate device M3; the first end of the first phase change device R1 is connected with a first bit line BL1, and the first end of the second phase change device R2 is connected with a second bit line BL2; the second end of the first phase change device R1, the drain of the first gating device M1 and the drain of the third gating device M3 are connected together; the second end of the second phase change device R2, the drain of the second gating device M2 and the source of the third gating device M3 are connected together; the grid electrode of the first gating device M1 and the grid electrode of the second gating device M2 are connected together to be used as a word line WL of the phase change memory unit, the grid electrode of the third gating device M3 is connected with a gate line SL, and the source electrode of the first gating device M1 and the source electrode of the second gating device M2 are both grounded.
In this embodiment, the first phase change device R1 and the second phase change device R2 are identical and used for storing different data. The first gating device M1 and the second gating device M2 have the same size, and the size of the third gating device M3 can be adjusted according to actual conditions. The first gating device M1, the second gating device M2 and the third gating device M3 are all NMOS tubes.
Therefore, the three gating devices are connected with the two phase change devices to realize a unit structure of one word line, two bit lines and one gating line, and the three gating devices are driven together during writing operation, so that the current flowing through the single gating device is reduced under the condition of ensuring the same current driving capability of a single phase change memory unit, and the size of the gating device can be further reduced.
A second embodiment of the present invention relates to a phase change memory array comprising 4 × 2 phase change memory cell structures of the first embodiment, the 4 × 2 phase change memory cell structures being arranged in a matrix array. The word lines of the phase change memory unit structures in the same row are shared, the gate lines of the phase change memory unit structures in the same row are shared, the first bit lines and the second bit lines of the phase change memory unit structures in the same column are shared, and each bit line is provided with a transmission gate. As shown in fig. 3, the word lines of the phase change memory cell structures in the first row and the first column and the phase change memory cell structures in the first row and the second column are WL0 and the gate lines are SL0, and similarly, the word lines of the phase change memory cell structures in the second row and the first column and the phase change memory cell structures in the second row and the second column are WL1 and the gate lines are SL1, and so on; the phase change memory cell structures of the first row and the first column, the phase change memory cell structures of the second row and the first column, the phase change memory cell structures of the third row and the first column and the phase change memory cell structures of the fourth row and the first column are all BL0, the second bit lines are BL1, the first bit lines BL0 are provided with transmission gates BLS0, and the second bit lines BL1 are provided with transmission gates BLS1.
A third embodiment of the present invention is directed to the driving method of the phase change memory array of the second embodiment, which includes a write driving method and a read driving method.
The write driving method includes: and opening transmission gates of a word line, a gate line and a bit line which are connected with a target phase change memory unit, and applying a write programming current pulse to the bit line where the target phase change memory unit is located, wherein the write programming current is driven by the first gating device, the second gating device and the third gating device together. For example, the target phase change memory cell is the second row and the second column, and only the word line WL1, the gate line SL1, and the transfer gate BLs1 of the bit line BL1 need to be turned on. The write programming current can be driven by the first gating device, the second gating device and the third gating device together, and the current flowing through a single gating device is reduced under the condition that the same current driving capability of a single phase change memory unit is ensured, so that the size of the gating device can be reduced. Under the condition of ensuring the same current driving capability, the size of the traditional 1T1R unit structure is as follows: (0.625 μm × 0.9) × (0.4 μm × 0.9) =0.2025 μm 2 (ii) a The dimensions of the 3T2R unit structure in this embodiment are: (0.71. Mu. M.times.0.9) × (0.6. Mu. M.times.0.9)/2 = 0.17253. Mu.m 2 Therefore, compared with the conventional 1T1R, the cell area can be reduced by 15% in the present embodiment, so that the cost of the phase change memory chip can be reduced in the present embodiment.
The read driving method comprises the following steps: and starting transmission gates of word lines and bit lines connected with the target phase change memory unit, reading the resistance value of the target phase change memory unit through ohm's law, and finally converting the resistance value into a corresponding digital logic value. For example, the target phase change memory cell is the third row and the first column, and at this time, the word line WL2 and the transmission gate BLs0 of the bit line BL0 are only needed to be turned on. Therefore, in the read driving process, the gate line SL is not gated, so that the parasitic capacitance on the bit line can be reduced, and the data reading speed can be increased.
Claims (7)
1. A phase change memory unit structure is characterized by comprising a first phase change device, a second phase change device, a first gating device, a second gating device and a third gating device; the first end of the first phase change device is connected with a first bit line, and the first end of the second phase change device is connected with a second bit line; the second end of the first phase change device, the drain of the first gating device and the drain of the third gating device are connected together; the second end of the second phase change device, the drain of the second gating device and the source of the third gating device are connected together; the grid electrode of the first gating device and the grid electrode of the second gating device are connected together to be used as the word line of the phase change memory unit, the grid electrode of the third gating device is connected with a gating line, and the source electrode of the first gating device and the source electrode of the second gating device are both grounded.
2. The phase change memory cell structure of claim 1, wherein the first phase change device and the second phase change device are identical.
3. The phase change memory cell structure of claim 1, wherein the first gating device and the second gating device are identical in size.
4. The phase change memory cell structure of claim 1, wherein the first, second and third gating devices are NMOS transistors.
5. A phase change memory array comprising M x N phase change memory cell structures according to any one of claims 1 to 4, wherein the M x N phase change memory cell structures are arranged in a matrix array, word lines of the phase change memory cell structures in a same row are shared, gate lines of the phase change memory cell structures in a same row are shared, first bit lines and second bit lines of the phase change memory cell structures in a same column are shared, and a transfer gate is provided on each bit line.
6. A write driving method for applying the phase change memory array of claim 5, wherein the transmission gates of the word line, the gate line and the bit line connected to the target phase change memory cell are turned on, and a write programming current pulse is applied to the bit line where the target phase change memory cell is located, wherein the write programming current is driven by the first gating device, the second gating device and the third gating device together.
7. The method for driving a phase change memory array according to claim 5, wherein the transmission gates of the word line and the bit line connected to the target phase change memory cell are turned on, the resistance of the target phase change memory cell is read out through ohm's law, and finally converted into the corresponding digital logic value.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211143725.7A CN115631776A (en) | 2022-09-20 | 2022-09-20 | Phase change memory unit structure, phase change memory array and driving method |
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| CN202211143725.7A CN115631776A (en) | 2022-09-20 | 2022-09-20 | Phase change memory unit structure, phase change memory array and driving method |
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