CN115616817A - Display panel and electronic device - Google Patents

Display panel and electronic device Download PDF

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Publication number
CN115616817A
CN115616817A CN202211240722.5A CN202211240722A CN115616817A CN 115616817 A CN115616817 A CN 115616817A CN 202211240722 A CN202211240722 A CN 202211240722A CN 115616817 A CN115616817 A CN 115616817A
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CN
China
Prior art keywords
display panel
signal
signal line
line
panel according
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Granted
Application number
CN202211240722.5A
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Chinese (zh)
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CN115616817B (en
Inventor
刘梦慧
杨立涛
姚智益
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Suzhou China Star Optoelectronics Technology Co Ltd
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Suzhou China Star Optoelectronics Technology Co Ltd
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Priority to CN202211240722.5A priority Critical patent/CN115616817B/en
Publication of CN115616817A publication Critical patent/CN115616817A/en
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Publication of CN115616817B publication Critical patent/CN115616817B/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application provides a display panel and an electronic device, a non-display area of the display panel is provided with a plurality of first signal lines and a plurality of signal transfer lines, each first signal line is electrically connected with at least one signal transfer line, one side of the first signal line far away from a substrate is provided with a first support column and a first blocking part, the first support column covers an electric connection area of the first signal line and the signal transfer lines, the first blocking part and the first support column are arranged at intervals and are arranged along a first direction, so that the first support column and the first blocking part are arranged, when frame sealing glue is prepared, the first support column and the first blocking part can enable the outward expansion resistance of the frame sealing glue to be uniform, and then the frame sealing glue with better uniformity is formed, and the problem that the frame sealing glue with poor uniformity exists in the existing narrow-frame display is solved.

Description

Display panel and electronic device
Technical Field
The application relates to the technical field of display, in particular to a display panel and an electronic device.
Background
With the development of display technology, the narrower the frame of the lcd, and accordingly, the narrower the frame sealing adhesive (seal) for bonding the upper and lower substrates of the lcd. Due to the limitation of the precision of the frame sealing adhesive preparation process, when the frame sealing adhesive with a narrow width is prepared, the formed frame sealing adhesive has poor uniformity.
Disclosure of Invention
The application provides a display panel and an electronic device to alleviate the technical problem that frame sealing glue uniformity is poor that current narrow-frame display exists.
In order to solve the above problems, the technical solution provided by the present application is as follows:
the embodiment of the application provides a display panel, it includes the display area and is located the non-display area of display area one side, display panel still includes:
a base substrate;
the first signal lines are arranged on the substrate base plate and positioned in the non-display area, each first signal line extends along a first direction, and the first signal lines are arranged at intervals along a second direction;
the signal transfer lines are arranged on the substrate base plate and located in the non-display area, each signal transfer line extends along the second direction, the signal transfer lines are arranged at intervals along the first direction, and each first signal line is electrically connected with at least one signal transfer line;
the plurality of first supporting columns are arranged on one side, away from the substrate base plate, of the first signal line, and each first supporting column covers an electric connection area of the first signal line and one signal transfer line; and
the first signal lines are arranged on the first supporting columns, the first supporting columns are arranged on the first supporting columns, and the first signal lines are arranged on the first supporting columns in a first direction.
In the display panel provided by the embodiment of the application, an orthographic projection of the first barrier on the substrate base plate is within a range of an orthographic projection of the first signal line on the substrate base plate.
In the display panel provided by the embodiment of the application, the same first signal line corresponds to the first support column, and the spacing distance between the adjacent first support column and the first blocking part is equal to the spacing distance between the adjacent two first blocking parts.
In the display panel provided in the embodiment of the present application, in the second direction, the plurality of first support columns are arranged in a staggered manner.
In the display panel provided in the embodiment of the present application, the first blocking portion is disposed corresponding to the first signal line far away from the display area.
In the display panel provided by the embodiment of the application, the first barrier is disposed above at least one of the three outermost first signal lines, where the outermost first signal line is a side far away from the display area.
In the display panel provided in the embodiment of the present application, the first barrier and the first support pillar are disposed in the same layer.
In the display panel provided in the embodiment of the present application, the display panel further includes a second signal line located on one side of the display area away from the first signal line and a second barrier portion located on one side of the substrate base plate away from the second signal line, and the second barrier portion extends along the first direction.
In the display panel provided in the embodiment of the present application, a length of the second barrier in the first direction is greater than a length of the second signal line in the first direction.
In the display panel provided in the embodiment of the present application, the display panel further includes:
the interlayer insulating layer covers the first signal line and the substrate base plate, and the signal transfer line is arranged on the interlayer insulating layer;
the planarization layer covers the signal transfer line and the interlayer insulating layer, and is provided with a first through hole and a second through hole;
the bridging electrode is arranged on the planarization layer, electrically connected with the signal patch cord through the first via hole, electrically connected with the first signal line through the second via hole, and provided with the first supporting column.
In the display panel provided by the embodiment of the application, a protruding structure is formed on the planarization layer, and the first barrier portion is formed by the protruding structure.
In the display panel provided in the embodiment of the present application, the display panel further includes:
the interlayer insulating layer covers the first signal line and the substrate base plate, a third through hole is formed in the interlayer insulating layer, and the signal transfer line is arranged on the interlayer insulating layer and is electrically connected with the first signal line through the third through hole;
the planarization layer covers the signal transfer line and the interlayer insulating layer, and the first support column is arranged on the planarization layer and corresponds to the third through hole.
The embodiment of the present application further provides an electronic device, which includes a housing and a display panel of one of the foregoing embodiments, where the housing forms an accommodating cavity, and the display panel is assembled in the accommodating cavity
The beneficial effect of this application does: in the display panel and the electronic device provided by the application, a non-display area of the display panel is provided with a plurality of first signal lines and a plurality of signal transfer lines, each first signal line is electrically connected with at least one signal transfer line, one side of the first signal line, which is far away from a substrate, is provided with a first support column and a first blocking part, the first support column covers an electric connection area of the first signal line and the signal transfer lines, the first blocking part and the first support column are arranged at intervals and are uniformly distributed along a first direction, so that the first support column and the first blocking part are arranged, when the frame sealing glue is prepared, the first support column and the first blocking part can enable the outer expansion resistance of the frame sealing glue to be uniform, and then the frame sealing glue with better uniformity is formed, and the problem that the uniformity of the frame sealing glue is poor in the existing narrow-frame display is solved.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art, the drawings used in the embodiments or technical solutions in the prior art are briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.
Fig. 2 is a schematic top view structure diagram of a display panel according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a detailed structure of the non-display area in fig. 2.
Fig. 4 is a schematic cross-sectional view taken along the direction M-M' in fig. 3.
Fig. 5 is a schematic view of a partial film structure of a sub-pixel in a display area according to an embodiment of the present disclosure.
Fig. 6 is another cross-sectional view along the direction M-M' in fig. 3.
FIG. 7 is a schematic cross-sectional view taken along the direction N-N' in FIG. 3.
Fig. 8 is a schematic top view structure diagram of a non-display area according to an embodiment of the present disclosure.
Fig. 9 is a schematic cross-sectional structure diagram of an electronic device provided in the present application.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. Directional phrases referred to in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting. In the drawings, elements having similar structures are denoted by the same reference numerals. In the drawings, the thickness of some layers and regions are exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily illustrated, but the present application is not limited thereto.
Referring to fig. 1 to 3, fig. 1 is a schematic cross-sectional structure of a display panel provided in an embodiment of the present application, fig. 2 is a schematic top-view structure of the display panel provided in the embodiment of the present application, and fig. 3 is a schematic detail structure of a non-display region in fig. 2. The display panel 100 includes a display area AA and a non-display area NA located at one side of the display area AA, where the display area AA is used to display a picture, and the non-display area NA is used to set a sealing structure, a peripheral circuit, and the like.
Taking the display panel 100 as a liquid crystal display panel as an example, as shown in fig. 1, the display panel 100 includes a first substrate 1 and a second substrate 2 that are oppositely disposed, where the first substrate 1 is an array substrate, and the second substrate 2 is a color film substrate. A liquid crystal layer 3 is disposed between the first substrate 1 and the second substrate 2, and the liquid crystal layer 3 corresponds to the display area AA. A frame sealing adhesive 4 surrounding the liquid crystal layer 3 is further arranged between the first substrate 1 and the second substrate 2, and the frame sealing adhesive 4 is located in the non-display area NA and used for bonding the first substrate 1 and the second substrate 2 and blocking water and oxygen.
It can be understood that the first substrate 1 serves as an array substrate, the array substrate is provided with a driving circuit and a peripheral circuit, and the frame sealing adhesive 4 is disposed in the non-display area NA and covers the peripheral circuit, so as to protect the peripheral circuit and prevent the peripheral circuit from being corroded.
Specific structures of the first substrate 1 in the display area AA and the non-display area NA will be specifically described below.
Specifically, referring to fig. 2, the display panel 100 includes a substrate 10, and optionally, the substrate 10 includes a rigid substrate such as a glass substrate or a plastic substrate. In the display area AA, a plurality of data lines DL extending along a first direction X and a plurality of gate scan lines GL extending along a second direction Y are disposed on the substrate 10, and the data lines DL and the gate scan lines GL define a plurality of pixel regions in a staggered manner. The first direction X is a vertical direction, and the second direction Y is a horizontal direction, but the present application is not limited thereto.
In the non-display area NA on one side of the display area AA, a plurality of first signal lines 20 and a plurality of signal transfer lines 30 are disposed on the substrate base plate 10, and fig. 2 schematically illustrates 8 first signal lines 20. Each of the first signal lines 20 extends along a first direction X, and a plurality of the first signal lines 20 are arranged at intervals along a second direction Y. Each signal patch cord 30 extends along the second direction Y, the plurality of signal patch cords 30 are arranged at intervals along the first direction X, and each first signal cord 20 is electrically connected to at least one signal patch cord 30.
Further, the display panel 100 further includes a plurality of GOA units 40 disposed on the substrate 10, and the GOA units 40 are also located in the non-display area NA. The first signal line 20 is connected to an input end of the GOA unit 40 through the signal transfer line 30, and is configured to provide a clock signal to the GOA unit 40, where the first signal line 20 is a clock signal line. The output end of the GOA unit 40 is electrically connected to the corresponding gate scanning line GL, and is configured to provide a gate driving signal to the gate scanning line GL.
Specifically, each first signal line 20 is electrically connected to at least one signal patch cord 30, each signal patch cord 30 is connected to one GOA unit 40, and each GOA unit 40 is connected to one gate scanning line GL. The GOA unit 40 is integrated on the display panel 100, so that a gate drive Integrated Circuit (IC) is not required, and the cost of the display panel 100 can be reduced. Each of the first signal lines 20 may provide a clock signal to the plurality of GOA units 40 in a time-sharing manner, so that the number of the first signal lines 20 may be reduced, the area of the non-display area NA may be reduced, and the frame of the display panel 100 may be reduced.
In order to further reduce the frame size of the display panel 100, it is an effective way to reduce the width of the frame sealing adhesive 4. However, reducing the width of the frame sealing adhesive 4 can make the edge uniformity of the prepared frame sealing adhesive 4 worse, for example, the edge of the side of the frame sealing adhesive 4 far away from the liquid crystal layer 3 is wavy. Therefore, the frame sealing adhesive 4 cannot completely cover the peripheral circuits on the array substrate, for example, the concave part of the frame sealing adhesive 4, which is wavy, cannot effectively protect the first signal line 20, which may cause corrosion of the first signal line 20, and further cause burning or black screen of the display panel 100, thereby affecting the quality of the display panel 100.
In order to solve the problem of poor uniformity of the frame sealing adhesive 4, the inventor of the present application finds in research that, when the frame sealing adhesive 4 is prepared, the frame sealing adhesive 4 is densely and uniformly blocked, so that the outward expansion resistance of the frame sealing adhesive 4 is uniform, and the frame sealing adhesive 4 with better uniformity is formed. Therefore, the inventor of the present application proposes to provide a dense and uniform blocking structure in the non-display area NA of the display panel 100 to improve the uniformity of the frame sealing adhesive 4.
Specifically, referring to fig. 3, a plurality of first supporting pillars 50 are disposed on a side of the first signal line 20 away from the substrate base plate 10, and each of the first supporting pillars 50 covers an electrical connection area of the first signal line 20 and one of the signal transfer lines 30. The plurality of first blocking portions 60 are disposed on a side of the first signal line 20 away from the substrate base plate 10 and are uniformly arranged along the first direction X, and each of the first blocking portions 60 is disposed at an interval from the first support pillar 50. The first support column 50 and the first blocking part 60 can make the outward expansion resistance of the frame sealing glue 4 uniform, so as to form the frame sealing glue 4 with better uniformity, and solve the problem of poor uniformity of the frame sealing glue 4 in the existing narrow-frame display.
The first support column 50 corresponds to an electrical connection area between the first signal line 20 and the signal transfer line 30 to protect the electrical connection area, where the electrical connection area between the first signal line 20 and the signal transfer line 30 refers to an area where the signal transfer line 30 is connected to the first signal line 20 through a via or a bridge, for example, as shown in fig. 4, the signal transfer line 30 is electrically connected to the first signal line 20 through a bridge, and as shown in fig. 6, the signal transfer line 30 is electrically connected to the first signal line 20 through a via.
Specifically, referring to fig. 4, fig. 4 is a schematic cross-sectional view taken along the direction M-M' in fig. 3. The first signal line 20 is disposed on the substrate base plate 10, the interlayer insulating layer 11 covers the first signal line 20 and the substrate base plate 10, the signal patch cord 30 is disposed on the interlayer insulating layer 11, the planarization layer 12 covers the signal patch cord 30 and the interlayer insulating layer 11, and the planarization layer 12 is provided with a first via hole 121 and a second via hole 122. Optionally, the planarization layer 12 is an organic insulating planarization layer (PFA).
A bridging electrode 70 is disposed on the planarization layer 12, the bridging electrode 70 is electrically connected to the signal transfer line 30 through the first via 121, and the bridging electrode 70 is also electrically connected to the first signal line 20 through the second via 122. Thus, the signal patch cord 30 is electrically connected to the first signal line 20 through the bridging electrode 70, and the area where the bridging electrode 70 is located is the electrical connection area between the signal patch cord 30 and the first signal line 20. The first support pillar 50 is disposed corresponding to the bridging electrode 70 and covers the bridging electrode 70 to protect the bridging electrode 70.
Optionally, the first signal line 20, the signal transfer line 30, and the bridging electrode 70 are disposed in the same layer as part of the metal layer in the display area AA. For example, taking a sub-pixel in the display area AA as an example, referring to fig. 5, fig. 5 is a schematic view of a partial film structure of a sub-pixel in the display area provided in this embodiment of the present application. In the display area AA, an active layer 81 is disposed on the substrate 10, and a gate insulating layer 13 covers the active layer 81 and the substrate 10. The gate 82 is disposed on the gate insulating layer 13, and the first signal line 20 is disposed on the same layer as the gate 82. The interlayer insulating layer 11 covers the gate electrode 82 and the gate insulating layer 13. The source and drain electrodes 83 and 84 are disposed on the interlayer insulating layer 11 and electrically connected to the active layer 81 through vias on the interlayer insulating layer 11. The signal transfer line 30 is disposed in the same layer as the source 83 and/or the drain 84. The planarization layer 12 covers the source electrode 83, the drain electrode 84, and the interlayer insulating layer 11. The pixel electrode 71 is disposed on the planarization layer 12, and is electrically connected to the drain electrode 84 through the via hole of the planarization layer 12. The bridge electrode 70 and the pixel electrode 71 are disposed on the same layer.
The active layer 81, the gate electrode 82, the source electrode 83, and the drain electrode 84 constitute a thin film transistor of one sub-pixel. Of course, the thin film transistor structure of the present application is not limited to that illustrated in fig. 5, and for example, the thin film transistor structure of the present application may also be a bottom gate structure, a double gate structure, or the like.
In addition, it should be noted that "layer arrangement" in the present application refers to that, in a preparation process, a film layer formed of the same material is subjected to patterning processing to obtain at least two different features, and then the at least two different features are arranged in the same layer. For example, in the embodiment of the present disclosure, the gate 13 and the first signal line 20 are obtained by patterning the same conductive film layer, and then the gate 13 and the first signal line 20 are disposed on the same layer.
In another embodiment, referring to fig. 6, fig. 6 is a schematic view of another cross-sectional structure along the direction M-M' in fig. 3. Different from fig. 4, a third via hole 111 is provided on the interlayer insulating layer 11, and the signal patch cord 30 is electrically connected to the first signal line 20 through the third via hole 111. The area where the signal patch cord 30 is located and covered by the third via hole 111 and the first via hole 121 is an electrical connection area between the signal patch cord 30 and the first signal line 20, and the first support column 50 is disposed corresponding to the third via hole 111.
With continued reference to fig. 3, the signal patch cords 30 are uniformly spaced in the first direction X, and the spacing between every two adjacent signal patch cords 30 is equal, so that the electrical connection areas between the signal patch cords 30 and the first signal lines 20 are also uniformly spaced, and the first support posts 50 covering the electrical connection areas are also uniformly spaced. Specifically, in the second direction Y, the plurality of first support columns 50 are arranged in a step shape, that is, the first support columns 50 are arranged in a staggered manner in the second direction Y, and an overlapping region exists between two adjacent first support columns 50 in the second direction Y.
Meanwhile, the first signal lines 20 are uniformly spaced in the second direction Y, and the spacing between every two adjacent first signal lines 20 is equal, so that the plurality of first support columns 50 are also uniformly spaced in the second direction Y, and the spacing between every two adjacent first support columns 50 is equal.
By arranging the first support columns 50 which are uniformly distributed, the outward expansion resistance of the frame sealing glue 4 can be uniform, and the frame sealing glue 4 with better uniformity is formed. In order to further improve the uniformity of the frame sealing glue 4, the display panel 100 of the present application is further provided with the first blocking portion 60.
The first blocking portion 60 is disposed at a position where the first support column 50 is not disposed in the non-display area NA, and is uniformly arranged along the first direction X, and each of the first blocking portion 60 and the first support column 50 is disposed at an interval. Optionally, the orthographic projection of the first blocking portion 60 on the substrate base plate 10 falls within the orthographic projection range of the first signal line 20 on the substrate base plate 10, that is, the first blocking portion 60 is arranged corresponding to the first signal line 20, and the electrical connection area between the signal patch cord 30 and the first signal line 20 is also arranged corresponding to the first signal line 20, so that the first support column 50 is also arranged above the first signal line 20, and thus the first blocking portion 60 and the first support column 50 are both arranged along the extending direction of the first signal line 20, so that the first blocking portion 60 and the first support column 50 form a more dense and uniform blocking structure together, and further the outer expansion resistance of the frame sealing glue 4 is more uniform.
Specifically, corresponding to the same first signal line 20, the distance D1 between the adjacent first support column 50 and the first blocking portion 60 is equal to the distance D2 between the adjacent first blocking portion 60, so that the same first support column 50 and the first blocking portion 60 are uniformly arranged above the first signal line 20. More specifically, above the same first signal line 20, at least one first blocking portion 60 is located between two adjacent first supporting pillars 50, and as schematically shown in fig. 3, three first blocking portions 60 are disposed between every two adjacent first supporting pillars 50.
Further, in the second direction Y, the first blocking portions 60 are also arranged in a step shape, that is, the first blocking portions 60 are arranged in a staggered manner in the second direction Y. Specifically, there is an overlapping portion between two adjacent first blocking portions 60 above two adjacent first signal lines 20.
Optionally, the first blocking portion 60 is disposed corresponding to the first signal line 20 far away from the display area AA, so as to better improve the edge uniformity problem of the frame sealing adhesive 4. Specifically, the first barrier 60 is disposed above at least one of the outermost three first signal lines 20, for example, as shown in fig. 3, the first barrier 60 is disposed above the outermost two first signal lines 20, where the outermost is a side far away from the display area AA.
In one embodiment, the first barrier 60 and the first support pillar 50 are disposed in the same layer to simultaneously form the first barrier 60 and the first support pillar 50 under the same process conditions. Specifically, referring to fig. 7, fig. 7 is a schematic cross-sectional view taken along the direction N-N' in fig. 3, in which the first barrier 60 and the first support pillar 50 are both located above the first signal line 20, the first support pillar 50 is disposed on the bridging electrode 70, and the first barrier 60 is disposed on the planarization layer 12.
It is understood that, in order to ensure the uniformity of the gap between the first substrate 1 and the second substrate 2 of the display panel 100, i.e., to maintain the stability of the thickness of the liquid crystal cell, the display panel 100 further includes a plurality of pillar-shaped support Pillars (PS) between the first substrate 1 and the second substrate 2, the pillar-shaped support pillars including a Main support pillar (Main PS) and an auxiliary support pillar (Sub PS), the first support pillar 50 of the present application is made of the same material and structure as the auxiliary support pillars, and the first support pillar 50 is formed at the same time when the auxiliary support pillars are formed. The first barrier 60 and the first support pillar 50 are the same in material and structure and are formed under the same process condition to simplify the process.
In another embodiment, the first barrier 60 may also be formed by the planarization layer 12, and specifically, the planarization layer 12 is formed with a protruding structure, and the first barrier 60 is formed by the protruding structure.
In an embodiment, please refer to fig. 1 to 8, and fig. 8 is a schematic top view structure diagram of a non-display area according to an embodiment of the present disclosure. Unlike the above embodiments, the display panel 100 further includes a second signal line 21 located on a side of the first signal line 20 away from the display area AA, and a second barrier portion 61 located on a side of the second signal line 21 away from the substrate 10, where the second signal line 21 includes a common electrode line and the like. The second blocks the portion 61 and follows first direction X extends, just the second blocks the portion 61 and is in length on the first direction X is greater than the second signal line 21 is in length on the first direction X, so that the second blocks the portion 61 and forms in the needs and sets up the whole region of frame sealing glue 4, also promptly the second blocks the portion 61 and is rectangular form, as blockking the barricade of frame sealing glue 4. The edge uniformity of the frame sealing glue 4 can be further optimized by arranging the whole second blocking part 61.
In fig. 8, a portion of the second barrier section 61 above the second signal line 21 is removed to show the second signal line 21 blocked by the second barrier section 61. For other descriptions, please refer to the above embodiments, which are not repeated herein.
Fig. 1 to 9 are shown, and fig. 9 is a schematic cross-sectional structure view of the electronic device provided in the present application, where the electronic device 1000 includes a housing 200 and a display panel 100 according to one of the above embodiments, the housing 200 is formed with an accommodating cavity, and the display panel 100 is assembled in the accommodating cavity.
According to the above embodiment:
the application provides a display panel and an electronic device, a non-display area of the display panel is provided with a plurality of first signal lines and a plurality of signal transfer lines, each first signal line is electrically connected with at least one signal transfer line, one side of the first signal line, which is far away from a substrate, is provided with a first support column and a first blocking part, the first support column covers an electric connection area of the first signal line and the signal transfer lines, the first blocking part and the first support column are arranged at intervals and are uniformly distributed along a first direction, so that the first support column and the first blocking part are arranged, when the frame sealing glue is prepared, the first support column and the first blocking part can enable the outer expansion resistance of the frame sealing glue to be uniform, and then the frame sealing glue with better uniformity is formed, and the problem that the frame sealing glue with poor uniformity exists in the existing narrow-frame display is solved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
The above embodiments of the present application are described in detail, and specific examples are applied herein to explain the principles and implementations of the present application, and the description of the above embodiments is only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (13)

1. A display panel comprising a display region and a non-display region on one side of the display region, the display panel further comprising:
a substrate base plate;
the first signal lines are arranged on the substrate base plate and positioned in the non-display area, each first signal line extends along a first direction, and the first signal lines are arranged at intervals along a second direction;
the signal transfer lines are arranged on the substrate base plate and located in the non-display area, each signal transfer line extends along the second direction, the signal transfer lines are distributed at intervals along the first direction, and each first signal line is electrically connected with at least one signal transfer line;
the plurality of first supporting columns are arranged on one side, away from the substrate base plate, of the first signal line, and each first supporting column covers an electric connection area of the first signal line and one signal transfer line; and
the first signal lines are arranged on the first supporting columns, the first supporting columns are arranged on the first supporting columns, and the first signal lines are arranged on the first supporting columns in a first direction.
2. The display panel according to claim 1, wherein an orthographic projection of the first barrier on the substrate base falls within a range of an orthographic projection of the first signal line on the substrate base.
3. The display panel according to claim 2, wherein a spacing distance between adjacent first support pillars and first barrier portions is equal to a spacing distance between two adjacent first barrier portions, corresponding to the same first signal line.
4. The display panel according to claim 3, wherein the first support columns are arranged in a staggered manner in the second direction.
5. The display panel according to claim 2, wherein the first barrier portion is disposed corresponding to the first signal line away from the display region.
6. The display panel according to claim 5, wherein the first barrier is disposed above at least one of the outermost three first signal lines, wherein the outermost side is a side away from the display region.
7. The display panel according to claim 1, wherein the first barrier portion and the first support column are provided in the same layer.
8. The display panel according to claim 1, wherein the display panel further comprises a second signal line on a side of the first signal line away from the display region, and a second barrier portion on a side of the second signal line away from the substrate base, the second barrier portion extending in the first direction.
9. The display panel according to claim 8, wherein a length of the second barrier in the first direction is greater than a length of the second signal line in the first direction.
10. The display panel according to any one of claims 1 to 9, characterized by further comprising:
the interlayer insulating layer covers the first signal line and the substrate base plate, and the signal transfer line is arranged on the interlayer insulating layer;
the planarization layer covers the signal transfer line and the interlayer insulating layer, and is provided with a first through hole and a second through hole;
and the bridging electrode is arranged on the planarization layer, is electrically connected with the signal transfer line through the first via hole, is electrically connected with the first signal line through the second via hole, and is provided with the first support column.
11. The display panel according to claim 10, wherein a convex structure is formed on the planarization layer, and the first barrier is formed by the convex structure.
12. The display panel according to any one of claims 1 to 9, characterized by further comprising:
the interlayer insulating layer covers the first signal line and the substrate base plate, a third through hole is formed in the interlayer insulating layer, and the signal transfer line is arranged on the interlayer insulating layer and is electrically connected with the first signal line through the third through hole;
the planarization layer covers the signal transfer line and the interlayer insulating layer, and the first support column is arranged on the planarization layer and corresponds to the third through hole.
13. An electronic device characterized by comprising a housing formed with a housing cavity and the display panel of any one of claims 1 to 12 fitted in the housing cavity.
CN202211240722.5A 2022-10-11 2022-10-11 Display panel and electronic device Active CN115616817B (en)

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103744205A (en) * 2013-12-25 2014-04-23 合肥京东方光电科技有限公司 Color film substrate, manufacturing method thereof, display panel and liquid crystal display device
CN203811938U (en) * 2014-05-14 2014-09-03 北京京东方光电科技有限公司 Display panel and display device
US20170343842A1 (en) * 2016-05-27 2017-11-30 Xiamen Tianma Micro-Electronics Co., Ltd Liquid crystal display panel
CN110262136A (en) * 2019-04-02 2019-09-20 厦门天马微电子有限公司 Display panel and display device
WO2020006862A1 (en) * 2018-07-02 2020-01-09 深圳市华星光电半导体显示技术有限公司 Liquid crystal display panel and preparation method therefor
CN110928060A (en) * 2019-11-11 2020-03-27 厦门天马微电子有限公司 Display panel and display device
CN111090202A (en) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 Display panel and display device
WO2020191869A1 (en) * 2019-03-28 2020-10-01 武汉华星光电半导体显示技术有限公司 Display panel
CN113345915A (en) * 2021-04-29 2021-09-03 合肥鑫晟光电科技有限公司 Array substrate, manufacturing method thereof, display panel and display device
CN113419374A (en) * 2021-06-15 2021-09-21 Tcl华星光电技术有限公司 Display panel and display device
CN113759616A (en) * 2021-09-14 2021-12-07 京东方科技集团股份有限公司 Display panel and display device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103744205A (en) * 2013-12-25 2014-04-23 合肥京东方光电科技有限公司 Color film substrate, manufacturing method thereof, display panel and liquid crystal display device
CN203811938U (en) * 2014-05-14 2014-09-03 北京京东方光电科技有限公司 Display panel and display device
US20170343842A1 (en) * 2016-05-27 2017-11-30 Xiamen Tianma Micro-Electronics Co., Ltd Liquid crystal display panel
WO2020006862A1 (en) * 2018-07-02 2020-01-09 深圳市华星光电半导体显示技术有限公司 Liquid crystal display panel and preparation method therefor
WO2020191869A1 (en) * 2019-03-28 2020-10-01 武汉华星光电半导体显示技术有限公司 Display panel
CN110262136A (en) * 2019-04-02 2019-09-20 厦门天马微电子有限公司 Display panel and display device
CN110928060A (en) * 2019-11-11 2020-03-27 厦门天马微电子有限公司 Display panel and display device
CN111090202A (en) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 Display panel and display device
CN113345915A (en) * 2021-04-29 2021-09-03 合肥鑫晟光电科技有限公司 Array substrate, manufacturing method thereof, display panel and display device
CN113419374A (en) * 2021-06-15 2021-09-21 Tcl华星光电技术有限公司 Display panel and display device
CN113759616A (en) * 2021-09-14 2021-12-07 京东方科技集团股份有限公司 Display panel and display device

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