CN115608654A

CN115608654A - Test system for semiconductor circuit and test method for semiconductor circuit

Info

Publication number: CN115608654A
Application number: CN202211021284.3A
Authority: CN
Inventors: 冯宇翔; 左安超
Original assignee: Guangdong Huixin Semiconductor Co Ltd
Current assignee: Guangdong Huixin Semiconductor Co Ltd
Priority date: 2021-08-26
Filing date: 2022-08-24
Publication date: 2023-01-17
Anticipated expiration: 2042-08-24
Also published as: CN115608654B; CN113770066A

Abstract

The invention relates to a test system of a semiconductor circuit and a test method of the semiconductor circuit, which carry out IO port test on the semiconductor circuit to be tested by connecting a signal generating device with a first type input pin of the semiconductor circuit to be tested and connecting a detection control device with a first type output pin of the semiconductor circuit to be tested; and after the IO test data of the semiconductor circuit to be tested meet the preset test conditions, connecting the signal generating equipment with the second type input pin of the semiconductor circuit to be tested, and connecting the detection control equipment with the second type output pin of the semiconductor circuit to be tested to test the function of the semiconductor circuit to be tested. Firstly, performing IO port test, namely preliminarily screening out an abnormal sample by adopting low-current and low-voltage test, and keeping the original failure appearance of the sample; and then, performing functional port test, namely testing the semiconductor circuit by adopting large current and high voltage, so that secondary damage to an abnormal sample during functional test can be avoided, and the situation that the abnormal sample cannot be intercepted after the functional test process is damaged is prevented.

Description

Test system for semiconductor circuit and test method for semiconductor circuit

Technical Field

The invention relates to a test system and a test method of a semiconductor circuit, belonging to the technical field of semiconductor circuit application.

Background

A semiconductor circuit is a power driven type product that combines power electronics with integrated circuit technology. The semiconductor circuit integrates a power switching device and a high-voltage driving circuit, and incorporates a failure detection circuit for detecting an overvoltage, an overcurrent, an overheat, and the like. The semiconductor circuit receives the control signal of the MCU to drive the subsequent circuit to work on one hand, and sends the state detection signal of the system back to the MCU for processing on the other hand. Compared with the traditional discrete scheme, the semiconductor circuit gains a bigger and bigger market with the advantages of high integration degree, high reliability and the like, is particularly suitable for frequency converters of driving motors and various inverter power supplies, and is an ideal power electronic device for variable-frequency speed regulation, metallurgical machinery, electric traction, servo drive and variable-frequency household appliances. Most of these applications are subject to harsh environmental conditions, particularly high temperatures, humidity, high voltages, which are critical to the quality and reliability of semiconductor circuits. In addition, since the semiconductor circuit plays a key role in the application, the semiconductor circuit needs to be tested before being shipped from a factory, and only the semiconductor circuit which passes the test can be qualified.

In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: in the current test process of the semiconductor circuit, the secondary damage of the semiconductor circuit is easily caused, and the damaged semiconductor circuit can not be intercepted in the function test process.

Disclosure of Invention

Therefore, it is necessary to solve the problems that the conventional semiconductor circuit is easily damaged secondarily during the test process, and cannot be intercepted after the function test process is damaged. A test system of a semiconductor circuit and a test method of a semiconductor circuit are provided.

Specifically, the present invention discloses a test system for a semiconductor circuit, comprising:

the signal generating device is used for being connected with a first class input pin of the semiconductor circuit to be tested and is configured to transmit a first IO test signal to the semiconductor circuit to be tested so that the semiconductor circuit to be tested generates a first feedback signal according to the first IO test signal;

the detection control equipment is used for connecting a first class output pin corresponding to the first class input pin of the semiconductor circuit to be detected, is configured to acquire a first feedback signal generated by the semiconductor circuit to be detected, processes the first feedback signal, and obtains first IO test data of the semiconductor circuit to be detected according to a processing result;

after the IO test data meet the preset test condition, the signal generating device is further configured to connect a second type input pin of the semiconductor circuit to be tested, and transmit a functional test signal to the semiconductor circuit to be tested, so that the semiconductor circuit to be tested generates a second feedback signal according to the functional test signal; the detection control equipment is also used for connecting a second type output pin corresponding to the second type input pin of the semiconductor circuit to be detected, and is configured to acquire a second feedback signal generated by the semiconductor circuit to be detected, process the second feedback signal, and obtain functional test data of the semiconductor circuit to be detected according to a processing result.

Optionally, after the functional test data meets the preset test condition, the signal generating device is further configured to connect a first class input pin of the semiconductor circuit to be tested, and configured to transmit a second IO test signal to the semiconductor circuit to be tested, so that the semiconductor circuit to be tested generates a third feedback signal according to the second IO test signal;

the detection control equipment is also used for connecting a first class output pin corresponding to the first class input pin of the semiconductor circuit to be detected, and is configured to acquire a third feedback signal generated by the semiconductor circuit to be detected, process the third feedback signal, and obtain second IO test data of the semiconductor circuit to be detected according to a processing result.

Optionally, the detection control device includes a controller, and a detection module connected to the controller;

the detection module is used for sequentially receiving the first feedback signal, the second feedback signal and the third feedback signal and sequentially transmitting the received first feedback signal, the received second feedback signal and the received third feedback signal to the controller; the controller is used for processing the received first feedback signal, the second feedback signal and the third feedback signal in sequence to respectively obtain first IO test data, function test data and second IO test data;

the controller is further used for confirming that the semiconductor circuit to be tested is a qualified product when the first IO test data, the function test data and the second IO test data respectively meet corresponding preset test conditions.

Optionally, the controller is further configured to connect to a signal generating device, and configured to transmit a signal switching instruction to the signal generating device, so that the signal generating device switches the current output signal according to the signal switching instruction; the current output signal is a first IO test signal, a functional test signal, or a second IO test signal.

Optionally, the first type of input pin includes a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an itrep pin, a VDD pin, a VSS pin, a VDD pin, or a VSS pin; the first type of output pins comprise a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an ITRIP pin, a VDD pin, a VSS pin, a VDD pin or a VSS pin;

the second type of input pins comprise a HIN1 pin, a HIN2 pin, a HIN3 pin, an LIN1 pin, an LIN2 pin, an LIN3 pin or a PFCI pin; the second type of output pin includes a HO1 pin, a HO2 pin, a HO3 pin, an LO1 pin, an LO2 pin, an LO3 pin, or a PFCOUT pin.

The invention also discloses a method for testing the semiconductor circuit, which comprises the following steps:

connecting the signal generating equipment with a first class input pin of the semiconductor circuit to be detected, and connecting the detection control equipment with a first class output pin of the semiconductor circuit to be detected, wherein the first class output pin corresponds to the first class input pin;

transmitting a first IO test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a first feedback signal according to the first IO test signal; acquiring a first feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the first feedback signal, and obtaining first IO test data of the semiconductor circuit to be tested according to a processing result;

after the IO test data meet the preset test conditions, connecting the signal generating equipment with a second type input pin of the semiconductor circuit to be tested, and connecting the detection control equipment with a second type output pin of the semiconductor circuit to be tested, wherein the second type output pin corresponds to the second type input pin;

transmitting a functional test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a second feedback signal according to the functional test signal; and acquiring a second feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the second feedback signal, and obtaining the functional test data of the semiconductor circuit to be tested according to the processing result.

Optionally, the step of obtaining the functional test data of the semiconductor circuit under test further comprises:

when the functional test data meet the preset test conditions, connecting the signal generating equipment with a first class input pin of the semiconductor circuit to be tested, and connecting the detection control equipment with a first class output pin, corresponding to the first class input pin, of the semiconductor circuit to be tested;

transmitting a second IO test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a third feedback signal according to the second IO test signal; and acquiring a third feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the third feedback signal, and obtaining second IO test data of the semiconductor circuit to be tested according to a processing result.

Optionally, the step of obtaining the second IO test data of the semiconductor circuit to be tested further includes:

and comparing the second IO test data with the corresponding preset test conditions through the detection control equipment, and confirming that the semiconductor circuit to be tested is a qualified product when the second IO test data meets the corresponding preset test conditions according to the comparison result.

Optionally, the step that the IO test data satisfies the preset test condition includes:

sequentially applying a preset first voltage signal between two adjacent first-class input pins through signal generation equipment, and judging the open-short circuit state of the first-class input pins according to the obtained corresponding first feedback signal through detection control equipment;

applying preset first current signals to corresponding first-class input pins of a driving chip contained in the semiconductor device to be tested in sequence through signal generation equipment, and obtaining diode characteristic parameters of the first-class input pins corresponding to the driving chip according to the obtained corresponding first feedback signals through detection control equipment;

and sequentially applying a preset level signal to the first type of input pins of the bridge arms contained in the corresponding semiconductor equipment to be tested through the signal generating equipment, and judging the on-off state of the corresponding bridge arms according to the obtained corresponding first feedback signals through the detection control equipment.

Optionally, the step of obtaining functional test data of the semiconductor circuit to be tested comprises:

sequentially applying a preset level signal to a second type of input pins of a bridge arm contained in the corresponding semiconductor device to be tested through the signal generating device, and obtaining pressure drop data of two ends of the corresponding bridge arm according to the obtained corresponding second feedback signal through the detection control device;

and sequentially applying preset pulse signals to second-class input pins of the bridge arms contained in the corresponding semiconductor equipment to be tested through the signal generating equipment, and obtaining dynamic parameters of the corresponding bridge arms according to the obtained corresponding second feedback signals through the detection control equipment.

One of the above technical solutions has the following advantages and beneficial effects:

in each embodiment of the above-mentioned test system for a semiconductor circuit, the signal generating device is connected to the first type input pin of the semiconductor circuit to be tested, and the detection control device is connected to the first type output pin of the semiconductor circuit to be tested, so that the signal generating device can transmit the first IO test signal to the semiconductor circuit to be tested, so that the semiconductor circuit to be tested generates the first feedback signal according to the first IO test signal; the detection control equipment can acquire a first feedback signal generated by the semiconductor circuit to be tested, process the first feedback signal, obtain first IO test data of the semiconductor circuit to be tested according to a processing result, and further process the first IO test data to realize IO port test of the semiconductor circuit to be tested; after IO test data of the semiconductor circuit to be tested meet preset test conditions, connecting the signal generating equipment with a second type input pin of the semiconductor circuit to be tested, connecting the detection control equipment with a second type output pin of the semiconductor circuit to be tested, wherein the second type output pin corresponds to the second type input pin, and transmitting a function test signal to the semiconductor circuit to be tested by the signal generating equipment so that the semiconductor circuit to be tested generates a second feedback signal according to the function test signal; the detection control equipment acquires a second feedback signal generated by the semiconductor circuit to be tested, processes the second feedback signal, obtains functional test data of the semiconductor circuit to be tested according to a processing result, and can process the functional test data to realize functional test of the semiconductor circuit to be tested. The test system of the semiconductor circuit firstly performs IO port test, namely, firstly, small-current and low-voltage test is adopted to preliminarily screen out abnormal samples, and the original failure appearance of the samples is kept; and then, performing functional port test, namely further testing the semiconductor circuit to be tested by adopting large current and high voltage, so that secondary damage to the abnormal sample during functional test can be avoided, and the situation that the semiconductor circuit to be tested cannot be intercepted after being damaged in the functional test process is prevented.

Drawings

Fig. 1 is a schematic diagram of a conventional semiconductor circuit.

Fig. 2 is a circuit diagram of a semiconductor circuit according to an embodiment of the invention.

FIG. 3 is a first block diagram of a test system for semiconductor circuits according to an embodiment of the present invention.

FIG. 4 is a second block diagram of a testing system for semiconductor circuits according to an embodiment of the present invention.

FIG. 5 is a first flowchart of a method for testing a semiconductor circuit according to an embodiment of the invention.

FIG. 6 is a second flowchart of a method for testing a semiconductor circuit according to an embodiment of the invention.

Fig. 7 is a third flowchart of a testing method of a semiconductor circuit according to an embodiment of the invention.

Reference numerals:

the circuit board 10, the insulating layer 20, the circuit layer 30, the circuit wiring layer 31, the driving chip 32, the inverter assembly 33, the pin 40, the sealing body 50, the first triode transistor 100, the second triode transistor 101, the third triode transistor 102, the fourth triode transistor 103, the fifth triode transistor 104, the sixth triode transistor 105, the switch tube 112, the third bootstrap diode 202, the second bootstrap diode 203, the first bootstrap diode 204, the diode 213, the first driving resistor 300, the second driving resistor 301, the third driving resistor 302, the fourth driving resistor 303, the fifth driving resistor 304, the sixth driving resistor 305, the semiconductor circuit 01 to be tested, the signal generating device 03, the detection control device 05, the controller 51, and the detection module 53.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic view illustrating a structure of a semiconductor circuit to be tested according to an embodiment of the present disclosure, where fig. 1 is a schematic view illustrating the structure of the semiconductor circuit to be tested according to the present disclosure. The semiconductor circuit to be tested may include a circuit substrate 10, a circuit layer 30, a plurality of pins 40, and a sealing body 50; an insulating layer 20 is provided on the circuit board 10; the circuit layer 30 is disposed on the insulating layer 20; the first ends of the plurality of pins 40 are electrically connected with the circuit layer 30 respectively; the sealing body 50 at least wraps one surface of the circuit substrate 10 on which the circuit layer 30 is disposed, and the second end of each lead 40 is exposed from the sealing body 50; the circuit layer 30 includes a circuit wiring layer 31, a driving chip 32, a PFC module (not shown) and an inverter component 33 are disposed on the circuit wiring layer 31; the inverter assembly 33 is connected to the driving chip 32.

As shown in fig. 2, the inverter assembly includes 3 sets of inverter modules, each set of inverter modules includes two three-pole transistors, wherein the first three-pole transistor 100 and the fourth three-pole transistor 103 form a set, the second three-pole transistor 101 and the fifth three-pole transistor 104 form a set, and the third three-pole transistor 102 and the sixth three-pole transistor 105 form a set. Each group of two tripolar transistors is divided into an upper bridge arm and a lower bridge arm, wherein the first tripolar transistor 100 is the upper bridge arm, and the fourth tripolar transistor 103 is the lower bridge arm; the second three-pole transistor 101 is an upper arm, and the fifth three-pole transistor 104 is a lower arm; third triode transistor 102 is the upper leg and sixth triode transistor 105 is the lower leg. The drain of the first triode transistor 100 of the upper bridge arm is connected with a pin P of a high-voltage input end of the semiconductor circuit to be tested, the source of the first triode transistor 100 of the upper bridge arm is connected with the drain of the fourth triode transistor 103 of the lower bridge arm, the source of the fourth triode transistor 103 of the lower bridge arm is connected with a pin U of the semiconductor circuit to be tested, the gate of the first triode transistor 100 is connected with a port HO1 of the driving chip through a first driving resistor 300, and the gate of the fourth triode transistor 103 is connected with a port LO1 of the driving chip through a fourth driving resistor 303. The drain of the second triode transistor 101 of the upper bridge arm is connected with a pin P of a high-voltage input end of the semiconductor circuit to be tested, the source of the second triode transistor 101 of the upper bridge arm is connected with the drain of the fifth triode transistor 104 of the lower bridge arm, the source of the fifth triode transistor 104 of the lower bridge arm is connected with a pin V of the semiconductor circuit to be tested, the gate of the second triode transistor 101 is connected with the HO2 port of the driving chip through a second driving resistor 301, and the gate of the fifth triode transistor 104 is connected with the LO2 port of the driving chip through a fifth driving resistor 304. The drain of the third triode transistor 102 of the upper bridge arm is connected with a pin P of a high-voltage input end of the semiconductor circuit to be tested, the source of the third triode transistor 102 of the upper bridge arm is connected with the drain of the sixth triode transistor 105 of the lower bridge arm, the source of the sixth triode transistor 105 of the lower bridge arm is connected with a pin W of the semiconductor circuit to be tested, the gate of the third triode transistor 102 is connected with an HO3 port of the driving chip through a third driving resistor 302, and the gate of the sixth triode transistor 105 is connected with an LO3 port of the driving chip through a sixth driving resistor 305.

The driving chip comprises a VSS port, a high-side output port and a low-side output port, wherein the high-side output port is provided with an HO1 port, an HO2 port and an HO3 port, and the low-side output port is provided with an LO1 port, an LO2 port, an LO3 port and a PFCOUT port. The driving chip further comprises a HIN1 port, a HIN2 port, a HIN3 port, a LIN1 port, a LIN2 port, a LIN3 port, a PFCIN port, a FAULT port, an ITRIP port, a RCIN port, a VSS port, a VDD port, a VB1 port, a VB2 port, a VB3 port, a VS1 port, a VS2 port and a VS3 port. The VB1 port is connected to the VDD port through the first bootstrap diode 204; the VB2 port is connected with the VDD port through a second bootstrap diode 203; the VB3 port is connected with the VDD port through a third bootstrap diode 202; the PFCOUT port is connected to the switching tube 112, the drain of the switching tube is connected to the P-terminal through the diode 213, and the source is connected to the-VCC pin of the semiconductor circuit to be tested.

It should be noted that, as shown in fig. 2, the VDD pin of the semiconductor circuit to be tested is connected to the power circuit inside the driver chip through the VDD port of the driver chip, so as to provide the operating power for the driver chip. A HIN1 pin of a semiconductor circuit to be tested is connected with a first high-side driving circuit in a driving chip through an HIN1 port of the driving chip, and outputs a control signal through an HO1 port of the driving chip so as to determine the on-off state of a first triode transistor 100; a HIN2 pin of the semiconductor circuit to be tested is connected with a second high-side driving circuit in the driving chip through an HIN2 port of the driving chip, and outputs a control signal through an HO2 port of the driving chip so as to determine the on-off state of the second triode transistor 101; a HIN3 pin of the semiconductor circuit to be tested is connected with a third high-side driving circuit in the driving chip through an HIN3 port of the driving chip, and outputs a control signal through an HO3 port of the driving chip so as to determine the on-off state of the third triode transistor 102; a LIN1 pin of the semiconductor circuit to be tested is connected with a first low-side drive circuit in the drive chip through a LIN1 port of the drive chip, and outputs a control signal through an LO1 port of the drive chip so as to determine the on-off of the fourth triode transistor 103; the LIN2 pin of the semiconductor circuit to be tested is connected with a second low-side drive circuit in the drive chip through the LIN2 port of the drive chip, and outputs a control signal through the LO2 port of the drive chip so as to determine the on-off of the fifth triode transistor 104; the LIN3 pin of the semiconductor circuit to be tested is connected with a third low-side drive circuit in the drive chip through the LIN3 port of the drive chip, and outputs a control signal through the LO3 port of the drive chip so as to determine the on-off of the sixth triode transistor 105. The PFCIN pin of the semiconductor circuit to be tested is connected to the PFCOUT driving circuit inside the driving chip through the PFCOUT port of the driving chip, and outputs a control signal through the PFCOUT port of the driving chip to determine the on/off of the switching tube 112. The semiconductor circuit to be tested receives input signals of 0V or 5V through a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCOUT1 pin, a PFCOUT2 pin, a PFCOUT3 pin and a PFCOUT4 pin. Of course, the input signal with other voltage amplitudes may be received according to actual needs, and the selection is specifically performed according to the actual device connected to the circuit. The triode transistor is one of an IGBT transistor, a reverse conducting IGBT transistor or a MOSFET transistor.

In one embodiment, as shown in fig. 3, the present invention proposes a test system of a semiconductor circuit, which includes a signal generation device 03 and a detection control device 05. The signal generating device 03 is used for connecting a first input pin of the semiconductor circuit 01 to be tested, and is configured to transmit a first IO test signal to the semiconductor circuit 01 to be tested, so that the semiconductor circuit 01 to be tested generates a first feedback signal according to the first IO test signal; the detection control device 05 is configured to connect a first type output pin of the semiconductor circuit 01 to be tested, which corresponds to the first type input pin, and is configured to acquire a first feedback signal generated by the semiconductor circuit 01 to be tested, process the first feedback signal, and obtain first IO test data of the semiconductor circuit 01 to be tested according to a processing result. After the IO test data satisfy the preset test condition, the signal generating device 03 is further configured to connect a second type input pin of the semiconductor circuit 01 to be tested, and transmit a functional test signal to the semiconductor circuit 01 to be tested, so that the semiconductor circuit 01 to be tested generates a second feedback signal according to the functional test signal; the detection control device 05 is further configured to connect a second type output pin of the semiconductor circuit 01 to be tested, which corresponds to the second type input pin, and configured to obtain a second feedback signal generated by the semiconductor circuit 01 to be tested, process the second feedback signal, and obtain functional test data of the semiconductor circuit 01 to be tested according to a processing result.

The signal generating device 03 is configured to provide a required test signal to the semiconductor circuit 01 to be tested, for example, the signal generating device 03 may provide a first IO test signal or a second IO test signal to the semiconductor circuit 01 to be tested. In an example, the signal generating device 03 is configured to provide a test voltage signal or a test current signal to the semiconductor circuit to be tested, for example, when the semiconductor circuit to be tested 01 is subjected to an IO port test, the signal generating device 03 may transmit a parameter voltage signal to the corresponding IO pin of the semiconductor circuit to be tested 01, and detect a feedback signal of the corresponding IO pin of the semiconductor circuit to be tested 01 through the detection control device 05, so as to determine an on-off state of the corresponding IO pin of the semiconductor circuit. Further, after the IO test of the semiconductor circuit 01 to be tested passes, the semiconductor circuit 01 to be tested is subjected to a functional test, that is, the signal generating device 03 may transmit a second IO test signal to the corresponding pin of the semiconductor circuit 01 to be tested, and the second feedback signal of the corresponding pin of the semiconductor circuit 01 to be tested is acquired and processed by the detection control device 05, so as to implement the functional test of the semiconductor circuit 01 to be tested.

The detection control device 05 can be used for acquiring parameters of the semiconductor circuit 01 to be tested in the test process, processing the acquired parameters, and judging whether the test parameters of the semiconductor circuit 01 to be tested meet preset conditions, so as to realize IO test and functional test of the semiconductor circuit 01 to be tested. For example, when the semiconductor circuit 01 to be tested is subjected to the IO test, the detection control device 05 may receive the first feedback signal of the semiconductor circuit 01 to be tested, process the first feedback signal to obtain first IO test data, and further determine whether the IO test data satisfies a preset test condition, thereby implementing the IO test on the semiconductor circuit 01 to be tested. Further, after the semiconductor circuit 01 to be tested passes the IO test, the detection control device 05 may receive a second feedback signal of the semiconductor circuit 01 to be tested, process the second feedback signal to obtain functional test data, and further determine whether the functional test data satisfies a preset test condition, thereby implementing the functional test on the semiconductor circuit 01 to be tested.

In an example, when the semiconductor circuit 01 to be tested is tested, the signal generating device 03 is first connected to the first type input pin corresponding to the semiconductor circuit 01 to be tested, and transmits a first feedback signal to the first type input pin corresponding to the semiconductor circuit 01 to be tested, so that the detection control device 05 detects a first feedback signal of the semiconductor circuit 01 to be tested in an IO test state, and processes the first feedback signal, thereby obtaining first IO test data. The detection control equipment 05 judges whether the first IO test data conforms to an expected set value of a semiconductor circuit parameter of a first feedback signal given by the corresponding signal generation equipment 03, if the detection control equipment 05 detects that the obtained first IO test data conforms to the expected set value, the semiconductor circuit 01 to be tested is judged to be qualified in the IO test, and the next step of functional test is carried out; if not, the signal generating device 03 terminates the test signal output and the test terminates.

When the function test is performed on the semiconductor circuit 01 to be tested, the signal generating device 03 is connected to the second type input pin corresponding to the semiconductor circuit 01 to be tested, and transmits a second feedback signal to the second type input pin corresponding to the semiconductor circuit 01 to be tested, so that the detection control device 05 detects a second feedback signal of the semiconductor circuit 01 to be tested in a function test state, and processes the second feedback signal to obtain function test data. The detection control device 05 determines whether the functional test data conforms to an expected set value of a parameter of the semiconductor circuit corresponding to the second feedback signal given by the signal generation device 03, and if the detection control device 05 detects that the obtained functional test data conforms to the expected set value, the semiconductor circuit 01 to be tested is determined to be qualified in functional test.

In a specific embodiment, after the functional test data meets the preset test condition, the signal generating device 03 is further configured to connect the first type input pin of the semiconductor circuit 01 to be tested, and transmit the second IO test signal to the semiconductor circuit 01 to be tested, so that the semiconductor circuit 01 to be tested generates the third feedback signal according to the second IO test signal. The detection control device 05 is further configured to connect a first class output pin of the semiconductor circuit 01 to be tested, which corresponds to the first class input pin, and to obtain a third feedback signal generated by the semiconductor circuit 01 to be tested, process the third feedback signal, and obtain second IO test data of the semiconductor circuit 01 to be tested according to a processing result.

After the IO test and the functional test are passed in sequence, the semiconductor circuit 01 to be tested performs a further IO test. Specifically, the signal generating device 03 is connected to the first input pin corresponding to the semiconductor circuit 01 to be tested, and transmits the third feedback signal to the first input pin corresponding to the semiconductor circuit 01 to be tested, so that the detection control device 05 detects the third feedback signal of the semiconductor circuit 01 to be tested in the IO test state, and processes the third feedback signal, thereby obtaining second IO test data. The detection control device 05 judges whether the second IO test data conforms to an expected set value of a parameter of the semiconductor circuit corresponding to the third feedback signal given by the signal generation device 03, if the detection control device 05 detects that the obtained second IO test data conforms to the expected set value, the IO test of the semiconductor circuit 01 to be tested is judged to be qualified, and then the final test of the semiconductor circuit 01 to be tested is judged to be qualified; if not, the signal generating device 03 terminates the test signal output and the test terminates. The method comprises the steps of sequentially carrying out IO test, function test and IO test on a semiconductor circuit 01 to be tested, namely, initially screening out an abnormal sample by adopting low-current and low-voltage tests, and keeping the original shape of the sample failure; then, performing a functional port test, namely further testing the semiconductor circuit 01 to be tested by adopting large current and high voltage; and finally, the abnormal sample is further screened out by adopting low-current and low-voltage tests, so that the secondary damage of the abnormal sample during the functional test can be avoided, the situation that the semiconductor circuit 01 to be tested cannot be intercepted after being damaged in the functional test process is prevented, and the test accuracy of the semiconductor circuit is improved.

In one example, as shown in fig. 4, the detection control device 05 includes a controller 51, and a detection module 53 connected to the controller 51. The detection module 53 is configured to receive the first feedback signal, the second feedback signal, and the third feedback signal in sequence, and transmit the received first feedback signal, the received second feedback signal, and the received third feedback signal to the controller 51 in sequence; the controller 51 is configured to sequentially process the received first feedback signal, second feedback signal, and third feedback signal to obtain first IO test data, functional test data, and second IO test data, respectively. The controller 51 is further configured to compare the first IO test data and the second IO test data when the first IO test data, the functional test data, and the second IO test data respectively satisfy corresponding preset test conditions, to calculate an offset value of the first IO test data and the second IO test data through the detection control device 05, and to confirm that the semiconductor circuit 01 to be tested is a qualified product when the offset value satisfies a preset range.

When the semiconductor circuit 01 to be tested is tested, the first feedback signal of the semiconductor circuit 01 to be tested is received through the detection module 53 of the detection control device 05, the received first feedback signal is transmitted to the controller 51, and then the controller 51 processes the first feedback signal to obtain first IO test data. The controller 51 judges whether the first IO test data conforms to a corresponding parameter expected set value, if the controller 51 detects that the obtained first IO test data conforms to the expected set value, the IO test of the semiconductor circuit 01 to be tested is judged to be qualified, and the next step of function test is performed; if not, the signal generating device 03 terminates the output of the test signal, terminates the test, and determines that the semiconductor circuit is defective. When the function test is performed on the semiconductor circuit 01 to be tested, the detection module 53 of the detection control device 05 receives the second feedback signal of the semiconductor circuit 01 to be tested, and transmits the received second feedback signal to the controller 51, so that the controller 51 processes the second feedback signal to obtain the function test data. The controller 51 judges whether the functional test data conforms to the expected set value of the corresponding parameter, if the controller 51 detects that the obtained functional test data conforms to the expected set value, the functional test of the semiconductor circuit to be tested 01 is qualified; if not, the signal generating device 03 terminates the output of the test signal, terminates the test, and determines that the semiconductor circuit is defective. After the semiconductor circuit 01 to be tested passes the IO test and the functional test in sequence, a further IO test is performed. The detection module 53 of the detection control device 05 receives the third feedback signal of the semiconductor circuit 01 to be tested, and transmits the received third feedback signal to the controller 51, so that the controller 51 processes the third feedback signal to obtain the second IO test data. The controller 51 judges whether the second IO test data conforms to a corresponding parameter expected set value, if the controller 51 detects that the obtained second IO test data conforms to the expected set value, the IO test of the semiconductor circuit 01 to be tested is judged to be qualified, and then the final test of the semiconductor circuit 01 to be tested is judged to be qualified; if not, the signal generating device 03 terminates the output of the test signal, terminates the test, and determines that the semiconductor circuit is defective. The detection module 53 sequentially acquires a first feedback signal, a second feedback signal and a third feedback signal, and the controller 51 sequentially processes the first feedback signal, the second feedback signal and the third feedback signal, namely, the abnormal sample is preliminarily screened out by adopting a low-current and low-voltage test, and the original failure morphology of the sample is reserved; then, performing a functional port test, namely further testing the semiconductor circuit 01 to be tested by adopting large current and high voltage; and finally, further screening out abnormal samples by adopting low current and low voltage tests, so that secondary damage to the abnormal samples during the functional test can be avoided, the semiconductor circuit 01 to be tested can not be intercepted after the damage of the functional test process, and the abnormal samples are finally determined to be qualified products only when the comparison deviation meets the preset value through comparing the IO test data of the front time and the back time, so that the samples found to have parameter deterioration trend in the test process can be further rejected, and the test accuracy of the semiconductor circuit is further improved.

In one embodiment, as shown in fig. 4, the controller 51 is further configured to connect the signal generating device 03, and configured to transmit a signal switching instruction to the signal generating device 03, so that the signal generating device 03 switches the current output signal according to the signal switching instruction; the current output signal is a first IO test signal, a functional test signal, or a second IO test signal.

The processing chip included in the controller 51 may be a DSP processing chip or a single chip.

Specifically, based on the controller 51 being connected to the signal generating device 03, after the semiconductor circuit 01 to be tested passes the initial IO test, the signal switching instruction may be transmitted to the signal generating device 03 through the controller 51, and the signal generating device 03 may switch the currently output first IO test signal into the functional test signal according to the signal switching instruction, so as to perform the functional test on the semiconductor circuit 01 to be tested. After the semiconductor circuit 01 to be tested passes the function test, the signal switching instruction can be transmitted to the signal generating device 03 through the controller 51, and the signal generating device 03 can switch the currently output function test signal into the second IO test signal according to the signal switching instruction so as to perform the IO test on the semiconductor circuit 01 to be tested again, thereby realizing the complete test on the semiconductor circuit.

In one example, based on the communication connection between the controller 51 and the signal generating device 03, the controller 51 detects a parameter of the semiconductor circuit 01 under test in a test state, and determines whether the parameter meets an expected set value of the semiconductor circuit 01 under test corresponding to a current output signal output by the signal generating device 03, if the parameter obtained by the controller 51 meets the expected set value, the semiconductor circuit under test is qualified, the next test is performed, and if the parameter does not meet the expected set value, the signal generating device 03 terminates the output of the test signal, and the test is terminated.

In one example, as shown in fig. 2 and 4, the first type input pins include a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an ITRIP pin, a VDD pin, a VSS pin, a VDD pin, or a VSS pin; the first type of output pin comprises a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an ITRIP pin, a VDD pin, a VSS pin, a VDD pin or a VSS pin. The second type of input pins comprise a HIN1 pin, a HIN2 pin, a HIN3 pin, an LIN1 pin, an LIN2 pin, an LIN3 pin or a PFCI pin; the second type of output pin includes a HO1 pin, a HO2 pin, a HO3 pin, an LO1 pin, an LO2 pin, an LO3 pin, or a PFCOUT pin.

Specifically, the specific test procedure of the semiconductor circuit 01 to be tested is as follows: the first step is to test the parameters of the IO port 01 of the semiconductor circuit to be tested, including but not limited to the following pin pins: a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an ITRIP pin, a VDD pin, a VSS pin, a VDD pin and a VSS pin; firstly, applying 0.2-1V voltage between every two pins to detect current for judging whether the pins have open circuit and short circuit abnormal states, and the method can be used for detecting the open circuit and short circuit states of a certain pin to all the pins; then, for the driving chip pins including but not limited to pin HIN1 pin, HIN2 pin, HIN3 pin, LIN1 pin, LIN2 pin, LIN3 pin, PFCIN pin, FAULT pin and ITRIP pin, diode characteristics between VSS pin and VDD pin are respectively matched (10 uA-1mA current is filled between the two pins); and finally, testing the on-off test of the IO ports, injecting high and low levels into each logic IO port, and detecting the on and off actions of corresponding bridge arms. Such as: and when the HIN1 pin inputs a high level and is connected with the corresponding U-phase upper bridge arm, the HIN2 pin, the HIN3 pin, the LIN1 pin, the LIN2 pin, the LIN3 pin and the PFCIN pin are connected with the corresponding U-phase upper bridge arm when the HIN1 pin inputs a low level. The small-current and low-voltage tests are used for primarily screening out abnormal samples, the original failure appearance of the samples is kept, and secondary damage to the abnormal samples during large-current and high-voltage condition tests adopted in the functional tests is avoided.

The second step is to the function test of the semiconductor circuit 01 to be tested, involves the high voltage and heavy current direction test: for example, testing for saturation pressure drop: and injecting high level into each logic IO port, and detecting the voltage drop at two ends of the bridge arm after the corresponding bridge arm is conducted. And if the pin HIN1 inputs a high level, detecting the conduction voltage drop of the upper bridge arm of the U phase. Other logic ports, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, and so on. As another example for the double pulse test: and measuring dynamic parameters of each bridge arm, wherein each bridge arm bears high-voltage and large-current impact.

And thirdly, testing the IO port of the semiconductor circuit 01 to be tested again, wherein the process of testing the IO port again is similar to that of the IO port testing in the first step, and the description is omitted. It should be noted that the IO port retest in the third step at least includes an on-off test in the IO port test.

In the embodiment, the semiconductor circuit 01 to be tested is subjected to primary IO port test, functional test and secondary IO port test in sequence, namely, the abnormal sample is preliminarily screened out by adopting low-current and low-voltage tests, and the original failure morphology of the sample is reserved; and then, performing functional port test, namely further testing the semiconductor circuit 01 to be tested by adopting large current and high voltage, so that secondary damage to an abnormal sample during the functional test can be avoided, the semiconductor circuit 01 to be tested can not be intercepted after being damaged in the functional test process, and finally performing IO port test once, so that the abnormal sample can be screened out again, and the test accuracy is improved.

The invention also discloses a method for testing the semiconductor circuit, as shown in fig. 5, the preparation method comprises the following steps:

step S100, connecting signal generating equipment to a first-class input pin of a semiconductor circuit to be detected, and connecting detection control equipment to a first-class output pin, corresponding to the first-class input pin, of the semiconductor circuit to be detected;

step S200, transmitting a first IO test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a first feedback signal according to the first IO test signal; acquiring a first feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the first feedback signal, and obtaining first IO test data of the semiconductor circuit to be tested according to a processing result;

step S300, after the IO test data meet the preset test conditions, connecting the signal generating equipment with a second type input pin of the semiconductor circuit to be tested, and connecting the detection control equipment with a second type output pin of the semiconductor circuit to be tested, wherein the second type output pin corresponds to the second type input pin;

step S400, transmitting a functional test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a second feedback signal according to the functional test signal; and acquiring a second feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the second feedback signal, and obtaining functional test data of the semiconductor circuit to be tested according to a processing result.

Specifically, the semiconductor circuit is prepared by the following specific steps: when testing the semiconductor circuit to be tested, firstly, the IO test is performed on the semiconductor circuit to be tested. The signal generating device is connected with a first type input pin corresponding to the semiconductor circuit to be tested, and transmits a first feedback signal to the first type input pin corresponding to the semiconductor circuit to be tested, so that the detection control device detects the first feedback signal of the semiconductor circuit to be tested in an IO test state, and processes the first feedback signal to obtain first IO test data. The detection control equipment judges whether the first IO test data accords with the expected set value of the semiconductor circuit parameter of the first feedback signal given by the corresponding signal generation equipment, if the detection control equipment detects that the obtained first IO test data accords with the expected set value, the IO test of the semiconductor circuit to be tested is judged to be qualified, and the next step of functional test is carried out; if not, the signal generating equipment terminates the output of the test signal, and the test is terminated.

Secondly, when the semiconductor circuit to be tested is subjected to function test, the signal generating equipment is connected with the corresponding second type input pin of the semiconductor circuit to be tested, and transmits a second feedback signal to the corresponding second type input pin of the semiconductor circuit to be tested, so that the detection control equipment detects the second feedback signal of the semiconductor circuit to be tested in a function test state, and processes the second feedback signal to obtain function test data. And the detection control equipment judges whether the functional test data accords with the expected set value of the semiconductor circuit parameter of the second feedback signal given by the corresponding signal generation equipment, and if the detection control equipment detects that the obtained functional test data accords with the expected set value, the functional test of the semiconductor circuit to be tested is qualified.

In the embodiment, the IO test and the function test are sequentially carried out on the semiconductor circuit to be tested, namely, the abnormal sample is preliminarily screened out by adopting the low-current and low-voltage test, and the original failure appearance of the sample is reserved; and then, performing functional port test, namely further testing the semiconductor circuit to be tested by adopting large current and high voltage, so that secondary damage to an abnormal sample during functional test can be avoided, the situation that the semiconductor circuit to be tested cannot be intercepted after being damaged in the functional test process is prevented, and the test accuracy of the semiconductor circuit is improved.

In one embodiment, as shown in fig. 6, step S400 is followed by:

step S500, when the functional test data meet the preset test conditions, the signal generating equipment is connected with the first type input pins of the semiconductor circuit to be tested, and the detection control equipment is connected with the first type output pins, corresponding to the first type input pins, of the semiconductor circuit to be tested.

Step S600, transmitting a second IO test signal to the semiconductor circuit to be tested through the signal generating equipment, so that the semiconductor circuit to be tested generates a third feedback signal according to the second IO test signal; and acquiring a third feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the third feedback signal, and obtaining second IO test data of the semiconductor circuit to be tested according to a processing result.

Specifically, the semiconductor circuit to be tested passes the IO test and the functional test in sequence, and then performs the IO test again. Specifically, the signal generation device is connected with a first type input pin corresponding to the semiconductor circuit to be tested, and transmits a third feedback signal to the first type input pin corresponding to the semiconductor circuit to be tested, so that the detection control device detects the third feedback signal of the semiconductor circuit to be tested in an IO test state, and processes the third feedback signal to obtain second IO test data. The detection control equipment judges whether the second IO test data accords with the expected set value of the semiconductor circuit parameter of the third feedback signal given by the corresponding signal generation equipment, if the detection control equipment detects that the obtained second IO test data accords with the expected set value, the IO test of the semiconductor circuit to be tested is qualified, and then the final test of the semiconductor circuit to be tested is qualified; if not, the signal generating equipment stops outputting the test signal, and the test is stopped. The method comprises the following steps of sequentially carrying out IO test, function test and IO test on a semiconductor circuit to be tested, namely initially screening out an abnormal sample by adopting a low-current and low-voltage test, and keeping the original failure appearance of the sample; then, performing functional port test, namely further testing the semiconductor circuit to be tested by adopting large current and high voltage; and finally, the abnormal sample is further screened out by adopting a low-current and low-voltage test, so that the secondary damage of the abnormal sample during the functional test can be avoided, the situation that the semiconductor circuit to be tested cannot be intercepted after being damaged in the functional test process is prevented, and the test accuracy of the semiconductor circuit is improved.

In one embodiment, as shown in fig. 7, step S600 is followed by:

and S700, comparing the second IO test data with corresponding preset test conditions through the detection control equipment, comparing the first IO test data with the second IO test data when the second IO test data meets the corresponding preset test conditions according to a comparison result, and determining that the semiconductor circuit to be tested is a qualified product when the comparison result meets a deviation range.

The detection control equipment judges whether the second IO test data accords with an expected set value of parameters of the semiconductor circuit corresponding to a third feedback signal given by the signal generation equipment, if the detection control equipment detects that the obtained second IO test data accords with the expected set value, the IO test of the semiconductor circuit to be tested is judged to be qualified, and then the final test of the semiconductor circuit to be tested is judged to be qualified; if not, the signal generating equipment terminates the output of the test signal, and the test is terminated. The method comprises the following steps of sequentially carrying out IO test, function test and IO test on a semiconductor circuit to be tested, namely initially screening out an abnormal sample by adopting a low-current and low-voltage test, and keeping the original failure appearance of the sample; then, performing functional port test, namely further testing the semiconductor circuit to be tested by adopting large current and high voltage; and finally, further screening out abnormal samples by adopting low-current and low-voltage tests, so that secondary damage to the abnormal samples during the functional test can be avoided, the semiconductor circuit to be tested can be prevented from being intercepted after the damage of the functional test process, and the abnormal samples are finally determined to be qualified products only when the comparison deviation meets the preset value by comparing the IO test data of the front part and the back part twice, so that the samples found to have parameter deterioration trend in the test process can be further removed, and the test accuracy of the semiconductor circuit is further improved.

In one example, the step of the IO test data satisfying the preset test condition includes:

applying preset first current signals to corresponding first-class input pins of a driving chip included in the semiconductor device to be tested in sequence through signal generation equipment, and obtaining diode characteristic parameters corresponding to the first-class input pins of the driving chip through detection control equipment according to the obtained corresponding first feedback signals;

and sequentially applying preset level signals to the first class of input pins of the bridge arms contained in the corresponding semiconductor equipment to be tested through the signal generating equipment, and judging the on-off state of the corresponding bridge arms according to the obtained corresponding first feedback signals through the detection control equipment.

Further, the step of obtaining the functional test data of the semiconductor circuit to be tested comprises:

sequentially applying a preset level signal to a second type of input pins of a bridge arm contained in the corresponding semiconductor device to be tested through signal generation equipment, and obtaining pressure drop data of two ends of the corresponding bridge arm according to the obtained corresponding second feedback signal through detection control equipment;

and sequentially applying preset pulse signals to second-class input pins of bridge arms contained in the corresponding semiconductor equipment to be tested through the signal generating equipment, and obtaining dynamic parameters of the corresponding bridge arms according to the obtained corresponding second feedback signals through the detection control equipment.

Specifically, the specific test process of the semiconductor circuit to be tested is as follows: firstly, testing IO port parameters of a semiconductor circuit to be tested, including but not limited to the following pin pins: a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an ITRIP pin, a VDD pin, a VSS pin, a VDD pin and a VSS pin; firstly, applying 0.2-1V voltage between every two pins to detect current for judging whether the pins have open circuit and short circuit abnormal states, and the method can be used for detecting the open circuit and short circuit states of a certain pin to all the pins; then, for the pins of the driving chip, including but not limited to pin HIN1 pin, HIN2 pin, HIN3 pin, LIN1 pin, LIN2 pin, LIN3 pin, PFCIN pin, FAULT pin and ITRIP pin, diode characteristics between VSS pin and VDD pin are respectively matched (10 uA-1mA current is filled between the two pins); and finally, testing the on-off test of the IO ports, injecting high and low levels into each logic IO port, and detecting the on and off actions of corresponding bridge arms. Such as: and when the HIN1 pin inputs a high level and is connected with the corresponding U-phase upper bridge arm, the HIN2 pin, the HIN3 pin, the LIN1 pin, the LIN2 pin, the LIN3 pin and the PFCIN pin are connected with the corresponding U-phase upper bridge arm when the HIN1 pin inputs a low level. The small-current and low-voltage tests are used for primarily screening out abnormal samples, the original failure appearance of the samples is kept, and secondary damage to the abnormal samples during large-current and high-voltage condition tests adopted in the functional tests is avoided.

The second step is to the function test of the semiconductor circuit to be tested, which relates to the high voltage and heavy current direction test: for example, testing for saturation pressure drop: and injecting high level into each logic IO port, and detecting the voltage drop at two ends of the bridge arm after the corresponding bridge arm is conducted. And if the pin HIN1 inputs a high level, detecting the conduction voltage drop of the upper bridge arm of the U phase. Other logic ports, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, and so on. As another example for the double pulse test: and measuring dynamic parameters of each bridge arm, wherein each bridge arm bears high-voltage and large-current impact.

And thirdly, testing the IO port of the semiconductor circuit to be tested again, wherein the process of testing the IO port again is similar to that of the IO port in the first step, and the details are not repeated. It should be noted that the IO port retest in the third step at least includes an on-off test in the IO port test.

In the embodiment, the initial IO port test, the function test and the second IO port test are sequentially carried out on the semiconductor circuit to be tested, namely, the small-current and low-voltage tests are adopted to initially screen out abnormal samples, and the original failure appearance of the samples is reserved; and then, performing functional port test, namely further testing the semiconductor circuit to be tested by adopting large current and high voltage, so that secondary damage of an abnormal sample during the functional test can be avoided, the semiconductor circuit to be tested can be prevented from being intercepted after the damage of the functional test process, and finally, performing IO port test once, so that the abnormal sample can be screened out again, and the test accuracy is improved.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "above," and "over" a second feature may be directly on or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A system for testing a semiconductor circuit, comprising:

the signal generating device is used for being connected with a first class input pin of a semiconductor circuit to be tested and is configured to transmit a first IO test signal to the semiconductor circuit to be tested so that the semiconductor circuit to be tested generates a first feedback signal according to the first IO test signal;

the detection control equipment is used for being connected with a first class output pin, corresponding to a first class input pin, of the semiconductor circuit to be detected, and is configured to acquire the first feedback signal generated by the semiconductor circuit to be detected, process the first feedback signal, and obtain first IO test data of the semiconductor circuit to be detected according to a processing result;

after the IO test data meet the preset test condition, the signal generation device is further configured to connect a second type input pin of the semiconductor circuit to be tested, and transmit a functional test signal to the semiconductor circuit to be tested, so that the semiconductor circuit to be tested generates a second feedback signal according to the functional test signal; the detection control equipment is also used for connecting a second type output pin corresponding to a second type input pin of the semiconductor circuit to be detected, and is configured to acquire the second feedback signal generated by the semiconductor circuit to be detected, process the second feedback signal and obtain functional test data of the semiconductor circuit to be detected according to a processing result;

the semiconductor circuit comprises a driving chip, a PFC (power factor correction) module and an inversion component connected with the driving chip, wherein the inversion component comprises three groups of inversion modules.

2. The system according to claim 1, wherein after the functional test data meets a preset test condition, the signal generating device is further configured to connect a first class input pin of the semiconductor circuit to be tested, and transmit a second IO test signal to the semiconductor circuit to be tested, so that the semiconductor circuit to be tested generates a third feedback signal according to the second IO test signal;

the detection control equipment is also used for connecting a first class output pin corresponding to the first class input pin of the semiconductor circuit to be detected, and is configured to acquire the third feedback signal generated by the semiconductor circuit to be detected, process the third feedback signal, and obtain second IO test data of the semiconductor circuit to be detected according to a processing result.

3. The test system of claim 2, wherein the test control device comprises a controller, and a test module connected to the controller;

the detection module is used for receiving the first feedback signal, the second feedback signal and the third feedback signal in sequence and transmitting the received first feedback signal, the received second feedback signal and the received third feedback signal to the controller in sequence; the controller is configured to sequentially process the received first feedback signal, the second feedback signal, and the third feedback signal to obtain the first IO test data, the functional test data, and the second IO test data, respectively;

the controller is further used for confirming that the semiconductor circuit to be tested is a qualified product when the first IO test data, the functional test data and the second IO test data respectively meet corresponding preset test conditions, the first IO test data and the second IO test data are compared, and the comparison result meets a deviation range.

4. The system for testing a semiconductor circuit according to claim 3, wherein the controller is further configured to connect the signal generating device, and configured to transmit a signal switching instruction to the signal generating device, so that the signal generating device switches the current output signal according to the signal switching instruction; the current output signal is the first IO test signal, the functional test signal, or the second IO test signal.

5. The test system for the semiconductor circuit according to claim 1, wherein the first-class input pin comprises a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an itrep pin, a VDD pin, a VSS pin, a VDD pin, or a VSS pin; the first class output pins comprise a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, a PFC pin, -VCC pin, a U-pin, a V-pin, a W-pin, a HIN1 pin, a HIN2 pin, a HIN3 pin, a LIN1 pin, a LIN2 pin, a LIN3 pin, a PFCIN pin, a FAULT pin, an ITRIP pin, a VDD pin, a VSS pin, a VDD pin or a VSS pin;

the second type of input pins comprise a HIN1 pin, a HIN2 pin, a HIN3 pin, an LIN1 pin, an LIN2 pin, an LIN3 pin or a PFCIN pin; the second type of output pin comprises a HO1 pin, a HO2 pin, a HO3 pin, a LO1 pin, a LO2 pin, a LO3 pin or a PFCOUT pin.

6. A method of testing a semiconductor circuit according to claims 1 to 5, comprising the steps of:

connecting signal generating equipment with a first type input pin of a semiconductor circuit to be detected, and connecting detection control equipment with a first type output pin, corresponding to the first type input pin, of the semiconductor circuit to be detected;

transmitting a first IO test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a first feedback signal according to the first IO test signal; acquiring the first feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the first feedback signal, and obtaining first IO test data of the semiconductor circuit to be tested according to a processing result;

after the IO test data meet the preset test conditions, connecting the signal generation equipment with a second type input pin of the semiconductor circuit to be tested, and connecting the detection control equipment with a second type output pin of the semiconductor circuit to be tested, wherein the second type output pin corresponds to the second type input pin;

transmitting a functional test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a second feedback signal according to the functional test signal; and acquiring the second feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the second feedback signal, and obtaining the functional test data of the semiconductor circuit to be tested according to the processing result.

7. The method of claim 6, wherein the step of obtaining functional test data for the semiconductor circuit under test further comprises:

when the functional test data meet preset test conditions, connecting the signal generation equipment with a first class input pin of a semiconductor circuit to be tested, and connecting the detection control equipment with a first class output pin of the semiconductor circuit to be tested, wherein the first class output pin corresponds to the first class input pin;

transmitting a second IO test signal to the semiconductor circuit to be tested through the signal generating equipment so that the semiconductor circuit to be tested generates a third feedback signal according to the second IO test signal; and acquiring the third feedback signal generated by the semiconductor circuit to be tested through the detection control equipment, processing the third feedback signal, and obtaining second IO test data of the semiconductor circuit to be tested according to a processing result.

8. The method of claim 7, wherein the step of obtaining second IO test data of the semiconductor circuit under test further comprises:

and comparing the second IO test data with corresponding preset test conditions through the detection control equipment, comparing the first IO test data with the second IO test data when the second IO test data meets the corresponding preset test conditions according to a comparison result, and determining that the semiconductor circuit to be tested is a qualified product when the comparison result meets a deviation range.

9. The method of claim 8, wherein the step of the IO test data satisfying the predetermined test condition is preceded by the steps of:

sequentially applying a preset first voltage signal between two adjacent first-class input pins through the signal generating equipment, and judging the open-short circuit state of the first-class input pins through the detection control equipment according to the obtained corresponding first feedback signal;

applying preset first current signals to corresponding first-class input pins of a driving chip included in the semiconductor device to be tested in sequence through the signal generating device, and obtaining diode characteristic parameters corresponding to the first-class input pins of the driving chip according to the obtained corresponding first feedback signals through the detection control device;

and sequentially applying a preset level signal to the first class of input pins corresponding to the bridge arms included in the semiconductor device to be tested through the signal generating device, and judging the on-off state of the corresponding bridge arms through the detection control device according to the obtained corresponding first feedback signals.

10. The method of claim 9, wherein the step of obtaining functional test data for the semiconductor circuit under test comprises:

sequentially applying a preset level signal to a second type of input pins corresponding to a bridge arm included in the semiconductor device to be tested through the signal generation device, and obtaining pressure drop data corresponding to two ends of the bridge arm through the detection control device according to the obtained corresponding second feedback signal;

and sequentially applying preset pulse signals to second-class input pins corresponding to bridge arms included in the semiconductor device to be tested through the signal generation device, and obtaining dynamic parameters corresponding to the bridge arms through the detection control device according to the obtained corresponding second feedback signals.