CN115602682A - Bidirectional thyristor device - Google Patents

Bidirectional thyristor device Download PDF

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Publication number
CN115602682A
CN115602682A CN202211297579.3A CN202211297579A CN115602682A CN 115602682 A CN115602682 A CN 115602682A CN 202211297579 A CN202211297579 A CN 202211297579A CN 115602682 A CN115602682 A CN 115602682A
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well
injection region
metal piece
polysilicon gate
trigger
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李凡阳
韩嘉迅
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Fuzhou University
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Fuzhou University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The invention provides a bidirectional silicon controlled rectifier device, which is a bidirectional silicon controlled rectifier device triggered by an RC circuit, and comprises an RC coupling auxiliary trigger path consisting of an external RC coupling circuit, a phase inverter and a PMOS (P-channel metal oxide semiconductor), a first discharge path provided by an annular PMOS (P-channel metal oxide semiconductor), and an SCR heavy current discharge path consisting of a PNPN (positive-negative-positive-negative) structure; the invention can be used for ESD protection of integrated circuits, can quickly detect ESD signals, and has low trigger voltage and strong current driving capability.

Description

Bidirectional thyristor device
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a bidirectional silicon controlled rectifier device.
Background
In recent years, integrated circuits are rapidly developed, and with the reduction of chip size and the increasing of integration level, an ESD (Electro-Static discharge) phenomenon becomes more and more non-negligible, but an ESD signal generally has a short action time and a large instantaneous energy, and an ESD window becomes more and more narrow, and an SCR is applied to various products as a protection device with strong area robustness and strong current discharge capability, but the trigger voltage of the SCR device in the conventional technology is higher. How to design an SCR device which is fast in ESD signal detection, low in trigger voltage and high in area efficiency has scientific and economic values.
The conventional bidirectional SCR structure is shown in fig. 1, and is a PNPNP structure. In the conventional structure, a P +/NW/PW/NW/N + path is formed between an anode and a cathode to discharge forward ESD current; a P +/NW/PW/NW/N + path is also formed between the cathode and the anode to bleed reverse ESD current. When the pulse current is gradually increased, the diode formed by the NW/PW firstly generates avalanche breakdown, then the current in the body is gradually increased, and when the voltage flowing through the resistors R1, R3 or R2 and R4 reaches 0.7V, the PNP triode and the NPN triode are started in sequence, so that a positive feedback path is formed in the body, and the ESD current is quickly discharged.
Disclosure of Invention
The invention provides a bidirectional silicon controlled rectifier device which can be used for ESD protection of an integrated circuit, can quickly detect an ESD signal, and has low trigger voltage and strong current driving capability.
The invention adopts the following technical scheme.
A bidirectional SCR device triggered by an RC circuit comprises an RC coupling circuit, an RC coupling auxiliary trigger path consisting of a phase inverter and a PMOS, a first discharge path provided by a ring PMOS, and an SCR high-current discharge path consisting of a PNPN structure, wherein the external RC coupling circuit provides ESD signal voltage for triggering ESD protection action of the device in a self-biasing mode.
When the silicon controlled rectifier device is prepared, a deep N well DNW (113) is arranged on a substrate P-sub (114) of the silicon controlled rectifier device by a BCD (binary-coded decimal) process, and a first P well (110), a first N well (111) and a second P well (112) are arranged in the deep N well;
the first P trap is internally provided with a first P + injection region (101) and a first N + injection region (102); a second P + injection region (103) which is connected with the first P well and the first N well is arranged in the first N well;
the second N + injection region (105) is distributed at the central symmetry axis position of the first N well (111) and is surrounded by the third annular P + injection region (104);
the fourth P + injection region (106) is connected with the first N well and the second P well and is symmetrical with the second P + injection region by the central symmetry axis of the first N well (111);
the third N + injection region (107) is positioned in the second P well and is symmetrical with the first N + injection region (102) by a central symmetry axis of the first N well (111);
the fifth P + injection region (108) is positioned in the second P well and is symmetrical with the first P + injection region (101) by a central symmetry axis of the first N well (111);
in the first N well (111), a left side polysilicon gate (115) and a left side thin gate oxide (117) are connected with a second P + injection region (103) and a third annular P + injection region (104), and a right side polysilicon gate (116) and a right side thin gate oxide (118) are connected with the third annular P + injection region (104) and a fourth P + injection region (106); the second N + injection region (105) is connected with a capacitor (119) of an external RC coupling circuit (212), and the capacitor (119) is connected with a first resistor (124), a second resistor (122) and a third resistor (123); the first resistor is grounded; the second resistor and the third resistor are respectively connected with the first inverter (120) and the second inverter (121).
The external RC coupling circuit is connected with a left polysilicon gate (115) of the first N well through a fifth metal piece (205), connected with a second N + injection region (105) of the first N well through a sixth metal piece (206), and connected with a right polysilicon gate (116) of the first N well through a seventh metal piece (207);
the first P + injection region (101) is connected with a first metal piece (201), the first N + injection region (102) is connected with a second metal piece (202), and the third N + injection region (107) is connected with a third metal piece (203); the fifth P + injection region (108) is connected with the fourth metal piece (204) in a leading mode;
the first metal piece and the second metal piece are connected with an eighth metal piece (208); the eighth metal piece leads out a first electrode (211) as a first electrodynamic stress terminal;
the third metal piece and the fourth metal piece are connected with a ninth metal (209); the ninth metal piece leads out a second electrode (212) as a second electrodynamic stress terminal.
The first metal piece, the second metal piece, the third metal piece, the fourth metal piece, the fifth metal piece, the sixth metal piece and the seventh metal piece are made of the same material, and the eighth metal piece and the ninth metal piece are made of the same material.
The PMOS of the RC-coupled auxiliary trigger path trigger circuit comprises a second P + injection region (103) crossing the first P-well (110) and the first N-well (111), and further comprises a fourth P + injection region (106) crossing the first N-well (111) and the second P-well (112);
the left side polysilicon gate (115) of the first N trap, the right side polysilicon gate (116) of the first N trap, the left side polysilicon gate (115), the left side thin gate oxide (117), the right side polysilicon gate (116) and the right side thin gate oxide (118) are all PMOS gates; the left side polysilicon gate (115) of the first N well is connected with a first inverter (120), and the right side polysilicon gate (116) of the first N well is connected with a second inverter (121).
The RC coupling auxiliary trigger path trigger circuit realizes quick trigger by quickly detecting ESD pulse, and reduces trigger voltage by a PMOS and an RC trigger circuit; the PMOS is of a ring structure and is used for providing an additional current leakage path to reduce the on-resistance, increase the current driving capability and increase the area efficiency.
In the external RC coupling circuit, the voltages led into the left side polysilicon gate (115) and the right side polysilicon gate (116) are adjusted by adjusting a first resistor (124), a second resistor (122) and a third resistor (123), so that the opening degree of PMOS trigger is controlled and adjusted to adjust the trigger voltage.
In the BCD process, a deep N well is arranged on a P substrate, a well region is isolated and injected in the deep N well, and STI field oxygen is used for isolation between P + and N + injection; the second N + injection region is an N + high-concentration injection region;
the BCD process adjusts the voltage conducted to the RC coupling circuit by adjusting the concentration of the N + injection region;
the BCD process adjusts the maintaining voltage by adjusting the widths of the left polysilicon gate (115) of the first N well and the right polysilicon gate (116) of the first N well, or adjusts the widths of the second P + injection region (103), the third annular P + injection region (104), the second N + injection region (105) and the fourth P + injection region (106), so that the high maintaining voltage is realized while the low trigger voltage is realized.
The bidirectional silicon controlled rectifier device is of a bilateral symmetry structure and has the same electrical characteristics and SCR current discharge paths under positive ESD stress and negative ESD stress.
The external RC coupling circuit is an external RC trigger circuit, and the bidirectional controllable silicon device generates ESD voltage in a self-bias mode.
The invention provides a bidirectional SCR device which can quickly detect ESD signals and has low trigger voltage and strong current driving capability, aiming at the problem that the SCR device can improve the area robustness and the current discharge capability but has higher trigger voltage.
The bidirectional SCR structure can increase the area efficiency and reduce the chip area, and meanwhile, the withstand voltage is improved and the power consumption is reduced by adopting a BCD (bipolar complementary metal oxide semiconductor) process. The bidirectional controllable silicon device can realize quick triggering, large current capacity, low on-resistance, large failure current and high area efficiency.
The invention can be used for ESD protection of an integrated circuit, realizes that the area efficiency can be increased, the failure current can be increased, the withstand voltage can be improved while the trigger voltage is reduced, the ESD signal detection is accelerated and the trigger is accelerated, and simultaneously, the maintenance voltage can be improved by increasing the length of a grid electrode.
According to the bidirectional silicon controlled device, the RC coupling circuit is fully utilized for auxiliary triggering, the advantage of strong SCR robustness is combined, the BCD high withstand voltage is utilized, the grid is increased, the maintaining voltage is improved, the ESD robustness is enhanced, and the failure current can be increased by utilizing an additional conduction path after triggering; in addition, the invention realizes a completely symmetrical electrical structure through design, so that the device has the same electrical characteristics and SCR current discharge paths under the positive and negative ESD stress, the area efficiency can be improved, and the bidirectional protection of ESD can be realized.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a bidirectional SCR structure in the prior art;
FIG. 2 is a schematic circuit diagram of the present invention;
FIG. 3 is another schematic circuit diagram of the present invention;
FIG. 4 is a schematic diagram of the present invention from the top (without the RC coupling circuit portion);
in the figure:
101-a first P + implant region; 102-a first N + implant region; 103-a second P + implant region; 104-a third annular P + implant region; 105-a second N + implant region; 106-fourth P + implant region; 107-a third N + implant region; 108-a fifth P + implant region;
110-a first P-well; 111-first N-well; 112-second P-well; 113-deep N-well DNW; 114-substrate p-sub; 115-left polysilicon gate; 116-right polysilicon gate; 117-left thin gate oxide; 118-thin right gate oxide; 119-capacitance;
120-a first inverter; 121-a second inverter; 122-a second resistance; 123-a third resistor; 124-first resistance;
201-a first metal piece; 202-a second metallic article; 203-a third metal piece; 204-a fourth metal piece; 205-fifth hardware; 206-a sixth metallic element; 207-seventh metal element; 208-an eighth metallic element; 209-a ninth metal piece; 211-a first electrode; 212-second electrode.
Detailed Description
As shown in the figure, the bidirectional silicon controlled rectifier device is triggered by an RC circuit, the silicon controlled rectifier device comprises an RC coupling auxiliary trigger path consisting of an external RC coupling circuit, a phase inverter and a PMOS, a first discharge path provided by a ring-shaped PMOS, and an SCR heavy current discharge path consisting of a PNPN structure, and the external RC coupling circuit provides an ESD signal voltage for triggering the ESD protection action of the device in a self-bias mode.
When the silicon controlled rectifier device is prepared, a deep N well DNW113 is arranged on a substrate P-sub114 of the silicon controlled rectifier device by a BCD (binary coded decimal) process, and a first P well 110, a first N well 111 and a second P well 112 are arranged in the deep N well;
a first P + injection region 101 and a first N + injection region 102 are arranged in the first P well; a second P + injection region 103 which is connected with the first P well and the first N well is arranged in the first N well;
the second N + implantation region 105 is distributed at the central symmetry axis position of the first N well 111 and surrounded by the third annular P + implantation region 104;
the fourth P + injection region 106 is connected to the first N well and the second P well, and is symmetric to the second P + injection region about the central axis of symmetry of the first N well 111;
the third N + implantation region 107 is located in the second P well and is symmetrical to the first N + implantation region 102 about the central symmetry axis of the first N well 111;
the fifth P + implantation region 108 is located in the second P well and is symmetric to the first P + implantation region 101 about the central symmetry axis of the first N well 111;
in the first N well 111, the left polysilicon gate 115 and the left thin gate oxide 117 connect the second P + implantation region 103 and the third P + implantation region 104, and the right polysilicon gate 116 and the right thin gate oxide 118 connect the third P + implantation region 104 and the fourth P + implantation region 106; the second N + implantation region 105 is connected to a capacitor 119 of an external RC coupling circuit 212, and the capacitor 119 is connected to the first resistor 124, the second resistor 122 and the third resistor 123; the first resistor is grounded; the second resistor and the third resistor are connected to the first inverter 120 and the second inverter 121, respectively.
The external RC coupling circuit is connected to the left polysilicon gate 115 of the first N well through a fifth metal 205, connected to the second N + injection region 105 of the first N well through a sixth metal 206, and connected to the right polysilicon gate 116 of the first N well through a seventh metal 207;
the first P + implantation region 101 is connected with a first metal piece 201, the first N + implantation region 102 is connected with a second metal piece 202, and the third N + implantation region 107 is connected with a third metal piece 203; the fifth P + implantation region 108 is connected to the fourth metal element 204;
the first metal piece, the second metal piece and the eighth metal piece 208 are connected; the eighth metal piece leads out a first electrode 211 as a first electrodynamic stress terminal;
the third metal piece and the fourth metal piece are connected with a ninth metal 209; the ninth metal piece leads out the second electrode 212 as a second electro-mechanical stress terminal.
The first metal piece, the second metal piece, the third metal piece, the fourth metal piece, the fifth metal piece, the sixth metal piece and the seventh metal piece are made of the same material, and the eighth metal piece and the ninth metal piece are made of the same material.
The PMOS of the RC-coupled auxiliary trigger path trigger circuit includes a second P + implant region 103 crossing the first P-well 110 and the first N-well 111, and further includes a fourth P + implant region 106 crossing the first N-well 111 and the second P-well 112;
the left polysilicon gate 115 of the first N well, the right polysilicon gate 116 of the first N well, the left polysilicon gate 115, the left thin gate oxide 117, the right polysilicon gate 116 and the right thin gate oxide 118 are all PMOS gates; the left polysilicon gate 115 of the first N-well is connected to the first inverter 120, and the right polysilicon gate 116 of the first N-well is connected to the second inverter 121.
The RC coupling auxiliary trigger path trigger circuit realizes quick trigger by quickly detecting ESD pulse, and reduces trigger voltage by a PMOS and an RC trigger circuit; the PMOS is of a ring structure and is used for providing an additional current leakage path to reduce the on-resistance, increase the current driving capability and increase the area efficiency
In the external RC coupling circuit, the voltages introduced to the left polysilicon gate 115 and the right polysilicon gate 116 are adjusted by adjusting the first resistor 124, the second resistor 122 and the third resistor 123, so as to control the turn-on degree of the PMOS trigger to adjust the trigger voltage.
In the BCD process, a deep N well is arranged on a P substrate, a well region is isolated and injected in the deep N well, and STI field oxygen is used for isolation between P + and N + injection; the second N + injection region is an N + high-concentration injection region;
the BCD process adjusts the voltage conducted to the RC coupling circuit by adjusting the concentration of the N + injection region;
the BCD process adjusts the sustain voltage by adjusting the widths of the left polysilicon gate 115 of the first N well and the right polysilicon gate 116 of the first N well, or adjusts the widths of the second P + implantation region 103, the third annular P + implantation region 104, the second N + implantation region 105, and the fourth P + implantation region 106, so as to achieve a high sustain voltage while achieving a low trigger voltage.
The bidirectional controllable silicon device is of a bilateral symmetry structure and has the same electrical characteristics and SCR current discharge paths under positive and negative ESD stress.
The external RC coupling circuit is an external RC trigger circuit, and the bidirectional controllable silicon device generates ESD voltage in a self-bias mode.
Example (b):
referring to fig. 2, 3 and 4, the present example provides a triac device including a main SCR conductive path PNPN, and a high-concentration N + external RC coupling circuit connected to an embedded PMOS.
The device of this example can function to lower and adjust the trigger voltage by the high concentration N + implantation region 105 and the adjustment of the resistors 122,123, 124; the detection of ESD pulses can be accelerated and the triggering speed can be accelerated through the external RC coupling circuits 119,122,123 and 124 and the inverters 120 and 121; when the PMOS103,104,115,117 and 104,106,116,118 are conducted, a conducting path can be added, the current driving capability is increased, and the failure current is increased; the lengths of the grid electrodes 115,117 and 116,118 can be increased, the maintaining voltage can be increased, and the BCD process is used for enabling the device to have better voltage resistance; the bidirectional controllable silicon device is completely symmetrical and has bidirectional ESD protection capability.
According to the bidirectional silicon controlled rectifier device, the RC coupling circuit is fully utilized for auxiliary triggering, the advantage of strong SCR robustness is combined, the BCD high withstand voltage is utilized, the grid is increased, the maintaining voltage is improved, the ESD robustness is enhanced, and an extra conduction path is utilized after triggering to increase the failure current. In addition, the structure is completely symmetrical through design, the device has the same electrical characteristics and SCR current discharge paths under positive and negative ESD stress, the area efficiency can be improved, and the bidirectional protection of ESD is realized.
It should be noted that the above is only a preferred embodiment of the present invention. However, the present invention is not limited to the above embodiments, and any equivalent changes and modifications made according to the embodiments of the present invention, which do not bring out the functional effects beyond the scope of the present invention, belong to the protection scope of the present invention.

Claims (10)

1. The bidirectional SCR device triggered by RC circuit is characterized in that: the silicon controlled rectifier device comprises an RC coupling auxiliary trigger path consisting of an external RC coupling circuit, a phase inverter and a PMOS (P-channel metal oxide semiconductor), a first discharge path provided by a ring PMOS (P-channel metal oxide semiconductor), and an SCR (silicon controlled rectifier) large-current discharge path consisting of a PNPN (positive-negative) structure, wherein the external RC coupling circuit provides ESD (electro-static discharge) signal voltage for triggering ESD (electro-static discharge) protection action of the device in a self-biasing mode.
2. A triac device according to claim 1 wherein: when the silicon controlled rectifier device is prepared, a deep N well DNW (113) is arranged on a substrate P-sub (114) of the silicon controlled rectifier device by a BCD (binary-coded decimal) process, and a first P well (110), a first N well (111) and a second P well (112) are arranged in the deep N well;
the first P trap is internally provided with a first P + injection region (101) and a first N + injection region (102); a second P + injection region (103) which is connected with the first P well and the first N well is arranged in the first N well;
the second N + injection region (105) is distributed at the central symmetry axis position of the first N well (111) and is surrounded by the third annular P + injection region (104);
the fourth P + injection region (106) is connected with the first N well and the second P well and is symmetrical with the second P + injection region by the central symmetry axis of the first N well (111);
the third N + injection region (107) is positioned in the second P well and is symmetrical with the first N + injection region (102) by a central symmetry axis of the first N well (111);
the fifth P + injection region (108) is positioned in the second P well and is symmetrical with the first P + injection region (101) by a central symmetry axis of the first N well (111);
in the first N well (111), a left side polysilicon gate (115) and a left side thin gate oxide (117) are connected with a second P + injection region (103) and a third annular P + injection region (104), and a right side polysilicon gate (116) and a right side thin gate oxide (118) are connected with the third annular P + injection region (104) and a fourth P + injection region (106); the second N + injection region (105) is connected with a capacitor (119) of an external RC coupling circuit (212), and the capacitor (119) is connected with a first resistor (124), a second resistor (122) and a third resistor (123); the first resistor is grounded; the second resistor and the third resistor are respectively connected with the first inverter (120) and the second inverter (121).
3. A triac device according to claim 2 wherein: the external RC coupling circuit is connected with a left polysilicon gate (115) of the first N well through a fifth metal piece (205), connected with a second N + injection region (105) of the first N well through a sixth metal piece (206), and connected with a right polysilicon gate (116) of the first N well through a seventh metal piece (207);
the first P + injection region (101) is connected with a first metal piece (201), the first N + injection region (102) is connected with a second metal piece (202), and the third N + injection region (107) is connected with a third metal piece (203); the fifth P + injection region (108) is connected with the fourth metal piece (204) in a leading mode;
the first metal piece and the second metal piece are connected with an eighth metal piece (208); the eighth metal piece leads out a first electrode (211) as a first electrodynamic stress terminal;
the third metal piece and the fourth metal piece are connected with a ninth metal (209); the ninth metal piece leads out a second electrode (212) as a second electrodynamic stress terminal.
4. A triac device according to claim 3 wherein: the first metal piece, the second metal piece, the third metal piece, the fourth metal piece, the fifth metal piece, the sixth metal piece and the seventh metal piece are made of the same material, and the eighth metal piece and the ninth metal piece are made of the same material.
5. A triac device according to claim 3 wherein: the PMOS of the RC-coupled auxiliary trigger path trigger circuit comprises a second P + injection region (103) crossing the first P-well (110) and the first N-well (111), and further comprises a fourth P + injection region (106) crossing the first N-well (111) and the second P-well (112);
the left side polysilicon gate (115) of the first N trap, the right side polysilicon gate (116) of the first N trap, the left side polysilicon gate (115), the left side thin gate oxide (117), the right side polysilicon gate (116) and the right side thin gate oxide (118) are all PMOS gates; the left side polysilicon gate (115) of the first N trap is connected with a first inverter (120), and the right side polysilicon gate (116) of the first N trap is connected with a second inverter (121).
6. A triac device according to claim 5, wherein: the RC coupling auxiliary trigger path trigger circuit realizes quick trigger by quickly detecting ESD pulse, and reduces trigger voltage by a PMOS and an RC trigger circuit; the PMOS is of a ring structure and is used for providing an additional current leakage path to reduce the on-resistance, increase the current driving capability and increase the area efficiency.
7. A triac device according to claim 5, wherein: in the external RC coupling circuit, the voltages led into the left side polysilicon gate (115) and the right side polysilicon gate (116) are adjusted by adjusting a first resistor (124), a second resistor (122) and a third resistor (123), so that the opening degree of PMOS trigger is controlled and adjusted to adjust the trigger voltage.
8. A triac device according to claim 5, wherein: in the BCD process, a deep N well is arranged on a P substrate, a well region is isolated and injected in the deep N well, and STI field oxygen is used for isolation between P + and N + injection; the second N + injection region is an N + high-concentration injection region;
the BCD process adjusts the voltage conducted to the RC coupling circuit by adjusting the concentration of the N + injection region;
the BCD process adjusts the maintaining voltage by adjusting the widths of the left polysilicon gate (115) of the first N well and the right polysilicon gate (116) of the first N well, or adjusts the widths of the second P + injection region (103), the third annular P + injection region (104), the second N + injection region (105) and the fourth P + injection region (106), so that the high maintaining voltage is realized while the low trigger voltage is realized.
9. A triac device according to claim 2 wherein: the bidirectional silicon controlled rectifier device is of a bilateral symmetry structure and has the same electrical characteristics and SCR current discharge paths under positive ESD stress and negative ESD stress.
10. A triac device according to claim 2, wherein: the external RC coupling circuit is an external RC trigger circuit, and the bidirectional controllable silicon device generates ESD voltage in a self-bias mode.
CN202211297579.3A 2022-10-22 2022-10-22 Bidirectional thyristor device Pending CN115602682A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314277A (en) * 2023-05-15 2023-06-23 微龛(广州)半导体有限公司 SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314277A (en) * 2023-05-15 2023-06-23 微龛(广州)半导体有限公司 SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method
CN116314277B (en) * 2023-05-15 2023-08-22 微龛(广州)半导体有限公司 SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method

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