CN115600352A

CN115600352A - Fault detection method and device, electronic equipment and readable storage medium

Info

Publication number: CN115600352A
Application number: CN202110719858.3A
Authority: CN
Inventors: 周昀逸
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2023-01-13
Also published as: WO2023274121A1

Abstract

The application provides a fault detection method, a fault detection device, electronic equipment and a readable storage medium, and relates to the technical field of detection. The fault detection method comprises the following steps: simulating a circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit; carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to a simulation state; and detecting the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determining the fault type of the to-be-detected circuit. By simulating the circuit to be tested, the overhaul of the circuit to be tested is reduced, and the damage to the circuit to be tested is avoided; carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to a simulation state so as to enrich signal samples; and detecting the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, determining the fault type of the to-be-detected circuit, and improving the fault detection accuracy of the to-be-detected circuit.

Description

Fault detection method and device, electronic equipment and readable storage medium

Technical Field

The present application relates to the field of detection technologies, and in particular, to a fault detection method and apparatus, an electronic device, and a readable storage medium.

Background

With the improvement of detection technology, the detection rate of permanent faults of the circuit system is higher and higher, and the detection rate of intermittent faults of the circuit system and the maintenance cost are not changed greatly. An intermittent fault of a circuit system is an intermittent and unpredictable fault which appears and disappears randomly, for example, the intermittent fault is generated and continued for a period of time, and the circuit system recovers the execution capacity of the circuit system by itself without any reparative maintenance operation.

Under the condition that the intermittent fault is determined to occur and is in an active period, a circuit system can generate an error result, so that the task in the circuit system is easily interrupted, and a false alarm can be caused; when it is determined that the intermittent fault disappears, the circuit system fault outputs a correct result, but the cause of the intermittent fault cannot be accurately detected, which results in waste of resources of the circuit system.

Disclosure of Invention

The application provides a fault detection method, a fault detection device, electronic equipment and a readable storage medium.

The embodiment of the application provides a fault detection method, which comprises the following steps: simulating a circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit; carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to a simulation state; and detecting the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determining the fault type of the to-be-detected circuit.

The embodiment of the application provides a fault detection device, including: the acquisition module is configured to simulate the circuit to be tested and acquire a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit; the signal acquisition module is configured to acquire signals of the simulation circuit and obtain a simulation signal set corresponding to a simulation state; and the fault detection module is configured to detect the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determine the fault type of the to-be-detected circuit.

An embodiment of the present application provides an electronic device, including: one or more processors; a memory having one or more programs stored thereon, which when executed by the one or more processors, cause the one or more processors to implement any one of the fault detection methods in the embodiments of the present application.

The embodiment of the present application provides a readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements any one of the fault detection methods in the embodiment of the present application.

According to the fault detection method, the fault detection device, the electronic equipment and the readable storage medium, the circuit to be detected is simulated, so that the simulation state of the simulation circuit and the simulation circuit corresponding to the circuit to be detected is obtained, the overhaul of the circuit to be detected is reduced, and the damage to the circuit to be detected is avoided; carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to a simulation state so as to enrich signal samples and improve the detection accuracy of the circuit to be detected; according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, the to-be-detected signal of the to-be-detected circuit is detected, the fault type of the to-be-detected circuit is determined, the fault detection accuracy of the to-be-detected circuit is improved, and unnecessary maintenance cost is reduced.

With respect to the above embodiments and other aspects of the present application and implementations thereof, further description is provided in the accompanying drawings description, detailed description and claims.

Drawings

Fig. 1 shows a schematic flow chart of a fault detection method according to an embodiment of the present application.

Fig. 2 is a schematic flow chart illustrating a fault detection method according to another embodiment of the present application.

Fig. 3 is a schematic flowchart illustrating a fault detection method according to still another embodiment of the present application.

Fig. 4 is a schematic flow chart illustrating a fault detection method according to another embodiment of the present application.

Fig. 5 is a block diagram illustrating a configuration of a fault detection apparatus according to an embodiment of the present application.

FIG. 6 sets forth a block diagram of an exemplary hardware architecture of computing devices capable of implementing the fault detection methods and apparatus according to embodiments of the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Through statistics of the existing test data, it can be known that the intermittent fault is very easy to cause transient failure of a circuit system. Generally, the occurrence number of intermittent faults accounts for 70-80% of the occurrence number of all faults, and when the intermittent faults are determined to occur and are in an active period, a circuit system can generate an error result, so that task interruption in the circuit system is easily caused, and false alarm can be caused; when intermittent faults occur, the intermittent faults disappear by restarting the circuit system, but the generation reasons of the intermittent faults are difficult to locate; when it is determined that the intermittent fault disappears, the circuit system fault outputs a correct result, but the cause of the intermittent fault cannot be accurately detected, which results in waste of resources of the circuit system. In a communication system, the most direct influence of intermittent faults on the communication system is to reduce the communication quality of communication equipment and shorten the service life of the communication equipment.

In a conventional processing method, a signal processing method based on Ensemble Empirical Mode Decomposition (EEMD) is used to detect a fault in a circuit system. However, in the signal processing method based on the EEMD, after the signal is averaged and decomposed, the obtained eigenmode Function (IMF) component does not completely conform to the definition of the eigenmode Function in the EEMD; moreover, only when the decomposition times are large enough, the added white noise has small enough influence on the signal decomposition, but a noise signal still exists, so that the accuracy of the fault type judgment is influenced. Moreover, the number of signal decompositions is too large, which also results in an extension of the processing time,

fig. 1 shows a schematic flow chart of a fault detection method according to an embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in fig. 1, the fault detection method in the embodiment of the present application may include the following steps.

Step S101, simulating the circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit.

Different simulation software can be adopted to simulate the circuit to be tested, so that a simulation circuit corresponding to the circuit to be tested is obtained. The simulation circuit can simulate the circuit to be tested to obtain different working states corresponding to the circuit to be tested, and the different working states corresponding to the circuit to be tested are represented through the simulation state of the simulation circuit, so that repeated overhaul of the circuit to be tested can be avoided, and damage to the circuit to be tested is avoided.

And S102, carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to the simulation state.

The simulation circuit can be subjected to signal acquisition according to different simulation states, and simulation signal sets in different simulation states are obtained.

For example, in the case where the simulation state is a normal state, a normal signal set in the normal state may be obtained, the normal signal set including a plurality of normal signals; in the case where the simulation state is a fault state, a fault information set in the fault state may be obtained, the fault information set including a plurality of fault signals.

By collecting simulation signal sets in different simulation states, signal samples can be enriched; the signal samples in different states are used, the working conditions of the simulation circuit in different simulation states can be observed more visually, and therefore the detection accuracy of the fault of the circuit to be detected is improved.

Step S103, detecting the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determining the fault type of the to-be-detected circuit.

The preset detection algorithm is a preset circuit detection algorithm.

The simulation signals in the simulation signal sets under different simulation states are processed by the preset detection algorithm, detection results corresponding to the different simulation states can be obtained, and then the fault state of the circuit to be detected can be quickly judged by comparing the different detection results, so that the fault detection speed of the circuit to be detected can be accelerated, the accuracy of the circuit to be detected in fault detection is improved, and unnecessary maintenance cost is reduced.

In the embodiment, the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit are obtained by simulating the circuit to be tested, so that the overhaul of the circuit to be tested is reduced, and the damage to the circuit to be tested is avoided; carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to a simulation state so as to enrich signal samples and improve the detection accuracy of the circuit to be detected; according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, the to-be-detected signal of the to-be-detected circuit is detected, the fault type of the to-be-detected circuit is determined, the fault detection accuracy of the to-be-detected circuit is improved, and unnecessary maintenance cost is reduced.

Fig. 2 is a schematic flowchart illustrating a fault detection method according to another embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in fig. 2, the fault detection method in the embodiment of the present application may include the following steps.

Step S201, simulating the circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit.

The simulation method includes the following steps of simulating a circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit, wherein the simulation method includes the following steps: simulating a circuit to be tested according to a simulation algorithm to obtain a simulation circuit, wherein the simulation circuit comprises switches arranged at an input end and an output end of a simulation component; acquiring the switching time and the switching frequency of a switch in the simulation circuit; and simulating the working state of the circuit to be tested according to the switching time and the switching frequency to obtain the simulation state of the simulation circuit.

For example, a switch is connected in series with each of the input end and the output end of a component which may have a fault, and then the circuit working conditions of the circuit to be tested in different working states are simulated by changing the switching time and the switching frequency of each switch. Then, by configuring parameters of each switch (for example, parameters such as the on time of the switch, the switching frequency, and the like), the circuit to be tested in different working states is simulated, and the simulation circuit in different working states is obtained.

The simulation circuit simulates the working conditions of the circuit to be tested under different working states, the detection of the circuit to be tested can be rapidly realized, and the damage to the circuit to be tested caused by misoperation is avoided.

In some implementations, the operating state of the circuit under test or the simulation state of the simulation circuit includes: any one or more of a normal state, an intermittent fault state and a permanent fault state; the simulation signal set corresponding to the simulation state comprises: any one or more of a normal simulation signal set, an intermittent fault simulation signal set and a permanent fault simulation signal set.

It should be noted that the above description is only for example on the working state of the circuit to be tested or the simulation state of the simulation circuit, and other non-described working states of the circuit to be tested or simulation states of the simulation circuit are also within the protection scope of the present application, and may be specifically set according to specific situations, and are not described herein again.

Under the condition that the simulation circuit is determined to be in any one or more of a normal state, an intermittent fault state and a permanent fault state, signal acquisition is carried out on the simulation circuit, the circuit to be detected can be observed visually, and any one or more of a normal simulation signal set, an intermittent fault simulation signal set and a permanent fault simulation signal set are obtained, so that various simulation signals are obtained, the working conditions of different simulation states of the simulation circuit are reflected, preparation is made for subsequent processing of simulation signals in the simulation signal set, and the detection speed of the circuit to be detected is accelerated.

Step S202, signal acquisition is carried out on the simulation circuit at a preset frequency, and a simulation signal set corresponding to a simulation state is obtained.

The preset frequency comprises a switching frequency in the simulation circuit.

It should be noted that the preset frequency needs to be kept consistent with the working frequency of the circuit to be tested, for example, the preset frequency is on/off 5 times per minute, and then the switching frequency in the simulation circuit is also on/off 5 times per minute, so as to ensure that the working conditions of the simulation circuit and the circuit to be tested are kept consistent; furthermore, the characteristics of the circuit to be tested in different working states can be accurately reflected through a simulation signal set obtained by signal acquisition of the simulation circuit.

Step S203, detecting the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determining the fault type of the to-be-detected circuit.

It should be noted that step S203 in this embodiment is the same as step S103 in the previous embodiment, and is not repeated herein.

In the embodiment, the circuit to be tested is simulated according to the simulation algorithm, so that the simulation circuit comprising the switches arranged at the input end and the output end of the simulation component is obtained, the circuit to be tested can be virtualized, and the debugging of the circuit to be tested is facilitated; acquiring the switching time and the switching frequency of a switch in the simulation circuit, and simulating the working state of the circuit to be tested according to the switching time and the switching frequency to obtain the simulation state of the simulation circuit, so that the simulation circuit can truly and accurately reflect different working states of the circuit to be tested; carrying out signal acquisition on the simulation circuit at a preset frequency to obtain a simulation signal set corresponding to a simulation state, so that the working conditions of the simulation circuit and a circuit to be tested can be kept consistent; through simulation signal sets corresponding to different simulation states, the characteristics of the circuit to be detected in different working states can be accurately reflected, and detection samples are enriched; according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, the to-be-detected signal of the to-be-detected circuit is detected, the fault type of the to-be-detected circuit is determined, the fault detection accuracy of the to-be-detected circuit is improved, and unnecessary maintenance cost is reduced.

Fig. 3 is a schematic flowchart illustrating a fault detection method according to still another embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in fig. 3, the fault detection method in the embodiment of the present application may include the following steps.

Step S301, simulating the circuit to be tested to obtain the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit.

Step S302, signal collection is carried out on the simulation circuit, and a simulation signal set corresponding to the simulation state is obtained.

It should be noted that steps S301 to S302 in this embodiment are the same as steps S101 to S102 in the embodiment shown in fig. 1, and are not repeated herein.

Step S303, performing empirical mode decomposition on the signal to be measured of the circuit to be measured to obtain a vector to be measured.

The empirical mode decomposition is a method for decomposing signals according to the time scale characteristics of data, any basis function is not required to be preset, and the empirical mode decomposition method is particularly suitable for analyzing and processing nonlinear and non-stationary signals.

By performing empirical mode decomposition on a signal to be detected of a circuit to be detected, an IMF component corresponding to the signal to be detected can be obtained, and the IMF component can enable the instantaneous frequency of the signal to be detected to be not influenced by specific fluctuation, wherein the specific fluctuation is unnecessary fluctuation formed by asymmetric waveforms. Then, the IMF component is used as a vector to be detected, so that a signal to be detected can be detected in a more accurate form, and the detection accuracy is improved.

Step S304, performing empirical mode decomposition on the simulation signals in the simulation signal set corresponding to the simulation state to obtain a feature vector matrix corresponding to the simulation state.

The method comprises the steps of carrying out empirical mode decomposition on simulation signals in a simulation signal set corresponding to a simulation state to obtain IMF components corresponding to the simulation signals, so that the simulation signals are presented in a more accurate form, and determining a characteristic vector matrix corresponding to the simulation state according to the IMF components corresponding to the simulation signals, so that the accuracy of the characteristic vector matrix corresponding to the simulation state can be guaranteed, and subsequent processing is facilitated.

Step S305, determining a fault detection model corresponding to the simulation state according to the eigenvector matrix corresponding to the simulation state and a preset detection algorithm.

Wherein, the simulation state comprises: any one or more of a normal state, an intermittent fault state and a permanent fault state.

For example, a preset detection algorithm is adopted to process the eigenvector matrix corresponding to the simulation state to obtain a fault detection model corresponding to the simulation state, that is, any one or more of the following detection models can be obtained: any one or more of a normal state detection model, an intermittent fault state detection model and a permanent fault state detection model.

Through the detection model of the diversity, the detection modes of the simulation circuit in different simulation states are refined, and the detection accuracy of the circuit to be detected can be improved.

In some specific implementations, processing the eigenvector matrix corresponding to the simulation state by using a preset detection algorithm to obtain a fault detection model corresponding to the simulation state includes: and estimating parameters of a preset detection model in the intermittent fault state by adopting a preset detection algorithm until the preset detection model meets a preset convergence condition to obtain the intermittent fault state detection model, wherein the preset detection model comprises a characteristic vector matrix.

The intermittent fault is the most likely fault of a circuit to be detected, parameters of a preset detection model in the intermittent fault state are estimated by adopting a preset detection algorithm, the intermittent fault state detection model can be obtained under the condition that the preset detection model meets a preset convergence condition, and the detection speed of the intermittent fault can be accelerated by adopting the intermittent fault state detection model.

It should be noted that the preset detection model includes a feature vector matrix, the feature vector matrix includes a plurality of IMF components, and the characteristics of the IMF components, that is, the IMF components can make the instantaneous frequency of the signal to be detected not affected by the specific fluctuation, so as to meet the requirement on the stability of the signal to be detected, and further ensure the detection accuracy of the circuit to be detected.

Step S306, inputting the vector to be tested to the fault detection model corresponding to the simulation state, and obtaining the working state probability corresponding to the circuit to be tested.

Wherein, the simulation state comprises: any one or more of a normal state, an intermittent fault state and a permanent fault state. Correspondingly, the probability of the working state corresponding to the circuit under test may include: the probability that the circuit to be tested is in a normal state, the probability that the circuit to be tested is in an intermittent fault state and the probability that the circuit to be tested is in a permanent fault state.

The proportion of the actual working state of the circuit to be tested can be reflected through different working state probabilities, and preparation is made for subsequently determining the fault type of the circuit to be tested.

In some specific implementations, the vector to be tested is input to the fault detection model corresponding to the simulation state to obtain the working state probability corresponding to the circuit to be tested, and the following method can be adopted: and inputting the vector to be tested into the fault detection model corresponding to the simulation state according to a forward-backward algorithm, and obtaining the working state probability corresponding to the circuit to be tested.

It should be noted that the forward-backward algorithm includes a forward probability and a backward probability, for example, the forward probability can be expressed as: inputting the vector to be detected to a fault detection model corresponding to the simulation state at the time 1-t, and obtaining the working state probability corresponding to the circuit to be detected; the backward probability can be expressed as: and inputting the vector to be detected to the fault detection model corresponding to the simulation state from t +1 to the termination time, and obtaining the working state probability corresponding to the circuit to be detected. Wherein t is an integer greater than or equal to 1.

The forward probability and the backward probability are input into the fault detection model corresponding to the simulation state, and the parameter estimation is carried out on the fault detection model corresponding to the simulation state, so that the obtained fault detection model corresponding to the simulation state has higher detection accuracy, the condition that the vector to be detected is input into the fault detection model after the parameter estimation corresponding to different simulation states is ensured, and the obtained working state probability corresponding to the circuit to be detected is more accurate.

Step S307, determining the fault type of the circuit to be tested according to the working state probability corresponding to the circuit to be tested.

Wherein, the operating condition probability that the circuit to be measured corresponds includes: and the likelihood probability is obtained based on the statistical model, and can be used for carrying out statistical processing on the acquired signals through the statistical model, so that the obtained likelihood probability is more accurate.

In some implementations, determining the fault type of the circuit to be tested according to the working state probability corresponding to the circuit to be tested includes: sequencing the probability of the circuit to be tested in a normal state, the probability of the circuit to be tested in an intermittent fault state and the probability of the circuit to be tested in a permanent fault state to obtain a sequencing result; and determining the fault type of the circuit to be tested according to the sequencing result.

For example, if the probability of the circuit to be tested in the normal state is 0.3, the probability of the circuit to be tested in the intermittent fault state is 0.7, and the probability of the circuit to be tested in the permanent fault state is 0.2, the sequencing result is: the working states corresponding to the circuit to be tested are sequentially from high to low: intermittent fault conditions, normal conditions, and permanent fault conditions; then the type of fault for the circuit under test may be determined to be an intermittent fault at this point.

By sequencing the probabilities corresponding to the possible working states of the circuit to be detected, the working state of the circuit to be detected can be clearly shown, the fault type of the circuit to be detected is clear at a glance, the detection speed of the fault type of the circuit to be detected is increased, and the accuracy of fault detection is improved.

In some specific implementations, the empirical mode decomposition is performed on the simulation signals in the simulation signal set corresponding to the simulation state in step S304 to obtain the eigenvector matrix corresponding to the simulation state, which may also be implemented by adopting the following method:

taking the simulation signal in the simulation signal set corresponding to the simulation state as an original signal; processing an original signal according to a preset noise signal to obtain a signal decomposition matrix, wherein the signal decomposition matrix is a matrix corresponding to a simulation state and comprises a plurality of decomposition vectors; and determining a characteristic vector matrix corresponding to the simulation state according to the signal decomposition matrix.

The simulation signal set corresponding to the simulation state may include: a normal simulation signal set, an intermittent fault simulation signal set and a permanent fault simulation signal set.

Respectively carrying out signal acquisition on simulation circuits in a normal state, an intermittent fault state and a permanent fault state, wherein m groups of simulation signal sets are acquired in each state, and simulation signals in each group of simulation signal sets are decomposed, so that the simulation signals in each group of simulation signal sets in each state can be decomposed into j IMF components, and then a signal decomposition matrix comprises: a normal state signal decomposition matrix, an intermittent fault state signal decomposition matrix, and a permanent fault state signal decomposition matrix, each signal decomposition matrix including m rows and j columns of IMF components, wherein m and j are integers greater than or equal to 1. Wherein the lengths of the simulated signals in each set of simulated signals are the same.

The original signals are processed according to the preset noise signals, so that signal decomposition matrixes in different simulation states are obtained, and the characteristics of the signals in each simulation state can be reflected in a multi-dimensional manner; and determining a characteristic vector matrix corresponding to the simulation state according to the signal decomposition matrix so as to enrich the characteristic information of the characteristic vector matrix, ensure that the acquired characteristic information of the signal is better extracted and processed, and facilitate subsequent processing.

In some implementations, the noise signal is preset, including: a first white noise and a second white noise, the second white noise being a noise having the same amplitude as the first white noise and having an opposite direction to the first white noise; processing an original signal according to a preset noise signal to obtain a signal decomposition matrix, comprising: adding first white noise to an original signal to obtain a first signal to be processed; adding second white noise to the original signal to obtain a second signal to be processed; and determining a signal decomposition matrix according to the first signal to be processed and the second signal to be processed.

Wherein the first white noise and the second white noise are each noise whose power spectral density is constant over the entire frequency domain. Random noise with the same energy density at all frequencies is called white noise. If the first white noise is gaussian white noise, the amplitude distribution of the first white noise follows gaussian distribution, and the power spectral density of the first white noise is uniformly distributed; the second white noise is also gaussian white noise but is noise that is the same in magnitude and opposite in direction to the first white noise.

The signal decomposition matrix is determined according to the first signal to be processed and the second signal to be processed, which may be that empirical mode decomposition is performed on the first signal to be processed and the second signal to be processed simultaneously, and then two groups of IMF components after decomposition are averaged to obtain the signal decomposition matrix. Because the first signal to be processed is obtained by adding the first white noise to the original signal, and the second signal to be processed is obtained by adding the second white noise to the original signal, the average value of the two groups of IMF components after decomposition can counteract the white noise added to the signal, avoid the influence of the white noise on the circuit detection, and improve the accuracy of the judgment on the fault type of the circuit to be detected.

In some implementations, determining the eigenvector matrix corresponding to the simulation state according to the signal decomposition matrix includes: taking the energy entropy of the decomposition vector in the signal decomposition matrix as a characteristic vector, wherein the energy entropy of the decomposition vector reflects the frequency band energy information of the signal to be processed; and determining a characteristic vector matrix corresponding to the simulation state according to the characteristic vector.

And the energy entropy of the decomposition vector reflects the frequency band energy information of the signal to be processed. Under the condition that the frequency band information corresponding to a certain simulation signal is determined to be changed, the change conditions corresponding to different faults can be directly reflected through the IMF component.

The IMF components corresponding to the simulation signals are subjected to energy entropy operation to obtain a characteristic vector matrix, and the fault type of the circuit to be tested can be quickly determined by well reflecting the occurrence conditions of different circuit faults through the characteristic vector matrix.

In some implementations, determining the eigenvector matrix corresponding to the simulation state according to the signal decomposition matrix includes: taking the amplitude of the decomposition vector in the signal decomposition matrix as a feature vector; and determining a characteristic vector matrix corresponding to the simulation state according to the characteristic vector.

Wherein the amplitude of the decomposition vector in the signal decomposition matrix is the absolute value of the maximum value of the decomposition vector occurring at the instant in one period. By taking the amplitude of the decomposition vector in the signal decomposition matrix as the characteristic vector, the change condition of each decomposition vector can be directly obtained; according to the characteristic vectors, the characteristic vector matrix corresponding to the simulation state is determined, the change condition of each characteristic vector in the characteristic vector matrix corresponding to the simulation state can be visually determined, the intuitiveness of the characteristic vector matrix is further ensured, and the detection speed of the circuit to be detected is accelerated.

In some specific implementations, the preset detection algorithm in step S305 includes: a maximum expectation algorithm or a wavelet decomposition algorithm; presetting a detection model, comprising: a discrete hidden Markov model or a back propagation neural network detection model; wherein the parameters of the discrete hidden Markov model comprise: the method comprises the steps of observation sequences, the number of simulation states, state initial probability, a transition probability matrix and an observation probability transition matrix, wherein the observation sequences comprise a characteristic vector matrix.

Wherein, the maximum expectation algorithm may comprise: any one or more of an Expectation-Maximization (EM) algorithm, an EM gradient algorithm and a generalized EM algorithm using Bayesian inference are used. The max-expectation algorithm can be applied to parameter estimation of Gaussian Mixture Model (GMM) and Hidden Markov Model (HMM).

The method takes the form of a characteristic vector matrix as an observation sequence of a discrete hidden Markov model, can ensure that the instantaneous frequency of a signal to be measured is not influenced by specific fluctuation any more, and ensures the stability of the observation sequence. In this embodiment, the number of simulation states may be 3, for example, the simulation states include: normal state, intermittent fault state, and permanent fault state. Through the analysis and processing of the state initial probability, the transition probability matrix and the observation probability transition matrix, the preset detection model gradually tends to be stable until the preset detection model meets the preset convergence condition, and the accuracy of the fault detection models corresponding to different simulation states obtained through training is guaranteed.

For example, the wavelet decomposition algorithm may also be applied to analysis and processing of unstable signals (e.g., simulation signals) to obtain accurate analysis results, thereby facilitating detection of signals to be detected.

The learning process of the propagated neural network includes forward learning and backward learning. In the forward propagation process, an input signal is transmitted from an input layer to an output layer through hidden layer-by-layer processing, and the state of each layer of neurons only affects the state of the next layer of neurons. However, if the desired output value is not obtained at the output layer, an error in the network output is attributed to an error in the connection weight. And reversely propagating the errors of the units of the output layer by layer to the input layer to be distributed to each unit, thereby obtaining the reference errors of the units of each layer so as to adjust the corresponding connection weight, namely, the neural network is reversely propagated. And (3) completing the mapping from the input layer to the output layer by using a process of minimizing a cost function in a learning mode of error back propagation. And the cost function therein may be the sum of the squares of the differences between the expected and actual outputs of the output units in all input modes.

In the application, the wavelet decomposition algorithm is used for processing the eigenvector matrixes corresponding to different simulation states, so that an accurate output signal can be obtained, and the output signal is processed by a back propagation neural network detection model, so that the obtained fault detection model under different simulation states is more accurate.

Fig. 4 is a schematic flow chart illustrating a fault detection method according to another embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in fig. 4, the fault detection method in the embodiment of the present application may include the following steps.

Step S401, collecting voltage signals of a circuit to be tested to obtain a signal set to be tested.

It should be noted that, while step S401 is executed, step S402 is also executed at the same time.

The output voltage of the circuit to be tested is collected, the obtained voltage signals are divided into a plurality of groups of signals to be tested, and the length of the signals to be tested is the same as that of the simulation signals obtained through the simulation circuit.

In the process of signal acquisition of the circuit to be detected, the frequency of the signal acquisition needs to be the same as that of the simulation circuit so as to ensure the consistency of the acquisition signal corresponding to the simulation circuit and the voltage signal corresponding to the circuit to be detected, thereby ensuring that the detection result is more accurate.

Step S402, simulating the circuit to be tested to obtain the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit.

The circuit to be tested is simulated by simulation software, and the following mode can be adopted: the input end and the output end of a component which is possible to have faults are respectively connected with a switch in series, and then the circuit of the circuit to be tested in a normal state, an intermittent fault state and a permanent fault state is simulated by changing the switching time and the switching frequency of each switch.

For example, by configuring parameters of each switch (for example, parameters such as the on time of the switch, the closed-loop time of the switch, the switching frequency, and the like), a circuit to be tested in an intermittent fault state is simulated, and a simulation circuit corresponding to the intermittent fault state is obtained; by setting the on-off of the switch, a circuit to be tested in a normal state and a circuit to be tested in a permanent fault state are simulated, and a simulation circuit corresponding to the normal state and a simulation circuit corresponding to the permanent fault state are obtained.

Step S403, performing signal acquisition on the simulation circuit at a preset frequency to obtain a simulation signal set corresponding to the simulation state.

Setting a preset input signal, inputting the preset input signal into simulation circuits corresponding to different simulation states, and collecting simulation signal sets corresponding to different simulation states through preset test points.

For example, the set of simulated signals can be expressed using equation (1) as:

where i represents the serial number of the simulation state (e.g., i equals 1 indicating a normal state, i equals 2 indicating an intermittent fault state, and i equals 3 indicating a permanent fault state). b represents the group number of the signals collected under different simulation states, and b is an integer greater than or equal to 1. n represents the number of sample points for each set of simulated signals.

Representing the nth simulation signal, y, of the group b acquired in the i-th state _ib A set of simulated signals representing the b-th group acquired in the i-th state.

Step S404, gaussian white noise is added to the simulation signals in the simulation signal set, empirical mode decomposition is carried out on the signals added with the Gaussian white noise, and IMF components corresponding to the simulation signals are obtained.

A first white noise (which may be a gaussian white noise) may be added to the simulation signals in the simulation signal set to obtain a first signal to be processed; then, a second white noise (the second white noise is a white noise signal having the same amplitude as the first white noise but opposite direction) is added to the simulation signals in the simulation signal set to obtain a second signal to be processed.

For example, the simulation signal is set to x (t), and the simulation signal x (t) may be n simulation signals in the formula (1)

And determining a linear signal to represent the variation trend of the simulation signal. A pair of white noises n with equal amplitude but opposite directions _i (t) added to the simulated signal x (t), two sets of signals can be obtained: i.e. the first signal to be processed P _i (t) and a second signal to be processed N _i (t), the specific calculation formula is shown as formula (2):

where i represents the number of the emulated signal x (t), i being an integer greater than or equal to 1.

Then, the first signal P to be processed is processed _i (t) and a second signal to be processed N _i (t) Empirical Mode Decomposition (EMD) was performed. For example, the first signals to be processed P are respectively processed by using the formula (3) _i (t) and a second signal to be processed N _i (t) EMD processing to obtain j IMF components, i.e. j IMF' _ik (t) andj imf ″) _ik (t)。

Wherein k is an integer greater than or equal to 1 and less than or equal to j, j being an integer greater than or equal to 1. And using equation (4) to pair the first signal Pi (t) to be processed and the second signal N to be processed _i The sum of (t) is decomposed 2n times to obtain IMF component of k order, i.e. IMF _k 。

Wherein 2n represents the number of decompositions and i is an integer of 1 or more and j or less.

In some specific implementations, the simulation circuits in the normal state, the intermittent fault state, and the permanent fault state are respectively subjected to signal acquisition, m sets of simulation signals are acquired in each state, and the simulation signals in each set of simulation signals are subjected to the above operation, so that the simulation signals in each set of simulation signal in each state can be decomposed into j IMF components.

Further obtaining IMF characteristic matrix A under 3 states _i As shown in equation (5).

Wherein m represents the number of acquisition groups, and m is an integer greater than or equal to 1; j represents the number of IMF components; i denotes the state number of the emulation circuit, e.g. if i is equal to 1, then A denotes the normal state ₁ Representing a normal state signal decomposition matrix; when i is equal to 2, it represents an intermittent fault state, then A ₂ Representing an intermittent fault condition signal decomposition matrix; when i is equal to 3, indicating a permanent fault condition, then A ₃ Representing a permanent fault status signal decomposition matrix.

Step S405, performing energy entropy operation on IMF components corresponding to the simulation signals to obtain a feature vector matrix.

The energy entropy can reflect the chaos degree of various uncertain factors in the simulation circuit. For example, when the operating state of the simulation circuit changes, the energy entropy of the simulation circuit changes. After the processing of step S404, each obtained IMF component includes frequency band information corresponding to the simulation signal, and when it is determined that the frequency band information corresponding to a certain simulation signal is changed, the change conditions corresponding to different faults can be directly reflected through the IMF component. Therefore, the IMF components corresponding to the simulation signals are subjected to energy entropy operation to obtain the characteristic vector matrix, and the occurrence conditions of different circuit faults can be well reflected through the characteristic vector matrix.

For example, the feature vector matrix can be obtained by calculation using the following formula.

1) Setting the simulation signals as x (t), and the IMF component corresponding to each simulation signal as C _K (t), the energy E corresponding to the kth IMF component can be calculated and obtained by adopting the formula (6) _k ：

Wherein k is an integer greater than or equal to 1.

The energy sum E of the j IMF components, as shown in equation (7):

E＝E ₁ +E ₂ +…+E _j (7)

where j represents the number of individual IMF components of each set of simulated signals.

2) Selecting the energy E of each IMF component of the mth group of simulation signals _mj Total energy E of the m-th group of simulation signals _m As the feature vector T _m As shown in equation (8):

wherein j represents the mth group of simulation messagesThe number of IMF components of the number; e _m Expressed as the sum of the energies of the j IMFs of the mth group; e _mj Representing the energy of the jth IMF component of the mth set of simulated signals.

3) According to m eigenvectors T corresponding to m groups of simulation signals _m And determining the eigenvector matrix C of m rows and j columns, as shown in formula (9).

By the method, the characteristic vector matrix C is obtained, the energy of j IMF components corresponding to each group of simulation signals can be clearly seen, so that the specific IMF component energy change can be quickly determined, and the occurrence conditions of different circuit faults can be quickly reflected through the characteristic vector matrix.

Step S406, a maximum expectation algorithm is adopted to estimate parameters of the discrete hidden Markov models in the normal state, the intermittent fault state and the permanent fault state respectively until the discrete hidden Markov models meet preset convergence conditions, and three detection models in three states are obtained.

It should be noted that step S407 is also executed simultaneously with step S406.

Step S407, gaussian white noise is added to the signal to be detected in the signal set to be detected, empirical mode decomposition is carried out on the signal to be detected after the Gaussian white noise is added, and a vector to be detected corresponding to the signal set to be detected is obtained.

It should be noted that, the processing procedure of the to-be-detected signal in the to-be-detected signal set is the same as the processing of the simulation signal in the simulation signal set in step S404, and details are not repeated here.

The vector to be tested corresponding to the signal set to be tested can be represented as an IMF component to be tested.

Step S408, the vector to be detected is respectively input into the normal state detection model, the intermittent fault state detection model and the permanent fault state detection model, and the probability that the circuit to be detected is in the normal state, the probability that the circuit to be detected is in the intermittent fault state and the probability that the circuit to be detected is in the permanent fault state are respectively obtained according to a forward-backward algorithm.

The normal state detection model, the intermittent fault state detection model and the permanent fault state detection model are all obtained by training in the following modes:

respectively estimating parameters of a preset detection Model (e.g., discrete Hidden Markov Model (DHMM) or Back Propagation Neural Network (BPNN) detection Model, etc.) in a normal state by using a preset detection algorithm (e.g., expectation-Maximization algorithm (EM), etc.) until the preset detection Model meets a preset convergence condition, and obtaining a normal state detection Model; estimating parameters of a preset detection model in an intermittent fault state by adopting a preset detection algorithm respectively until the preset detection model meets a preset convergence condition, and obtaining an intermittent fault state detection model; and respectively estimating parameters of a preset detection model in a permanent fault state by adopting a preset detection algorithm until the preset detection model meets a preset convergence condition, and obtaining the permanent fault state detection model.

The DHMM can be expressed by the following formula (10):

λ＝(A，B，π，N，M) (10)

wherein λ represents DHMM; n represents the number of states (e.g., N equals 3 for the present embodiment including the normal state, intermittent fault state, and permanent fault state); m represents the number of observations corresponding to each state; pi represents the initial probability of each state; b represents an observation probability transition matrix; a denotes the transition probability matrix between different states. The specific calculation method of the above parameters is as follows:

for example, set M observations to: v ₁ ，V ₂ ，…，V _M Then, the observed value corresponding to the circuit to be measured at time t can be expressed as: o is _t ∈(V ₁ ，V ₂ ，…，V _M ). The transition probability matrix a between different states can be represented by equation (11):

A＝(a _ij ) _N*N (11)

wherein, a _ij State q representing the time t of a circuit to be tested _i State q of transition to time t +1 _j Conditional probability of (a) _ij Can be obtained by calculation using the formula (12).

a _ij ＝P(Q _t+1 ＝q _j |Q _t ＝q _i ) (12)

Wherein Q _t Indicating the state at time t, Q _t+1 Represents the state at the time point of t +1, i and j are integers which are greater than or equal to 1 and less than or equal to N, and N is an integer greater than or equal to 1.

Setting the initial probability of the ith state to pi _i ，π _i Can be expressed by equation (13):

π _i ＝P(Q ₁ ＝q _i ) (13)

the circuit under test is always in a normal state initially, and, in the event that it is determined that N is equal to 3, the initial state probability matrix may be set to

The observation probability transition matrix B can be represented by equation (14):

B＝(b _jk ) _N*M (14)

wherein, b _jk ＝P(O _t ＝v _k |Q _t ＝q _j ) I.e. b _jk Representing the state q of the circuit under test at time t _j In the case of (2), the generated observation value v _k Probability of cun-ought. Wherein, b _jk Need to satisfy

And k is an integer of 1 or more and M or less.

In some implementations, a _ij Can also be expressed as xi _t (i, j) can be calculated by using the formula (15):

ξ _t (i，j)＝P(O，O _t ＝q _i ，Q _t+1 ＝q _j |λ) (15)

wherein, O _t Indicating the state, Q, corresponding to the circuit under test at time t _t ∈(q ₁ ，q ₂ ，…，q _N ) Wherein q is ₁ ，q ₂ ，…，q _N Respectively representing a first state, a second state, \8230;, and an Nth state.

Then, based on the forward-backward algorithm, the forward variable alpha in the forward algorithm is converted _t (i) And a backward variable beta in a backward algorithm _t (j) Substituting equation (15) can obtain updated xi _t (i, j), updated ξ _t (i, j) is shown in equation (16):

wherein the forward variable α _t (i)＝P(O ₁ ，O ₂ ，…，0 _t ，q _i ＝S _i |λ)，S _i Representing hidden states, backward variable beta _t (j)＝P(O _t+1 ，0 _t+2 ，…，O _T |q _t ＝S _i ，λ)。

Further, the circuit to be tested is at q at time t _i Probability xi of a state _t (i) As shown in equation (17):

note that, the backward variable (also referred to as local probability) β _t (j) Showing that the DHMM is known and the circuit to be tested is in a hidden state S at the moment t _i The probability of a local observation sequence from time T +1 to the termination time T.

Then, the various parameters of the DHMM model are estimated, and the following parameters are obtained: initial probability value

(as shown in equation (18)), a state transition matrix

(as shown in equation (19)) and an observation matrix

(as shown in formula (20))

Wherein, the first and the second end of the pipe are connected with each other,

indicating the desired number of transitions from the ith state to other states,

representing the number of expected values to transition from the ith state to the jth state.

Further, by the initial probability value

State transition matrix

And observation matrix

The model λ in different states is determined, and for example, a normal state detection model, an intermittent failure state detection model, and a permanent failure state detection model are available.

The characteristic vector matrix C is used as an observation sequence, and the EM algorithm is adopted to estimate each parameter of the DHMM until the DHMM models in different states meet the preset convergence condition, so that a normal state detection model, an intermittent fault state detection model and a permanent fault state detection model are obtained, and the probability corresponding to each state is conveniently calculated in the follow-up process.

Step S409, the probability that the circuit to be tested is in a normal state, the probability that the circuit to be tested is in an intermittent fault state and the probability that the circuit to be tested is in a permanent fault state are sequenced, and the state with the maximum probability is determined as the fault type of the circuit to be tested.

In the embodiment, the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit are obtained by simulating the circuit to be tested, so that the overhaul of the circuit to be tested is reduced, and the damage to the circuit to be tested is avoided; carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to a simulation state so as to enrich signal samples and improve the detection accuracy of the circuit to be detected; the acquisition frequency which is the same as the frequency of the simulation circuit is adopted to acquire the voltage signal of the circuit to be detected, so that the consistency of the acquisition signal corresponding to the simulation circuit and the voltage signal corresponding to the circuit to be detected can be ensured, and the detection result is more accurate; gaussian white noise is added to simulation signals in the simulation signal set, empirical mode decomposition is carried out on the signals added with the Gaussian white noise to obtain IMF components corresponding to the simulation signals, energy entropy operation is carried out on the IMF components corresponding to the simulation signals to obtain a characteristic vector matrix, and because the IMF components in the characteristic vector matrix comprise frequency band information corresponding to the simulation signals, the occurrence conditions of different circuit faults can be well reflected through the characteristic vector matrix; then, the characteristic vector matrix is used as an observation sequence, and the EM algorithm is adopted to estimate each parameter of the DHMM until the DHMM models in different states meet the preset convergence condition, so that a normal state detection model, an intermittent fault state detection model and a permanent fault state detection model are obtained; and then according to a forward-backward algorithm, respectively obtaining the probability that the circuit to be tested is in a normal state, the probability that the circuit to be tested is in an intermittent fault state and the probability that the circuit to be tested is in a permanent fault state, so that the state with the highest probability can be used as the fault type of the circuit to be tested, the detection accuracy of the fault type of the circuit to be tested is ensured, and unnecessary maintenance cost is reduced.

According to the simulation signal set corresponding to the simulation state and the preset detection algorithm, the to-be-detected signal of the to-be-detected circuit is detected, the fault type of the to-be-detected circuit is determined, the fault detection accuracy of the to-be-detected circuit is improved, and unnecessary maintenance cost is reduced.

A fault detection device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. Fig. 5 is a block diagram illustrating a configuration of a fault detection apparatus according to an embodiment of the present application. As shown in fig. 5, the fault detection apparatus may include the following modules.

The acquiring module 501 is configured to simulate a circuit to be tested, and acquire a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit; a signal acquisition module 502 configured to perform signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to the simulation state; the fault detection module 503 is configured to detect a to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determine a fault type of the to-be-detected circuit.

According to the fault detection device, the acquisition module simulates the circuit to be detected to obtain the simulation circuit corresponding to the circuit to be detected and the simulation state of the simulation circuit, so that the maintenance of the circuit to be detected is reduced, and the damage to the circuit to be detected is avoided; the signal acquisition module is used for acquiring signals of the simulation circuit to obtain a simulation signal set corresponding to the simulation state so as to enrich signal samples and improve the detection accuracy of the circuit to be detected; and detecting the to-be-detected signal of the to-be-detected circuit by using the fault detection module according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, determining the fault type of the to-be-detected circuit, improving the accuracy of fault detection of the to-be-detected circuit and reducing unnecessary maintenance cost.

It is to be understood that this invention is not limited to the particular arrangements and instrumentalities shown in the attached drawings. For convenience and brevity of description, detailed description of a known method is omitted here, and for the specific working processes of the system, the module and the unit described above, reference may be made to corresponding processes in the foregoing method embodiments, which are not described herein again.

FIG. 6 illustrates a block diagram of an exemplary hardware architecture of a computing device capable of implementing the fault detection method and apparatus in accordance with embodiments of the present invention.

As shown in fig. 6, computing device 600 includes an input device 601, an input interface 602, a central processor 603, a memory 604, an output interface 605, and an output device 606. The input interface 602, the central processing unit 603, the memory 604, and the output interface 605 are connected to each other via a bus 607, and the input device 601 and the output device 606 are connected to the bus 607 via the input interface 602 and the output interface 605, respectively, and further connected to other components of the computing device 600.

Specifically, the input device 601 receives input information from the outside, and transmits the input information to the central processor 603 through the input interface 602; the central processor 603 processes input information based on computer-executable instructions stored in the memory 604 to generate output information, stores the output information temporarily or permanently in the memory 604, and then transmits the output information to the output device 606 through the output interface 605; output device 606 outputs output information to the exterior of computing device 600 for use by a user.

In one embodiment, the computing device shown in fig. 6 may be implemented as an electronic device that may include: a memory configured to store a program; a processor configured to execute the program stored in the memory to perform the fault detection method described in the above embodiments.

In one embodiment, the computing device shown in fig. 6 may be implemented as a fault detection system that may include: a memory configured to store a program; a processor configured to execute the program stored in the memory to perform the fault detection method described in the above embodiments.

The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application. In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.

Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages.

The block diagrams of any logic flows in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read Only Memory (ROM), random Access Memory (RAM), optical storage devices and systems (digital versatile disks, DVDs, or CD discs), etc. The computer readable medium may include a non-transitory storage medium. The data processor may be of any type suitable to the local technical environment, such as but not limited to general purpose computers, special purpose computers, microprocessors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.

The foregoing has provided by way of exemplary and non-limiting examples a detailed description of exemplary embodiments of the present application. Various modifications and adaptations to the foregoing embodiments may become apparent to those skilled in the relevant arts in view of the following drawings and the appended claims without departing from the scope of the invention. Therefore, the proper scope of the invention is to be determined according to the claims.

Claims

1. A method of fault detection, the method comprising:

simulating a circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit;

carrying out signal acquisition on the simulation circuit to obtain a simulation signal set corresponding to the simulation state;

and detecting the to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determining the fault type of the to-be-detected circuit.

2. The method of claim 1, wherein the simulating the circuit to be tested to obtain the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit comprises:

simulating the circuit to be tested according to a simulation algorithm to obtain the simulation circuit, wherein the simulation circuit comprises switches arranged at the input end and the output end of a simulation component;

acquiring the switching time and the switching frequency of the switch in the simulation circuit;

and simulating the working state of the circuit to be tested according to the switching time and the switching frequency to obtain the simulation state of the simulation circuit.

3. The method of claim 2, wherein the operating state of the circuit under test or the simulation state of the simulation circuit comprises: any one or more of a normal state, an intermittent fault state and a permanent fault state;

the simulation signal set corresponding to the simulation state comprises: any one or more of a normal simulation signal set, an intermittent fault simulation signal set and a permanent fault simulation signal set.

4. The method of claim 1, wherein the acquiring the signals of the simulation circuit to obtain the simulation signal set corresponding to the simulation state comprises:

and carrying out signal acquisition on the simulation circuit at a preset frequency to obtain a simulation signal set corresponding to the simulation state, wherein the preset frequency comprises a switching frequency in the simulation circuit.

5. The method according to claim 1, wherein the detecting the signal to be detected of the circuit to be detected according to the simulation signal set corresponding to the simulation state and a preset detection algorithm to determine the fault type of the circuit to be detected comprises:

performing empirical mode decomposition on a signal to be detected of the circuit to be detected to obtain a vector to be detected;

performing empirical mode decomposition on simulation signals in a simulation signal set corresponding to the simulation state to obtain a feature vector matrix corresponding to the simulation state;

determining a fault detection model corresponding to the simulation state according to the eigenvector matrix corresponding to the simulation state and the preset detection algorithm;

inputting the vector to be tested to a fault detection model corresponding to the simulation state to obtain the working state probability corresponding to the circuit to be tested;

and determining the fault type of the circuit to be tested according to the working state probability corresponding to the circuit to be tested.

6. The method according to claim 5, wherein performing empirical mode decomposition on the simulation signals in the set of simulation signals corresponding to the simulation state to obtain the eigenvector matrix corresponding to the simulation state comprises:

taking the simulation signal in the simulation signal set corresponding to the simulation state as an original signal;

processing the original signal according to a preset noise signal to obtain a signal decomposition matrix, wherein the signal decomposition matrix is a matrix corresponding to the simulation state and comprises a plurality of decomposition vectors;

and determining a characteristic vector matrix corresponding to the simulation state according to the signal decomposition matrix.

7. The method of claim 6, wherein the presetting the noise signal comprises: a first white noise and a second white noise, the second white noise being a noise having the same amplitude as the first white noise and an opposite direction to the first white noise;

the processing the original signal according to a preset noise signal to obtain a signal decomposition matrix includes:

adding first white noise to the original signal to obtain a first signal to be processed;

adding second white noise to the original signal to obtain a second signal to be processed;

and determining a signal decomposition matrix according to the first signal to be processed and the second signal to be processed.

8. The method of claim 6, wherein determining the eigenvector matrix corresponding to the simulation state from the signal decomposition matrix comprises:

taking the energy entropy of the decomposition vector in the signal decomposition matrix as a characteristic vector, wherein the energy entropy of the decomposition vector reflects the frequency band energy information of the signal to be processed;

and determining a characteristic vector matrix corresponding to the simulation state according to the characteristic vector.

9. The method of claim 6, wherein determining the eigenvector matrix corresponding to the simulation state from the signal decomposition matrix comprises:

taking the amplitude of the decomposition vector in the signal decomposition matrix as a feature vector;

10. The method according to claim 5, wherein the determining the fault detection model corresponding to the simulation state according to the eigenvector matrix corresponding to the simulation state and the preset detection algorithm comprises:

processing the characteristic vector matrix corresponding to the simulation state by adopting the preset detection algorithm to obtain a fault detection model corresponding to the simulation state;

the fault detection model corresponding to the simulation state comprises: any one or more of a normal state detection model, an intermittent fault state detection model and a permanent fault state detection model.

11. The method according to claim 10, wherein the processing the eigenvector matrix corresponding to the simulation state by using the preset detection algorithm to obtain the fault detection model corresponding to the simulation state comprises:

and estimating parameters of a preset detection model in the intermittent fault state by adopting the preset detection algorithm until the preset detection model meets a preset convergence condition, so as to obtain the intermittent fault state detection model, wherein the preset detection model comprises the eigenvector matrix.

12. The method of claim 11, wherein the predetermined detection algorithm comprises: a maximum expectation algorithm or a wavelet decomposition algorithm;

the preset detection model comprises: a discrete hidden Markov model or a back propagation neural network detection model; wherein the parameters of the discrete hidden Markov model comprise: observation sequence, the number of the simulation states, state initial probability, transition probability matrix and observation probability transition matrix, wherein the observation sequence comprises the characteristic vector matrix.

13. The method according to any one of claims 10 to 12, wherein the inputting the vector to be tested to the fault detection model corresponding to the simulation state to obtain the operating state probability corresponding to the circuit to be tested comprises:

and inputting the vector to be tested to the fault detection model corresponding to the simulation state according to a forward-backward algorithm to obtain the working state probability corresponding to the circuit to be tested.

14. The method of claim 13, wherein the probability of the operating state corresponding to the circuit under test comprises: the probability that the circuit to be tested is in the normal state, the probability that the circuit to be tested is in the intermittent fault state and the probability that the circuit to be tested is in the permanent fault state;

determining the fault type of the circuit to be tested according to the working state probability corresponding to the circuit to be tested, wherein the determining comprises the following steps:

sequencing the probability that the circuit to be tested is in the normal state, the probability that the circuit to be tested is in the intermittent fault state and the probability that the circuit to be tested is in the permanent fault state to obtain a sequencing result;

and determining the fault type of the circuit to be tested according to the sequencing result.

15. A fault detection device, comprising:

the acquisition module is configured to simulate a circuit to be tested, and acquire a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit;

the signal acquisition module is configured to acquire signals of the simulation circuit and obtain a simulation signal set corresponding to the simulation state;

and the fault detection module is configured to detect a to-be-detected signal of the to-be-detected circuit according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determine the fault type of the to-be-detected circuit.

16. An electronic device, comprising:

one or more processors;

memory having one or more programs stored thereon that, when executed by the one or more processors, cause the one or more processors to implement the fault detection method of any of claims 1-14.

17. A readable storage medium, characterized in that the readable storage medium stores a computer program which, when executed by a processor, implements the fault detection method according to any one of claims 1-14.