WO2023274121A1 - Fault detection method and apparatus, and electronic device and computer-readable storage medium - Google Patents

Abstract

Provided in the present application are a fault detection method, a fault detection apparatus, and an electronic device and a computer-readable storage medium. The fault detection method comprises: performing simulation on a circuit to be tested, so as to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit; performing signal collection on the simulation circuit, so as to obtain a simulation signal set corresponding to the simulation state; and according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, performing detection on a signal under test of the circuit to be tested, so as to determine a fault type of the circuit to be tested.

Description

Fault detection method and device, electronic device, and computer-readable storage medium

Cross References to Related Applications

This application claims priority to Chinese Patent Application No. 202110719858.3 filed on June 28, 2021, the contents of which are hereby incorporated by reference in their entirety.

technical field

The present application relates to the technical field of detection, and in particular to a fault detection method, a fault detection device, electronic equipment, and a computer-readable storage medium.

Background technique

With the improvement of the detection technology, the detection rate of the permanent fault of the circuit system is getting higher and higher, while the detection rate of the intermittent fault of the circuit system and the change of the maintenance cost are relatively small. The intermittent failure of the circuit system is a kind of intermittent and unpredictable failure that appears and disappears randomly. For example, after the intermittent failure occurs and lasts for a period of time, the circuit system resumes its execution ability without any corrective maintenance operations.

When it is determined that intermittent faults occur and are in an active period, the circuit system will produce wrong results, which will easily lead to interruption of tasks in the circuit system and cause false alarms; when it is determined that intermittent faults disappear, the circuit system will output correct results , but cannot accurately detect the cause of intermittent faults, resulting in a waste of circuit system resources.

public content

An embodiment of the present application provides a fault detection method, including: simulating the circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit; collecting signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state; And according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, the signal to be tested of the circuit to be tested is detected, and the fault type of the circuit to be tested is determined.

An embodiment of the present application provides a fault detection device, including: an acquisition module configured to simulate a circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit; a signal acquisition module configured to perform signal processing on the simulation circuit Acquisition, obtaining a simulation signal set corresponding to the simulation state; and a fault detection module configured to detect the signal to be tested of the circuit to be tested according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determine the fault type of the circuit to be tested.

An embodiment of the present application provides an electronic device, including: one or more processors; and a memory on which one or more computer programs are stored. When the one or more computer programs are executed by the one or more processors, One or more processors are made to implement the fault detection method in the embodiment of the present application.

An embodiment of the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the fault detection method in the embodiment of the present application is implemented.

Regarding the above embodiments and other aspects of the present application and their implementation, more descriptions are provided in the description of the drawings, the detailed description and the claims.

Description of drawings

FIG. 1 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application.

FIG. 2 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application.

FIG. 3 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application.

Fig. 4 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application.

FIG. 5 shows a structural diagram of a fault detection device provided by an embodiment of the present application.

FIG. 6 shows a structural diagram of an exemplary hardware architecture of a computing device capable of implementing the fault detection method and apparatus according to the embodiments of the present application.

detailed description

In order to make the purpose, technical solution and advantages of the application clearer, the embodiments of the application will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

Through the statistics of the existing test data, it can be known that intermittent faults can easily cause short-term failure of the circuit system. In general, the number of intermittent faults accounts for 70% to 80% of all faults. When it is determined that intermittent faults occur and are active, the circuit system will produce wrong results, which will easily lead to the interruption of tasks in the circuit system. , and will cause false alarms; in the case of intermittent faults, restarting the circuit system will make the intermittent faults disappear, but it is difficult to locate the cause of the intermittent faults; in the case of determining that the intermittent faults disappear, the circuit system will output the correct result , but cannot accurately detect the cause of intermittent faults, resulting in a waste of circuit system resources. In the communication system, the most direct impact of intermittent faults on the communication system is to reduce the communication quality of communication equipment and shorten the service life of communication equipment.

In some processing methods, a signal processing method based on Ensemble Empirical Mode Decomposition (EEMD) is used to detect faults in the circuit system. However, in the signal processing method based on EEMD, after the signal is averaged and decomposed, the obtained Intrinsic Mode Function (IMF) component does not fully conform to the definition of the Intrinsic Mode Function in EEMD; and , only when the number of decompositions is large enough, the added white noise will have a small enough impact on the signal decomposition, but there will still be noise signals, which will affect the accuracy of the judgment of the fault type. Moreover, too many times of decomposing the signal will also lead to prolongation of the signal processing time.

FIG. 1 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in FIG. 1 , the fault detection method in the embodiment of the present application may include steps S101 to S103.

In step S101, the circuit to be tested is simulated to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit.

Different simulation software can be used to simulate the circuit to be tested, so as to obtain a simulated circuit corresponding to the circuit to be tested. The simulation circuit can simulate the circuit to be tested to obtain different working states corresponding to the circuit to be tested. The simulation state of the simulated circuit is used to represent the different working states of the circuit to be tested, which can avoid multiple inspections of the circuit to be tested, avoid damage to the circuit under test.

Step S102, collecting signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state.

Signal collection can be performed on the simulation circuit according to different simulation states to obtain simulation signal sets under different simulation states.

For example, when the simulation state is a normal state, the normal signal set under the normal state can be obtained, and the normal signal set includes a plurality of normal signals; when the simulation state is a fault state, the fault signal under the fault state can be obtained A set, the set of fault signals includes a plurality of fault signals.

By collecting simulation signal sets in different simulation states, signal samples can be enriched; using signal samples in a variety of different simulation states can more intuitively observe the working conditions of the simulation circuit in different simulation states, thereby improving the performance of the circuit under test. Fault detection accuracy.

Step S103 , according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, detect the signal under test of the circuit under test, and determine the fault type of the circuit under test.

The preset detection algorithm is a preset circuit detection algorithm.

Using the preset detection algorithm to process the simulation signals in the simulation signal set under different simulation states, the detection results corresponding to different simulation states can be obtained, and then the comparison between different detection results can quickly determine the The specific fault state of the circuit can speed up the fault detection speed of the circuit to be tested, improve the accuracy of fault detection of the circuit to be tested, and reduce unnecessary maintenance costs.

In the above-mentioned fault detection method, by simulating the circuit to be tested, the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit are obtained, thereby reducing the maintenance of the circuit to be tested, and avoiding damage to the circuit to be tested; performing signal acquisition on the simulation circuit, Obtain the simulation signal set corresponding to the simulation state to enrich the signal samples and improve the detection accuracy of the circuit fault under test; according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, detect the signal under test of the circuit under test and determine the The fault type of the circuit under test can speed up the fault detection speed of the circuit under test, improve the accuracy of fault detection of the circuit under test, and reduce unnecessary maintenance costs.

FIG. 2 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in FIG. 2 , the fault detection method in the embodiment of the present application may include steps S201 to S203.

In step S201, the circuit to be tested is simulated to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit.

In some embodiments, the emulation of the circuit to be tested and obtaining the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit include: simulating the circuit to be tested according to a simulation algorithm to obtain a simulation circuit, and the simulation circuit includes the switches at the input and output ends of the circuit; obtain the switching time and switching frequency of the switch in the simulation circuit; and simulate the working state of the circuit under test according to the switching time and switching frequency to obtain the simulation state of the simulation circuit.

For example, connect a switch in series at the input end and output end of the component that may be faulty, and then, by changing the switching time and switching frequency of each switch, simulate the circuit working conditions of the circuit under test under different working conditions. Then, by configuring the parameters of each switch (such as the opening time of the switch, the closing time of the switch, and the switching frequency and other parameters), the circuit under test under different working conditions is simulated, and the simulated circuit under different working conditions is obtained.

By simulating the working conditions of the circuit under test under different working conditions through the simulation circuit, the rapid detection of the circuit under test can be realized, and the damage to the circuit under test caused by misoperation can be avoided.

In some embodiments, the working state of the circuit to be tested or the simulation state of the simulation circuit includes: any one or more of normal state, intermittent fault state and permanent fault state; the simulation signal set corresponding to the simulation state includes: normal simulation Any one or more of signal collection, intermittent fault simulation signal collection and permanent fault simulation signal collection.

It should be noted that the above is just an example for the working state of the circuit under test or the simulation state of the simulation circuit, and other unexplained working states of the circuit under test or the simulation state of the simulation circuit are also within the protection scope of the present application. It can be specifically set according to specific situations, and will not be repeated here.

When it is determined that the simulated circuit is in any one or more of the normal state, intermittent fault state and permanent fault state, the signal acquisition of the simulated circuit can be intuitively observed to obtain the normal simulated signal set, intermittent Any one or several of the fault simulation signal set and the permanent fault simulation signal set can be used to obtain a variety of simulation signals, which can reflect the working conditions of the simulation circuit in different simulation states, and make a contribution to the subsequent processing of the simulation signals in the simulation signal set. Get ready to speed up detection of your circuit under test.

In step S202, signal collection is performed on the simulation circuit at a preset frequency to obtain a simulation signal set corresponding to the simulation state.

Preset frequencies include switching frequencies in simulated circuits.

It should be noted that the preset frequency needs to be consistent with the working frequency of the circuit to be tested. For example, if the preset frequency is 5 times per minute, the switching frequency in the simulation circuit is also 5 times per minute to ensure that the simulation The working conditions of the circuit and the circuit under test are consistent; furthermore, the simulation signal set obtained by collecting signals from the simulation circuit can accurately reflect the characteristics of the circuit under test under different working conditions.

Step S203 , according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, detect the signal under test of the circuit under test, and determine the fault type of the circuit under test.

It should be noted that step S203 in the fault detection method shown in FIG. 2 is the same as step S103 in the fault detection method shown in FIG. 1 above, and will not be repeated here.

In the above fault detection method, by simulating the circuit to be tested according to the simulation algorithm, the simulation circuit including the switches arranged at the input end and the output end of the analog component can be obtained, which can virtualize the circuit to be tested and facilitate the debugging of the circuit to be tested; The switching time and switching frequency of the switch in the simulation circuit, and according to the switching time and the switching frequency, simulate the working state of the circuit to be tested, and obtain the simulation state of the simulation circuit, so that the simulation circuit can truly and accurately reflect the difference of the circuit to be tested The working state of the simulation circuit; the signal collection of the simulation circuit is carried out at a preset frequency to obtain the simulation signal set corresponding to the simulation state, which can ensure that the working conditions of the simulation circuit and the circuit under test are consistent; and through the simulation signal set corresponding to different simulation states, it can Accurately reflect the characteristics of the circuit under test under different working conditions, and enrich the detection samples; according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, detect the signal under test of the circuit under test to determine the fault type of the circuit under test, Improve the accuracy of fault detection of the circuit to be tested and reduce unnecessary maintenance costs.

FIG. 3 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in FIG. 3 , the fault detection method in the embodiment of the present application may include steps S301 to S307.

Step S301, simulating the circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit.

Step S302, collecting signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state.

It should be noted that step S301 and step S302 in the fault detection method shown in FIG. 3 are the same as step S101 and step S102 in the fault detection method shown in FIG. 1 , and will not be repeated here.

Step S303, performing empirical mode decomposition on the signal to be tested of the circuit to be tested to obtain a vector to be tested.

Empirical mode decomposition is a method of signal decomposition based on the time scale characteristics of the data itself, without presetting any basis functions. This empirical mode decomposition method is especially suitable for the analysis and processing of nonlinear and non-stationary signals.

Through empirical mode decomposition of the test signal of the test circuit, the Intrinsic Mode Function (IMF) component corresponding to the test signal can be obtained, and the IMF component can make the instantaneous frequency of the test signal no longer subject to specific fluctuations Specific fluctuations are unwanted fluctuations formed by asymmetrical waveforms. Then, the IMF component is used as the vector to be tested, so that the signal to be tested can be detected in a more accurate form, and the detection accuracy can be improved.

Step S304, performing empirical mode decomposition on the simulation signals in the simulation signal set corresponding to the simulation state to obtain an eigenvector matrix corresponding to the simulation state.

Perform empirical mode decomposition on the simulation signals in the simulation signal set corresponding to the simulation state, and obtain the IMF components corresponding to each simulation signal, so that the simulation signals can be presented in a more accurate form, and determine the simulation state according to the IMF components corresponding to each simulation signal The corresponding eigenvector matrix can ensure the accuracy of the eigenvector matrix corresponding to the simulation state and facilitate subsequent processing.

Step S305, according to the eigenvector matrix corresponding to the simulation state and the preset detection algorithm, determine the fault detection model corresponding to the simulation state.

The simulation state includes any one or more of normal state, intermittent fault state and permanent fault state.

For example, the preset detection algorithm is used to process the eigenvector matrix corresponding to the simulation state to obtain the fault detection model corresponding to the simulation state, that is, any one or several of the following detection models can be obtained: normal state detection model, intermittent Faulty state detection model and permanent faulty state detection model.

Through a variety of detection models, the detection methods of the simulation circuit in different simulation states can be refined to improve the detection accuracy of the circuit to be tested.

In some embodiments, the adopting the preset detection algorithm to process the eigenvector matrix corresponding to the simulation state, and obtaining the fault detection model corresponding to the simulation state includes: adopting the preset detection algorithm to perform preset detection under the intermittent fault state The parameters of the model are estimated until the preset detection model satisfies the preset convergence condition, and the intermittent fault state detection model is obtained. The preset detection model includes an eigenvector matrix.

Intermittent faults are the most likely faults in the circuit to be tested. By using the preset detection algorithm, the parameters of the preset detection model under the intermittent fault state are estimated until the preset detection model meets the preset convergence conditions. An intermittent fault state detection model is obtained, and the detection speed of intermittent faults can be accelerated by using the intermittent fault state detection model.

It should be noted that the preset detection model includes an eigenvector matrix, and the eigenvector matrix includes a plurality of IMF components. The characteristics of the IMF components can be used, that is, the instantaneous frequency of the signal to be tested can no longer be affected by specific fluctuations through the IMF components. , to meet the stability requirements of the signal to be tested, thereby ensuring the detection accuracy of the circuit to be tested.

Step S306, input the vector to be tested into the fault detection model corresponding to the simulation state, and obtain the working state probability corresponding to the circuit to be tested.

The simulation state includes any one or more of normal state, intermittent fault state and permanent fault state. Correspondingly, the working state probability corresponding to the circuit to be tested may include: the probability that the circuit to be tested is in a normal state, the probability that the circuit to be tested is in an intermittent fault state, and the probability that the circuit to be tested is in a permanent fault state. kind.

Through different working state probabilities, it can reflect the proportion of the actual working state of the circuit under test, and prepare for the subsequent determination of the fault type of the circuit under test.

In some implementations, the input of the vector to be tested into the fault detection model corresponding to the simulation state, and obtaining the probability of the working state corresponding to the circuit to be tested can also be implemented in the following manner: according to the forward-backward algorithm, the vector to be tested is Input to the fault detection model corresponding to the simulation state to obtain the working state probability corresponding to the circuit to be tested.

It should be noted that the forward-backward algorithm includes forward probability and backward probability. For example, the forward probability can be expressed as: at time 1 to t, the vector to be tested is input into the fault detection model corresponding to the simulation state, so The obtained probability of the working state corresponding to the circuit under test; the backward probability can be expressed as: from t+1 to the termination moment, input the vector to be tested into the fault detection model corresponding to the simulation state, and obtain the corresponding working state of the circuit under test probability. t is an integer greater than or equal to 1.

By inputting the forward probability and backward probability into the fault detection model corresponding to the simulation state, and estimating the parameters of the fault detection model corresponding to the simulation state, the obtained fault detection model corresponding to the simulation state has higher detection accuracy , so as to ensure that the vectors to be tested are input into the fault detection model after parameter estimation corresponding to different simulation states, and the obtained working state probability corresponding to the circuit to be tested is more accurate.

Step S307: Determine the fault type of the circuit to be tested according to the working state probability corresponding to the circuit to be tested.

The working state probability corresponding to the circuit to be tested includes: likelihood probability, which is a probability obtained based on a statistical model, and the collected signal can be statistically processed through the statistical model to ensure that the obtained likelihood probability is more accurate.

In some embodiments, the determination of the fault type of the circuit under test according to the probability of the working state corresponding to the circuit under test includes: the probability that the circuit under test is in a normal state, the probability that the circuit under test is in an intermittent fault state, and the probability that the circuit under test is in a fault state. The probability of the permanent fault state is sorted to obtain the sorting result; and according to the sorting result, the fault type of the circuit to be tested is determined.

For example, the probability that the circuit to be tested is in a normal state is 0.3, the probability that the circuit to be tested is in an intermittent fault state is 0.7, and the probability that the circuit to be tested is in a permanent fault state is 0.2, then the sorting result is: the corresponding working state probability of the circuit to be tested The order from high to low is: intermittent fault state, normal state and permanent fault state; then it can be determined that the fault type of the circuit under test is intermittent fault at this time.

By sorting the probabilities corresponding to the possible working states of the circuit to be tested, it is possible to clearly show the specific working state of the circuit to be tested, so that the fault type of the circuit to be tested is clear at a glance, and the detection speed of the fault type of the circuit to be tested is accelerated. Improved accuracy of fault detection.

In some implementation manners, step S304 may also be implemented in the following manner:

The simulation signal in the simulation signal set corresponding to the simulation state is used as the original signal; the original signal is processed according to the preset noise signal, and the signal decomposition matrix is obtained. The signal decomposition matrix is a matrix corresponding to the simulation state, and the signal decomposition matrix includes multiple decompositions vector; and according to the signal decomposition matrix, determine the eigenvector matrix corresponding to the simulation state.

The simulated signal set corresponding to the simulated state may include: a normal simulated signal set, an intermittent fault simulated signal set, and a permanent fault simulated signal set.

Collect signals from the simulation circuits in normal state, intermittent fault state and permanent fault state respectively, collect m sets of simulation signal sets for each state of simulation circuit, and decompose the simulation signals in each set of simulation signal sets, so that So that the simulation signals in each group of simulation signal sets in each state can be decomposed into j IMF components, the signal decomposition matrix includes: normal state signal decomposition matrix, intermittent fault state signal decomposition matrix and permanent fault state signal decomposition Matrix, the signal decomposition matrix corresponding to each state includes IMF components with m rows and j columns, where m and j are integers greater than or equal to 1. The lengths of the simulation signals in each simulation signal set are the same.

By processing the original signal according to the preset noise signal, the signal decomposition matrix under different simulation states can be obtained, which can reflect the characteristics of the signal under each simulation state in multiple dimensions; and according to the signal decomposition matrix, the eigenvector matrix corresponding to the simulation state can be determined , so that the characteristic information of the eigenvector matrix is richer, and the characteristic information of the collected signal is ensured to be better extracted and processed to facilitate subsequent processing.

In some implementations, the preset noise signal includes: first white noise and second white noise, the second white noise is noise with the same amplitude and opposite direction to the first white noise; the preset noise signal according to Processing the original signal to obtain the signal decomposition matrix includes: adding first white noise to the original signal to obtain the first signal to be processed; adding second white noise to the original signal to obtain the second signal to be processed; and according to the first signal to be processed signal and the second signal to be processed, and determine a signal decomposition matrix.

Both the first white noise and the second white noise are noises whose power spectral density is constant in the entire frequency domain. Random noise with the same energy density at all frequencies is called white noise. If the first white noise is Gaussian white noise, that is, the amplitude distribution of the first white noise obeys Gaussian distribution, and the power spectral density of the first white noise is evenly distributed; then the second white noise is also Gaussian white noise, but the second The white noise is noise having the same amplitude and opposite direction to the first white noise.

The determination of the signal decomposition matrix based on the first signal to be processed and the second signal to be processed may be to perform empirical mode decomposition on the first signal to be processed and the second signal to be processed at the same time, and then analyze the two groups obtained after the decomposition The IMF components are averaged to obtain a signal decomposition matrix. Since the first signal to be processed is the signal obtained by adding the first white noise to the original signal, and the second signal to be processed is the signal obtained by adding the second white noise to the original signal, therefore, the two sets of IMF components obtained after decomposition The average value can offset the white noise added to the original signal, avoid the influence of white noise on the circuit detection, and improve the accuracy of the judgment of the fault type of the circuit under test.

In some embodiments, the determining the eigenvector matrix corresponding to the simulation state according to the signal decomposition matrix includes: using the energy entropy of the decomposition vector in the signal decomposition matrix as the eigenvector, and the energy entropy of the decomposition vector reflects the frequency band energy of the signal to be processed information; and according to the eigenvectors, determine the eigenvector matrix corresponding to the simulation state.

The energy entropy of the decomposition vector reflects the frequency band energy information of the signal to be processed. When it is determined that the frequency band information corresponding to a certain simulated signal has changed, the IMF component can directly reflect the corresponding changes of different faults.

By calculating the energy entropy of the IMF components corresponding to each simulation signal, the eigenvector matrix is obtained, which can well reflect the occurrence of different circuit faults through the eigenvector matrix, and quickly determine the fault type of the circuit to be tested.

In some embodiments, the determining the eigenvector matrix corresponding to the simulation state according to the signal decomposition matrix includes: using the magnitude of the decomposition vector in the signal decomposition matrix as the eigenvector; and determining the eigenvector corresponding to the simulation state according to the eigenvector matrix.

The magnitude of the decomposition vector in the signal decomposition matrix is the absolute value of the maximum value of the decomposition vector appearing instantaneously within one cycle. By using the magnitude of the decomposition vector in the signal decomposition matrix as the eigenvector, the change of each decomposition vector can be directly obtained; according to the eigenvector, the eigenvector matrix corresponding to the simulation state can be determined intuitively. The changes of each eigenvector in the eigenvector, thereby ensuring the intuitiveness of the eigenvector matrix, and speeding up the detection speed of the circuit to be tested.

In some embodiments, the preset detection algorithm in step S305 includes: maximum expectation algorithm or wavelet decomposition algorithm; the preset detection model includes: discrete hidden Markov model or backpropagation neural network detection model; discrete hidden Markov The parameters of the model include: the observation sequence, the number of simulation states, the initial state probability, the transition probability matrix and the observation probability transition matrix, and the observation sequence includes the eigenvector matrix.

The maximum expectation algorithm may include: any one or several of Bayesian inference maximum expectation algorithm (Expectation-Maximization algorithm, EM), EM gradient algorithm and generalized EM algorithm. The expectation-maximization algorithm can be applied to parameter estimation of Gaussian Mixture Model (GMM) and Hidden Markov Model (HMM).

In the form of the eigenvector matrix, as the observation sequence of the discrete hidden Markov model, the instantaneous frequency of the signal to be measured is no longer affected by the specific fluctuation, and the stability of the observation sequence is guaranteed. In the above fault detection method, the number of simulated states may be three, for example, the simulated states include: normal state, intermittent fault state and permanent fault state. Through the analysis and processing of the initial state probability, transition probability matrix and observation probability transition matrix, the preset detection model gradually tends to be stable until the preset detection model meets the preset convergence conditions, ensuring that the different simulation states obtained by training correspond to Accuracy of the fault detection model.

For example, the wavelet decomposition algorithm can also be applied to the analysis and processing of non-stationary signals (eg, simulated signals), so as to obtain accurate analysis results and facilitate the detection of the signal to be tested.

The learning process of propagation neural network includes forward learning and reverse learning. In the forward propagation process, the input signal is processed layer by layer from the input layer to the output layer through the hidden layer, and the state of neurons in each layer only affects the state of neurons in the next layer. However, if the expected output value cannot be obtained at the output layer, the error of the network output is attributed to the error of the connection weight. By backpropagating the error of the output layer unit to the input layer layer by layer to apportion to each unit, so as to obtain the reference error of each layer of neurons, in order to adjust the corresponding connection weights, that is, the backpropagation neural network. Through the learning method of error back propagation, the process of minimizing the cost function is used to complete the mapping from the input layer to the output layer. And the cost function can be the sum of the squares of the difference between the expected output and the actual output of the output unit in all input modes.

In this application, by using the wavelet decomposition algorithm to process the eigenvector matrices corresponding to different simulation states, an accurate output signal can be obtained, and then the output signal is processed by the backpropagation neural network detection model, so that the obtained different The fault detection model under the simulation state is more accurate.

Fig. 4 shows a schematic flowchart of a fault detection method provided by an embodiment of the present application. The fault detection method can be applied to a fault detection device. As shown in FIG. 4 , the fault detection method in the embodiment of the present application may include steps S401 to S409.

Step S401, collecting the voltage signal of the circuit under test to obtain a set of signals under test.

It should be noted that, while step S401 is executed, step S402 is also executed simultaneously.

The output voltage of the circuit to be tested is collected, and the obtained voltage signal is divided into multiple groups of signals to be tested, and the length of the signals to be tested is the same as that of the simulated signal obtained through the simulated circuit.

In the process of signal acquisition of the circuit under test, the acquisition frequency needs to be the same as that of the simulation circuit, so as to ensure the consistency of the acquisition signal corresponding to the simulation circuit and the voltage signal corresponding to the circuit under test, so that the detection result is more accurate.

Step S402, simulating the circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit.

The circuit to be tested can be simulated by the simulation software in the following way: connect a switch in series at the input end and output end of the component that may fail, and then simulate the test circuit by changing the switching time and switching frequency of each switch. A circuit in its normal state, intermittent fault state, and permanent fault state.

For example, by configuring the parameters of each switch (for example, parameters such as the opening time of the switch, the closing time of the switch, and the switching frequency), the circuit to be tested under the intermittent fault state is simulated to obtain the simulation circuit corresponding to the intermittent fault state; On and off, simulating the circuit under test under normal state and the circuit under test under permanent fault state, and obtain the simulation circuit corresponding to normal state and the simulation circuit corresponding to permanent fault state.

Step S403, collecting signals from the simulation circuit at a preset frequency to obtain a simulation signal set corresponding to the simulation state.

A preset input signal is set, and the preset input signal is input into a simulation circuit corresponding to a different simulation state, and a set of simulation signals corresponding to a different simulation state is collected through a preset test point.

For example, the simulated signal set can be expressed as:

i represents the serial number of the simulation state (for example, when i is equal to 1, it represents the normal state; when i is equal to 2, it represents the intermittent fault state; when i is equal to 3, it represents the permanent fault state). b represents the number of groups of signals collected in different simulation states, and b is an integer greater than or equal to 1. n represents the number of sample points of each group of simulation signals.

Indicates the nth simulation signal of group b collected in state i, and y _ib represents the collection of simulation signals of group b collected in state i.

Step S404, adding Gaussian white noise to the simulation signals in the simulation signal set, and performing empirical mode decomposition on the signals after adding Gaussian white noise, to obtain IMF components corresponding to each simulation signal.

The first white noise (the first white noise can be Gaussian white noise) can be added to the simulated signal in the simulated signal set to obtain the first signal to be processed; then, the second white noise is added to the simulated signal in the simulated signal set noise (the second white noise is a white noise signal with the same amplitude as the first white noise but opposite in direction), to obtain a second signal to be processed.

For example, if the simulation signal is set to x(t), the simulation signal x(t) can be obtained by n simulation signals in formula (1)

The determined linear signal is used to characterize the variation trend of the simulated signal. Adding a pair of white noise n _i (t) with equal amplitude but opposite directions to the simulated signal x(t), two sets of signals can be obtained: the first signal to be processed P _i (t) and the second signal to be processed N _i (t), the specific calculation formula is shown in formula (2):

i represents the serial number of the simulation signal x(t), and i is an integer greater than or equal to 1.

Then, Empirical Mode Decomposition (EMD) is performed on the first signal to be processed P _i (t) and the second signal to be processed N _i (t). For example, using formula (3) to perform EMD processing on the first signal to be processed P _i (t) and the second signal to be processed N _i (t), respectively, to obtain j IMF components, that is, j imf′ _ik (t) and j imf″ _ik (t).

k is an integer greater than or equal to 1 and less than or equal to j, and j is an integer greater than or equal to 1. And use the formula (4) to decompose the sum of the first signal to be processed P _i (t) and the second signal to be processed N _i (t) 2n times to obtain the k-order IMF component, ie IMF _k .

2n represents the number of decompositions, and i is an integer greater than or equal to 1 and less than or equal to j.

In some embodiments, signal acquisition is performed on the simulated circuits in the normal state, intermittent fault state and permanent fault state respectively, each state collects m sets of simulated signal sets, and the simulated signals in each group of simulated signal sets are carried out as above operation, so that the simulation signals in each group of simulation signal sets in each state can be decomposed into j IMF components. Then the IMF feature matrix A _i in the three states is obtained as shown in formula (5).

m represents the number of collection groups, and m is an integer greater than or equal to 1; j represents the quantity of the IMF component; i represents the state number of the simulation circuit, for example, when i equals ₁ , it represents a normal state, and A1 represents a normal state signal decomposition matrix; When i is equal to 2, it means intermittent fault state, then A ₂ represents the signal decomposition matrix of intermittent fault state; when i is equal to 3, it represents permanent fault state, then A ₃ represents the signal decomposition matrix of permanent fault state.

Step S405, performing energy entropy calculations on the IMF components corresponding to each simulation signal to obtain an eigenvector matrix.

Energy entropy can reflect the degree of confusion of various uncertain factors in the simulation circuit. For example, when the operating state of the simulated circuit changes, the energy entropy of the simulated circuit will change. After processing in step S404, each obtained IMF component includes the frequency band information corresponding to the simulated signal. When it is determined that the frequency band information corresponding to a certain simulated signal has changed, the IMF component can directly reflect the change corresponding to different faults. Therefore, the energy entropy calculation is performed on the IMF components corresponding to each simulation signal to obtain the eigenvector matrix, which can well reflect the occurrence of different circuit faults through the eigenvector matrix.

For example, steps 1) to 3) and their corresponding formulas can be used to calculate and obtain the eigenvector matrix.

Step 1) Set the simulation signal as x(t), and the IMF components corresponding to each simulation signal as C _K (t), then use formula (6) to calculate the energy E _k corresponding to the kth IMF component:

k is an integer greater than or equal to 1.

Then the energy sum E of the j IMF components is shown in formula (7):

E E ₁ +E ₂ +…+E _j (7)

j represents the number of IMF components of each group of simulated signals.

Step 2) Select the ratio of the energy E _mj of the jth IMF component of the m-th group of simulation signals to the total energy E _m of the m-th group of simulation signals as the eigenvector T _m , as shown in formula (8):

j represents the number of IMF components of the m-th group of simulation signals; E _m represents the energy sum of the j IMFs of the m-th group; E _mj represents the energy of the j-th IMF component of the m-th group of simulation signals.

Step 3) According to the m eigenvectors T _m corresponding to the m groups of simulation signals, determine the eigenvector matrix C with m rows and j columns, as shown in formula (9).

Through the above method, the eigenvector matrix C is obtained, and the energy of the j IMF components corresponding to each group of simulation signals can be clearly seen, so as to quickly determine which specific IMF component energy changes, and then quickly reflect the difference through the eigenvector matrix C. The occurrence of circuit failure.

In step S406, the maximum expectation algorithm is used to estimate the parameters of the discrete hidden Markov model in the normal state, the intermittent fault state and the permanent fault state, until the discrete hidden Markov model meets the preset convergence conditions, and three kinds of Three detection models in the state.

It should be noted that, while step S406 is executed, step S407 is also executed simultaneously.

Step S407, adding Gaussian white noise to the signal to be tested in the signal set to be tested, and performing empirical mode decomposition on the signal to be tested after adding Gaussian white noise, to obtain a vector to be measured corresponding to the signal to be measured in the signal set to be tested.

It should be noted that the processing process of the signal to be tested in the signal set to be tested is the same as the process of processing the simulated signal in the simulated signal set in step S404 , and will not be repeated here.

The vector to be measured corresponding to the signal set to be measured can be expressed as an IMF component.

Step S408, input the vectors to be tested into the normal state detection model, the intermittent fault state detection model and the permanent fault state detection model, respectively, according to the forward-backward algorithm, obtain the probability of the circuit under test being in a normal state, the circuit under test The probability of being in an intermittent fault state and the probability that the circuit under test is in a permanent fault state.

The normal state detection model, the intermittent fault state detection model and the permanent fault state detection model are all models obtained by training as follows:

A preset detection algorithm (for example, Expectation-Maximization algorithm, EM, etc.) Estimate the parameters of the propagation neural network (Back Propagation Neural Network, BPNN) detection model, etc.) until the preset detection model meets the preset convergence conditions, and obtain the normal state detection model; The parameters of the preset detection model are estimated until the preset detection model meets the preset convergence conditions, and the intermittent fault state detection model is obtained; the preset detection algorithm is used to estimate the parameters of the preset detection model under the permanent fault state respectively, Until the preset detection model satisfies the preset convergence condition, a permanent fault state detection model is obtained.

DHMM can be expressed by the following formula (10):

λ=(A,B,π,N,M) (10)

λ represents DHMM; N represents the number of working states of the circuit under test (for example, the working state corresponding to the circuit under test includes normal state, intermittent fault state and permanent fault state, then N is equal to 3); M represents the number of observations corresponding to each state ; π represents the initial probability of each state; B represents the observation probability transition matrix; A represents the transition probability matrix between different states. The specific calculation method of the above parameters is as follows:

For example, if M observation values are set as: V ₁ , V ₂ ,…,V _M , then the corresponding observation value of the circuit under test at time t can be expressed as: O _t ∈(V ₁ ,V ₂ ,…,V _M ) . The transition probability matrix A between different states can be expressed by formula (11):

A＝(a _ij ) _N*N (11)

a _ij represents the conditional probability of the circuit under test transitioning from state q _i at time t to state q _j at time t+1, and a _ij can be calculated using formula (12).

a _ij =P(Q _t+1 =q _j |Q _t =q _i ) (12)

Q _t represents the state at time t, Q _t+1 represents the state at time t+1, i and j are integers greater than or equal to 1 and less than or equal to N, and N is an integer greater than or equal to 1.

Set the initial probability of the i-th state as π _i , π _i can be expressed by formula (13):

π _i =P(Q ₁ =q _i ) (13)

The circuit to be tested is always in a normal state at the beginning, and when N is determined to be 3, the initial state probability matrix can be set as π _i =[1,0,0].

The observation probability transition matrix B can be expressed by formula (14):

B＝(b _jk ) _N*M (14)

b _jk =P(O _t =v _k |Q _t =q _j ), that is, b _jk represents the probability corresponding to the generated observed value v _k in the case of the state q _j of the circuit under test at time t. b _jk needs to satisfy

And, k is an integer greater than or equal to 1 and less than or equal to M.

In some implementations, a _ij can also be expressed as ξ _t (i,j), which can be calculated using formula (15):

ξ _t (i,j)=P(O,O _t =q _i ,Q _t+1 =q _j |λ) (15)

O _t represents the state corresponding to the circuit under test at time t, Q _t ∈ (q ₁ ,q ₂ ,…,q _N ), q ₁ ,q ₂ ,…,q _N represent the first state, the second state,… ..., the Nth state.

Then, based on the forward-backward algorithm, the forward variable α _t (i) in the forward algorithm and the backward variable β _t (j) in the backward algorithm are substituted into formula (15) to obtain the updated ξ _t (i, j), the updated ξ _t (i, j) is shown in formula (16):

Forward variable α _t (i)=P(O ₁ ,O ₂ ,...,O _t , q _i =S _i |λ), S _i represents the hidden state, and backward variable β _t (j)=P(O _{t +1} , O _t+2 , . . . , O _T |q _t = S _i , λ).

Furthermore, the probability ξ _t (i) of the circuit under test being in state q _i at time t is shown in formula (17):

It should be noted that the backward variable (also called the local probability) β _t (j) represents the local observation from the time t+1 to the termination time T when the DHMM is known and the circuit under test is in the hidden state S _i at time t. sequence probability.

Then, each parameter of the DHMM model is estimated to obtain the following parameters: initial probability value

(As shown in formula (18)), state transition matrix

(as shown in formula (19)) and observation probability transition matrix

(As shown in formula (20))

Indicates the number of expected values that the i-th state transfers to other states,

Indicates the expected number of transitions from the i-th state to the j-th state.

Further, through the initial probability value

state transition matrix

and the observation probability transition matrix

Determine the model λ under different states, for example, a normal state detection model, an intermittent fault state detection model and a permanent fault state detection model can be obtained.

By using the eigenvector matrix C as the observation sequence, the EM algorithm is used to estimate the parameters of the DHMM until the DHMM models in different states meet the preset convergence conditions, so as to obtain the normal state detection model, intermittent fault state detection model and permanent fault State detection model to facilitate subsequent calculation of the probability corresponding to each state.

Step S409, sort the probability of the circuit under test being in a normal state, the probability of the circuit under test being in an intermittent fault state, and the probability of the circuit under test being in a permanent fault state, and determine the state with the highest probability as the fault type of the circuit under test.

In the above-mentioned fault detection method, by simulating the circuit to be tested, the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit are obtained, the maintenance of the circuit to be tested is reduced, and the damage to the circuit to be tested is avoided; signal acquisition is performed on the simulation circuit , to obtain the simulation signal set corresponding to the simulation state, so as to enrich the signal samples and improve the detection accuracy of the circuit to be tested; to use the same acquisition frequency as that of the simulation circuit to collect the voltage signal of the circuit to be tested, which can ensure that the simulation circuit corresponds to The consistency between the collected signal and the voltage signal corresponding to the circuit under test makes the detection result more accurate; Gaussian white noise is added to the simulated signal in the simulated signal set, and the empirical mode decomposition is performed on the signal after adding Gaussian white noise to obtain For the IMF components corresponding to each simulation signal, the energy entropy calculation is performed on the IMF components corresponding to each simulation signal to obtain the eigenvector matrix. Because the IMF component in the eigenvector matrix includes the frequency band information corresponding to the simulation signal, it can be obtained through the eigenvector matrix. reflect the occurrence of different circuit faults; then use the eigenvector matrix as the observation sequence, and use the EM algorithm to estimate the parameters of the DHMM until the DHMM models in different states meet the preset convergence conditions, so as to obtain the normal state detection model, The intermittent fault state detection model and the permanent fault state detection model; then according to the forward-backward algorithm, the probability that the circuit under test is in a normal state, the probability that the circuit under test is in an intermittent fault state, and the probability that the circuit under test is in a permanent fault state are respectively obtained. Probability, to use the state with the highest probability as the fault type of the circuit under test to ensure the detection accuracy of the fault type of the circuit under test and reduce unnecessary maintenance costs.

According to the simulation signal set corresponding to the simulation state and the preset detection algorithm, detect the signal under test of the circuit under test, determine the fault type of the circuit under test, improve the accuracy of fault detection of the circuit under test, and reduce unnecessary maintenance costs.

The fault detection device according to the embodiment of the present application will be described in detail below with reference to the accompanying drawings. FIG. 5 shows a structural diagram of a fault detection device provided by an embodiment of the present application. As shown in FIG. 5 , the fault detection device may include an acquisition module 501 , a signal collection module 502 and a fault detection module 503 .

The acquisition module 501 is configured to simulate the circuit to be tested to obtain the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit; the signal acquisition module 502 is configured to collect signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state; fault detection The module 503 is configured to detect the signal under test of the circuit under test according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, and determine the fault type of the circuit under test.

According to the fault detection device of the present application, by obtaining module 501 to simulate the circuit to be tested, obtain the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit, reduce the maintenance of the circuit to be tested, and avoid damage to the circuit to be tested; use signal acquisition Module 502 collects signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state, so as to enrich the signal samples and improve the detection accuracy of the circuit to be tested; use the fault detection module 503 according to the simulation signal set corresponding to the simulation state and the preset detection algorithm , detect the test signal of the test circuit, determine the fault type of the test circuit, speed up the fault detection speed of the test circuit and improve the accuracy of the fault detection of the test circuit, and reduce unnecessary maintenance costs. To be clear, the present application is not limited to the specific configurations and processes described above and shown in FIG. 5 . For the convenience and brevity of description, the detailed description of the known methods is omitted here, and the specific working process of the above-described systems, modules and units can refer to the corresponding process in the aforementioned fault detection method, which will not be repeated here.

FIG. 6 shows a structural diagram of an exemplary hardware architecture of a computing device capable of implementing the fault detection method and apparatus according to the embodiments of the present application.

As shown in FIG. 6 , the computing device 600 includes an input device 601 , an input interface 602 , a central processing unit 603 , a memory 604 , an output interface 605 , and an output device 606 . The input interface 602, the central processing unit 603, the memory 604, and the output interface 605 are connected to each other through the bus 607, and the input device 601 and the output device 606 are respectively connected to the bus 607 through the input interface 602 and the output interface 605, and then communicate with other components of the computing device 600. Component connections.

Specifically, the input device 601 receives input information from the outside, and transmits the input information to the central processing unit 603 through the input interface 602; the central processing unit 603 processes the input information based on computer-executable instructions stored in the memory 604 to generate output information, temporarily or permanently store the output information in the memory 604, and then transmit the output information to the output device 606 through the output interface 605; the output device 606 outputs the output information to the outside of the computing device 600 for use by the user.

In some implementations, the computing device shown in FIG. 6 can be implemented as an electronic device that can include: a memory configured to store a computer program; and a processor configured to run the computer program stored in the memory. program to perform the fault detection method described above.

In some implementations, the computing device shown in FIG. 6 can be implemented as a fault detection system, and the fault detection system can include: a memory configured to store a computer program; and a processor configured to run the program stored in the memory. A computer program for performing the fault detection method described above.

The embodiment of the present application also provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the above fault detection method is implemented.

The above descriptions are merely exemplary embodiments of the present application, and are not intended to limit the protection scope of the present application. In general, the various embodiments of the present application can be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.

The embodiments of the present application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. Computer program instructions may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source code written in any combination of one or more programming languages or object code.

Any logic flow block diagrams in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules and functions, or may represent a combination of program steps and logic circuits, modules and functions. Computer programs can be stored on memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random-access memory (RAM), optical memory devices and systems (digital versatile disc DVD or CD), etc. Computer readable media may include non-transitory storage media. The data processor can be of any type suitable for the local technical environment, such as but not limited to general purpose computer, special purpose computer, microprocessor, digital signal processor (DSP), application specific integrated circuit (ASIC), programmable logic device (FGPA) and processors based on multi-core processor architectures.

The foregoing has provided a detailed description of exemplary embodiments of the present application by way of exemplary and non-limiting examples. However, considering the accompanying drawings and the claims, various modifications and adjustments to the above embodiments are obvious to those skilled in the art, but do not depart from the scope of the present application. Therefore, the proper scope of the application will be determined from the claims.

Claims (17)

1. A fault detection method, comprising:

   Simulating the circuit to be tested to obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit;

   Collecting signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state; and

   According to the simulated signal set corresponding to the simulated state and the preset detection algorithm, the tested signal of the tested circuit is detected to determine the fault type of the tested circuit.
2. The method according to claim 1, wherein said simulating the circuit to be tested, and obtaining the simulation circuit corresponding to the circuit to be tested and the simulation state of the simulation circuit comprises:

   simulating the circuit to be tested according to a simulation algorithm to obtain the simulation circuit, the simulation circuit including a switch arranged at an input end and an output end of an analog component;

   obtaining switching times and switching frequencies of the switches in the simulated circuit; and

   According to the switching time and the switching frequency, the working state of the circuit under test is simulated to obtain the simulation state of the simulation circuit.
3. The method according to claim 2, wherein the operating state of the circuit to be tested or the simulation state of the simulation circuit comprises: at least one of a normal state, an intermittent fault state and a permanent fault state;

   The simulated signal set corresponding to the simulated state includes: at least one of a normal simulated signal set, an intermittent fault simulated signal set, and a permanent fault simulated signal set.
4. The method according to claim 1, wherein said collecting signals from said simulation circuit and obtaining a simulation signal set corresponding to said simulation state comprises:

   Signal collection is performed on the simulation circuit at a preset frequency to obtain a simulation signal set corresponding to the simulation state, where the preset frequency includes a switching frequency in the simulation circuit.
5. The method according to claim 1, wherein, according to the simulation signal set corresponding to the simulation state and the preset detection algorithm, the signal to be tested of the circuit to be tested is detected to determine the fault of the circuit to be tested Types include:

   performing empirical mode decomposition on the signal to be tested of the circuit to be tested to obtain a vector to be tested;

   Performing empirical mode decomposition on the simulation signals in the simulation signal set corresponding to the simulation state to obtain the eigenvector matrix corresponding to the simulation state;

   Determine a fault detection model corresponding to the simulation state according to the eigenvector matrix corresponding to the simulation state and the preset detection algorithm;

   Inputting the vector to be tested into a fault detection model corresponding to the simulation state to obtain a working state probability corresponding to the circuit to be tested; and

   The fault type of the circuit under test is determined according to the working state probability corresponding to the circuit under test.
6. The method according to claim 5, wherein performing empirical mode decomposition on the simulation signals in the simulation signal set corresponding to the simulation state, and obtaining the eigenvector matrix corresponding to the simulation state comprises:

   Using the simulation signal in the simulation signal set corresponding to the simulation state as the original signal;

   Processing the original signal according to a preset noise signal to obtain a signal decomposition matrix, wherein the signal decomposition matrix is a matrix corresponding to the simulation state, and the signal decomposition matrix includes a plurality of decomposition vectors; and

   According to the signal decomposition matrix, an eigenvector matrix corresponding to the simulation state is determined.
7. The method according to claim 6, wherein the preset noise signal comprises: a first white noise and a second white noise, and the second white noise is the same in amplitude and opposite in direction to the first white noise noise;

   The processing the original signal according to the preset noise signal, and obtaining the signal decomposition matrix includes:

   adding the first white noise to the original signal to obtain a first signal to be processed;

   adding the second white noise to the original signal to obtain a second signal to be processed; and

   The signal decomposition matrix is determined according to the first signal to be processed and the second signal to be processed.
8. The method according to claim 6, wherein, according to the signal decomposition matrix, determining the eigenvector matrix corresponding to the simulation state comprises:

   Using the energy entropy of the decomposition vector in the signal decomposition matrix as a feature vector, the energy entropy of the decomposition vector reflects the frequency band energy information of the signal to be processed; and

   According to the eigenvectors, an eigenvector matrix corresponding to the simulation state is determined.
9. The method according to claim 6, wherein, according to the signal decomposition matrix, determining the eigenvector matrix corresponding to the simulation state comprises:

   using the magnitudes of the decomposition vectors in the signal decomposition matrix as eigenvectors; and

   According to the eigenvectors, an eigenvector matrix corresponding to the simulation state is determined.
10. The method according to claim 5, wherein, according to the eigenvector matrix corresponding to the simulation state and the preset detection algorithm, determining the fault detection model corresponding to the simulation state comprises:

    Using the preset detection algorithm to process the eigenvector matrix corresponding to the simulation state to obtain a fault detection model corresponding to the simulation state; and

    The fault detection model corresponding to the simulation state includes: at least one of a normal state detection model, an intermittent fault state detection model, and a permanent fault state detection model.
11. The method according to claim 10, wherein, using the preset detection algorithm, processing the eigenvector matrix corresponding to the simulation state, and obtaining the fault detection model corresponding to the simulation state comprises:

    Using the preset detection algorithm to estimate the parameters of the preset detection model in the intermittent fault state until the preset detection model satisfies a preset convergence condition to obtain the intermittent fault state detection model, the The preset detection model includes the feature vector matrix.
12. The method according to claim 11, wherein the preset detection algorithm comprises: a maximum expectation algorithm or a wavelet decomposition algorithm;

    The preset detection model includes: a discrete hidden Markov model or a backpropagation neural network detection model; wherein, the parameters of the discrete hidden Markov model include: an observation sequence, the number of simulation states, and the initial probability of a state , a transition probability matrix and an observation probability transition matrix, the observation sequence includes the eigenvector matrix.
13. The method according to any one of claims 10 to 12, wherein the inputting the vector to be tested into the fault detection model corresponding to the simulation state, and obtaining the working state probability corresponding to the circuit to be tested comprises:

    According to the forward-backward algorithm, the vector to be tested is input into the fault detection model corresponding to the simulation state, and the working state probability corresponding to the circuit to be tested is obtained.
14. The method according to claim 13, wherein the working state probability corresponding to the circuit under test includes: the probability that the circuit under test is in the normal state, the probability that the circuit under test is in the intermittent fault state, and the probability that the circuit under test is in the permanent fault state;

    The determining the fault type of the circuit under test according to the working state probability corresponding to the circuit under test includes:

    sorting the probability that the circuit under test is in the normal state, the probability that the circuit under test is in the intermittent fault state, and the probability that the circuit under test is in the permanent fault state, to obtain a ranking result; and

    According to the ranking result, the fault type of the circuit under test is determined.
15. A fault detection device, comprising:

    An acquisition module configured to simulate the circuit to be tested, and obtain a simulation circuit corresponding to the circuit to be tested and a simulation state of the simulation circuit;

    A signal collection module configured to collect signals from the simulation circuit to obtain a simulation signal set corresponding to the simulation state; and

    The fault detection module is configured to detect the signal under test of the circuit under test according to the simulation signal set corresponding to the simulation state and a preset detection algorithm, and determine the fault type of the circuit under test.
16. An electronic device comprising:

    at least one processor; and

    A memory having stored thereon at least one computer program which, when executed by said at least one processor, causes said at least one processor to implement a malfunction as claimed in any one of claims 1 to 14 Detection method.
17. A computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the fault detection method according to any one of claims 1 to 14 is implemented.

Images