CN115599615B - CHT technology processor power management design architecture - Google Patents

CHT technology processor power management design architecture Download PDF

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CN115599615B
CN115599615B CN202211288180.9A CN202211288180A CN115599615B CN 115599615 B CN115599615 B CN 115599615B CN 202211288180 A CN202211288180 A CN 202211288180A CN 115599615 B CN115599615 B CN 115599615B
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power
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CN115599615A (en
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王杜
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Changsha Fangwei Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to the field of integrated circuits, in particular to a power management design architecture of a CHT (Single emission multithreading dynamic cycle parallel) processor; the architecture system of the invention comprises: the system comprises a standby area IO ring, a test area IO ring, a standard area IO ring, a standby domain, a test domain and a standard domain. The invention creates a power management method suitable for a CHT technical processor and a brand new power management design framework. The technology of the invention meets the ultra-low power consumption requirement and the MBIST test requirement (such as CHTDFTFLOW requirement), and aims to realize a deep power management strategy, but not an application-level (such as DVFS scheme) power management strategy, and has important application value for a lightweight low-power consumption (such as Internet of things) processor.

Description

CHT technology processor power management design architecture
Technical Field
The invention relates to the field of integrated circuits, in particular to a method for designing and realizing a chip system on a chip (SOC) of a processor by adopting a CHT technology (single-emission multithreading dynamic cyclic parallelism technology, hereinafter referred to as CHT technology).
Background
The integrated circuit industry is heavily supported. The architecture of the processor is the basis for building the processor, and most common architectures are foreign architectures, such as x86 architecture, ARM architecture, etc. There are many limitations to the application of these architectures, so new architectures are needed. The novel architecture technology is the core of an autonomous controllable, safe and reliable domestic processor and is also a difficult point. At present, the system structure technology has less innovation results, urgent requirements, great strategic status and wide market space; the SOC technology system matched with the method has important significance.
The existing power management scheme of the processor generally realizes the management of the power through an application layer, and cannot meet the requirements of MBIST (memory build-in-self test) and low power consumption.
Disclosure of Invention
The purpose of the invention is that: the invention discloses a power management method suitable for a CHT (compact flash) technical processor, which meets the requirements of ultra-low power consumption and MBIST test (such as CHT DFT FLOW), aims to realize a deep power management strategy, and is not an application-level (such as DVFS scheme) power management strategy, and particularly has important application value for a lightweight low-power consumption (such as Internet of things) processor. The technology of the invention has important guiding significance for the design of the CHT technology processor, is also suitable for the common architecture processor, and has important guiding significance for the design of the general processor.
The present invention provides a CHT technology processor power management design architecture comprising: the system comprises a standby area IO ring, a test area IO ring, a standard area IO ring, a standby domain, a test domain and a standard domain;
the standby area IO ring is connected to an analog IO end, a universal digital IO end, a wake-up signal end and a first core voltage end, and an external IO domain high-voltage power supply end, a test enabling end and a first core voltage power-up completion identifier;
the test area IO ring is connected to an external IO domain high-voltage power supply end, a test digital IO end, a third core voltage end, a test high-voltage power supply end, a power down signal end, a first core voltage power-up completion identifier and a third core voltage power-up completion identifier;
the standard area IO ring is connected to an external IO domain high-voltage power supply end, a second core voltage end, a general digital IO end, an analog IO end, a power-down signal end, a test enabling end, a first core voltage power-up completion identifier and a third core voltage power-up completion identifier;
the standby domain comprises a first voltage regulator, a second voltage regulator, standby domain logic, a dual-voltage power supply IP unit and a core voltage IP unit;
the standard domain comprises a standard domain dual-voltage power supply IP unit, a standby domain dual-voltage power supply IP unit and standard domain logic;
the test domain comprises test domain logic and a nonvolatile memory, the test domain logic is connected to the first core voltage power-up completion identifier, the third core voltage terminal and the third core voltage power-up completion identifier, and the test domain logic is connected to a test IO port and a test enabling terminal; and when the test enabling end takes effect, the second core voltage end is closed, the second core voltage power-up completion mark takes effect, and the test domain logic enters a test state.
Further, the internal interface information of the design architecture includes:
the first voltage regulator is connected to an external IO domain high-voltage power supply end, a first core voltage end and a first core voltage power-up completion identifier;
the second voltage regulator is connected to the external IO domain high-voltage power supply end, the first core voltage end-of-power-up identifier, the power-down signal end, the test enabling end, the second core voltage end, the third core voltage end-of-power-up identifier, the third core voltage end and the third core voltage end-of-power-up identifier.
Further, the system also comprises an IO isolation region, wherein the standby region IO ring, the test region IO ring and the standard region IO ring are isolated through the IO isolation region.
Further, the standby area IO ring is connected to an analog IO port, a general IO port, a wake-up signal end, a first core voltage end, an external IO domain high-voltage power supply end and a test enabling end, and the first core voltage power-up completion identifier is adopted to carry out power-up bias and power-down bias; the minimum system of the standby area IO ring comprises: the wake-up signal end, the external IO domain high-voltage power supply end, the test enabling end and the first core voltage power-up completion identification.
Further, the test area IO ring is connected to the external IO domain high voltage power supply terminal, the test digital IO terminal, the third core voltage terminal, and the test high voltage power supply terminal, and uses the power-down signal terminal, the first core voltage power-up completion identifier and the third core voltage power-up completion identifier to perform power-up bias and power-down bias, and the minimum system of the test area IO ring includes: and the test digital IO end, the test high-voltage power supply end, the power-down signal end and the third core voltage are provided with a power-up mark.
Further, the standard area IO ring comprises the external IO domain high-voltage power supply end, a second core voltage end, a general IO end and an analog IO end, and a power-down signal end, a test enabling end, a first core voltage power-up completion identifier and a second core voltage power-up completion identifier are adopted to carry out power-up bias and power-down bias; the minimum system of the IO ring of the test area comprises: the general IO end, the power-down signal end, the test enabling end and the second core voltage are powered up to be identified.
Further, the internal circuitry of the processor chip is cut into: the standby domain, the test domain and the standard domain are isolated and biased by the cross-domain logic interaction signal through the isolation bias logic part.
Further, the standby domain further comprises a standby logic part, a standby domain dual-voltage power supply IP unit and a standby domain core power supply IP unit, the standby domain IO ring is externally adopted for communication, and the isolation bias logic part is internally adopted for communication; the second voltage regulator is divided into parts, such as one output path of Vcore2 and the other output path of Vcore3; the minimum system of the standby domain comprises: the first voltage regulator, the second voltage regulator, and the standby logic.
Further, the test domain comprises the test domain logic and a nonvolatile memory, the test area IO ring is adopted to communicate externally, and the isolation bias logic part is adopted to communicate internally.
Further, the standard domain comprises the standard domain dual-voltage power supply IP unit, the standard domain core power supply IP unit and the standard domain logic, the standard region IO ring is adopted for communication, and the isolation bias logic part is adopted for communication; the minimum system of the standard domain comprises: standard domain logic.
Further, the test domain and the standard domain are in direct logic communication through a logic network of the test logic block and the standard domain logic.
Further, the isolation bias logic part is the core of cross-domain logic communication, the IO isolation is the core of IO circuit segmentation, and the two parts are specially designed for isolation bias.
Further, the test enabling end is used for being connected with the card pin.
In summary, the beneficial effects of the implementation of the invention are as follows:
1. a power management method suitable for a CHT technical processor is created;
2. the invention provides a brand new power management technology, which meets the requirements of ultra-low power consumption and MBIST test (such as CHTDFTFLOW requirements);
3. implementing a deep power management policy, rather than an application-level (e.g., DVFS scheme) power management policy;
4. the method has important application value for lightweight low-power consumption (such as Internet of things) processors;
5. the method has important guiding significance for the design of the CHT technical processor, and based on the technical characteristics of the CHT, the method complements each other and complements each other;
6. is also suitable for the common architecture processor, and has important guiding significance for the design of the general processor.
Drawings
FIG. 1 is a block diagram of a CHT power management architecture.
FIG. 2 is a schematic diagram showing MBIST timing analysis without testing the internal voltage in the present technology.
FIG. 3 is a schematic diagram of an MBIST timing analysis method for testing internal voltages according to the present invention.
FIG. 4 is a schematic diagram showing a second MBIST timing analysis for testing internal voltages according to the present invention.
FIG. 5 is a timing analysis of a low power mode according to the present invention.
FIG. 6 is a diagram illustrating a power tree analysis in accordance with the present invention.
FIG. 7 is a diagram illustrating a reset tree analysis in accordance with the present invention.
FIG. 8 is a diagram illustrating power-on and power-off bias detail analysis in accordance with the present technique.
FIG. 9 is a diagram illustrating a low power consumption power-down bias detail analysis in accordance with the present invention.
FIG. 10 illustrates an isolation bias method in accordance with the present invention.
FIG. 11 is a schematic diagram showing details of MBIST power-off bias analysis in accordance with the present invention.
FIG. 12 is a flow chart of the MBIST power supply method in the present technology.
FIG. 13 shows a second process of the MBIST power supply method in the present invention.
FIG. 14 is a diagram illustrating a low power consumption, off-site save-restore framework in accordance with the present invention.
FIG. 15 is a flow chart illustrating the low power consumption power-down on-site save-restore process in accordance with the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings.
The invention creates a power management method suitable for a CHT technical processor and a brand new power management technology. The technology of the invention meets the ultra-low power consumption requirement and the MBIST test requirement (such as CHT DFTFLOW requirement), and aims to realize a deep power management strategy, but not an application-level (such as DVFS scheme) power management strategy, and has important application value for a lightweight low-power consumption (such as Internet of things) processor. The technology of the invention has important guiding significance for the design of the CHT technology processor, is also suitable for the common architecture processor, and has important guiding significance for the design of the general processor.
As shown in fig. 1, the overall technology architecture includes:
Figure GDA0004253589980000061
Figure GDA0004253589980000071
the internal interface information specifically includes:
Figure GDA0004253589980000072
Figure GDA0004253589980000081
Figure GDA0004253589980000091
Figure GDA0004253589980000101
the signals (or networks) with the same names are connected with each other to form an inherent connection relationship.
As shown in fig. 2, in order to perform MBIST timing analysis without testing internal voltage in the present invention, the following steps are implemented according to the flow:
s1: external start power supply (VDDH start power supply), internal in high resistance state (Z);
s2: vcore1 starts set up and completes, vcore2 and Vcore3 will now be suppressed (0), with no output; vcore1ok (first core voltage end of up identifier) output validation (0), prepare to reset the Vcore1 load, vcore3 ok (third core voltage end of up identifier) can be in an indefinite state (X) at this time, also can press output validation (0), if output validation (0) 026-Vcore1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier), 037-Vcore 1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier) can become 026-Vcore3 ok (third core voltage end of up identifier), 037-Vcore3 (third core voltage end of up identifier);
s3: vcore1 outputs normally, starts to reset its load, and the load will appear in a transient unstable state (X) until the reset is completed; vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is in effect (0); power_off and MBIST_EN (test Enable) are in an inactive state (Invalid); vcore1ok (first core voltage power up complete flag) output is inactive (1);
s4: vcore2, vcore3 begin set up and complete;
s5: vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is validated (0), resetting Vcore2, vcore3 loads;
s6: the reset is completed and the normal working state is entered;
s7: an external voltage supply applied to 023-Vcore3 (the third core voltage terminal), the magnitude of which is the maximum value of the core voltage, typically 1.1 Vcore3;
s8: the MBIST test (CP test) is turned on, and the MBIST_EN (test enable) is validated by the P-off CMD or 016-MBIST_EN (test enable), respectively:
(1) From the external pin 016-mbist_en (test enable);
(2) 022-MBIST_DIO (test digital IO end), 051-MBIST logic (P-off CMD), 08-Isolated bias circuit, 043-Standby logic (Standby logic part) from external communication;
this situation may be directly validated by the P-off CMD to Power off, so mbist_en (test enable) may be omitted;
vcore2 off and Vcore3 ok (third core voltage power up done flag) are in effect; the internal Vcore3 is turned off, completely controlled by the outside;
s9: the test is completed, and an external voltage is applied to 023-Vcore3 (the third core voltage end), wherein the magnitude is the minimum value of the core voltage, and is generally 0.9 times Vcore3;
s10: the invalidation of MBIST_EN (test enable) is caused by either P-off CMD or 016-MBIST_EN (test enable);
this case may be disabled directly by the P-off CMD with Power off (Power down side), so mbist_en (test enable side) may be omitted;
vcore2 is turned on to power up and all loads are reset by Vcore3 ok (third core voltage powered up flag);
s11: returning to the normal working state.
As shown in fig. 3, an MBIST timing analysis, which is a method for testing internal voltages in the present technology, is implemented according to the flow, as follows,
s1: external start power supply (VDDH start power supply), internal in high resistance state (Z);
s2: vcore1 starts set up and completes, vcore2 and Vcore3 will now be suppressed (0), with no output; vcore1ok (first core voltage end of up identifier) output validation (0), prepare to reset the Vcore1 load, vcore3 ok (third core voltage end of up identifier) can be in an indefinite state (X) at this time, also can press output validation (0), if output validation (0) 026-Vcore1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier), 037-Vcore 1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier) can become 026-Vcore3 ok (third core voltage end of up identifier), 037-Vcore3 (third core voltage end of up identifier);
s3: vcore1 outputs normally, starts to reset its load, and the load will appear in a transient unstable state (X) until the reset is completed; vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is in effect (0); power_off and MBIST_EN (test Enable) are in an inactive state (Invalid); vcore1ok (first core voltage power up complete flag) output is inactive (1);
s4: vcore2, vcore3 begin set up and complete;
s5: vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is validated (0), resetting Vcore2, vcore3 loads;
s6: the reset is completed and the normal working state is entered; vcore1 and Vcore3 can be measured in the period, the measuring current is relatively large, the measuring precision is affected, the card needle position can be increased, but the cost is increased;
s7: an external voltage supply applied to 023-Vcore3 (the third core voltage terminal), the magnitude of which is the maximum value of the core voltage, typically 1.1 Vcore3;
s8: the MBIST test (CP test) is turned on, and the MBIST_EN (test enable) is validated by the P-off CMD or 016-MBIST_EN (test enable), respectively:
(1) From the external pin 016-mbist_en (test enable);
(2) 022-MBIST_DIO (test digital IO end), 051-MBIST logic (P-off CMD), 08-Isolated bias circuit, 043-Standby logic (Standby logic part) from external communication;
this situation may be directly validated by the P-off CMD to Power off, so mbist_en (test enable) may be omitted;
vcore2 off and Vcore3 ok (third core voltage power up done flag) are in effect; the internal Vcore3 is turned off, completely controlled by the outside;
s9: the test is completed, and an external voltage is applied to 023-Vcore3 (the third core voltage end), wherein the magnitude is the minimum value of the core voltage, and is generally 0.9 times Vcore3;
s10: the invalidation of MBIST_EN (test enable) is caused by either P-off CMD or 016-MBIST_EN (test enable);
this situation may be directly validated by the P-off CMD to Power off, so mbist_en (test enable) may be omitted;
vcore2 is turned on to power up and all loads are reset by Vcore3 ok (third core voltage powered up flag);
s11: returning to the normal working state.
As shown in fig. 4, the second MBIST timing analysis method for testing the internal voltage in the present invention is implemented according to the following steps:
s1: external start power supply (VDDH start power supply), internal in high resistance state (Z);
s2: vcore1 starts set up and completes, vcore2 and Vcore3 will now be suppressed (0), with no output; vcore1ok (first core voltage end of up identifier) output validation (0), prepare to reset the Vcore1 load, vcore3 ok (third core voltage end of up identifier) can be in an indefinite state (X) at this time, also can press output validation (0), if output validation (0) 026-Vcore1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier), 037-Vcore 1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier) can become 026-Vcore3 ok (third core voltage end of up identifier), 037-Vcore3 (third core voltage end of up identifier);
s3: vcore1 outputs normally, starts to reset its load, and the load will appear in a transient unstable state (X) until the reset is completed; vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is in effect (0); power_off and MBIST_EN (test Enable) are in an inactive state (Invalid); vcore1ok (first core voltage power up complete flag) output is inactive (1);
s4: vcore2, vcore3 begin set up and complete;
s5: vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is validated (0), resetting Vcore2, vcore3 loads;
s6: the reset is completed and the normal working state is entered;
s7: the MBIST test (CP test) is turned on, and the MBIST_EN (test enable) is validated by the P-off CMD or 016-MBIST_EN (test enable), respectively:
(1) From the external pin 016-mbist_en (test enable);
(2) 022-MBIST_DIO (test digital IO end), 051-MBIST logic (P-off CMD), 08-Isolated bias circuit, 043-Standby logic (Standby logic part) from external communication;
vcore2 off and Vcore3 ok (third core voltage power up done flag) are in effect; vcore1 and Vcore3 can be measured in the period, the measuring current is moderate, and the measuring precision is high;
s8: an external voltage supply applied to 023-Vcore3 (the third core voltage terminal), the magnitude of which is the maximum value of the core voltage, typically 1.1 Vcore3;
s9: the Power off (Power off end) is enabled by the P-off CMD, the internal Vcore3 is closed, and the external control is performed completely;
s10: the test is completed, and an external voltage is applied to 023-Vcore3 (the third core voltage end), wherein the magnitude is the minimum value of the core voltage, and is generally 0.9 times Vcore3;
s11: the invalidation of MBIST_EN (test enable) is caused by either P-off CMD or 016-MBIST_EN (test enable); the Power off (Power off end) is enabled by the P-off CMD;
vcore2 is turned on to power up and all loads are reset by Vcore3 ok (third core voltage powered up flag);
s12: returning to the normal working state.
As shown in fig. 5, for the time sequence analysis of the low power mode in the present technology, according to the flow, the following is implemented in detail,
s1: external start power supply (VDDH start power supply), internal in high resistance state (Z);
s2: vcore1 starts set up and completes, vcore2 and Vcore3 will now be suppressed (0), with no output; vcore1ok (first core voltage end of up identifier) output validation (0), prepare to reset the Vcore1 load, vcore3 ok (third core voltage end of up identifier) can be in an indefinite state (X) at this time, also can press output validation (0), if output validation (0) 026-Vcore1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier), 037-Vcore 1ok (first core voltage end of up identifier) & Vcore3 ok (third core voltage end of up identifier) can become 026-Vcore3 ok (third core voltage end of up identifier), 037-Vcore3 (third core voltage end of up identifier);
s3: vcore1 outputs normally, starts to reset its load, and the load will appear in a transient unstable state (X) until the reset is completed; vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is in effect (0); power_off and MBIST_EN (test Enable) are in an inactive state (Invalid); vcore1ok (first core voltage power up complete flag) output is inactive (1);
wake up (Wake up signal end) state does not influence the subsequent state pushing at this time;
s4: vcore2, vcore3 begin set up and complete;
s5: vcore3 ok (third core voltage up-done flag), vcore3 ok (third core voltage up-done flag) output is validated (0), resetting Vcore2, vcore3 loads;
s6: vcore3 ok (third core voltage up-end identifier), vcore3 ok (third core voltage up-end identifier) output invalidation (1) reset is completed, and normal working state is entered;
s7: a low Power consumption mode (Power off state) is started, power off (Power off end) is enabled by Cross logic, output is closed by Vcore2 and Vcore3, and output is enabled (0) by Vcore3 ok (third core voltage up end mark) and Vcore3 ok (third core voltage up end mark); at this time, the external security Wake up (Wake-up signal end) is invalid;
s8: entering a low Power consumption mode (Power off state), wherein the system current can be as low as 1 uA;
s9: the external Wake up (Wake-up signal end) takes effect, and the Power off (Power-down signal end) state is cleared;
s10: starting resuscitation internally, and powering up Vcore2 and Vcore3 again;
s11: the output of Vcore2 and Vcore3 loads by Vcore3 ok (third core voltage power-up completion identification) and Vcore3 ok (third core voltage power-up completion identification) takes effect (0) to complete reset; at this time, the external Wake up (Wake-up signal end) can be withdrawn at will;
s12: returning to the normal working state.
As shown in fig. 6, the power tree relationship carding in the technology of the present invention is divided into three parts according to the Vcore voltage power supply relationship:
(1) Standby domain, vcore1 power grid related components, including: 011-SAIO, 012-SGPIO, 013-Wake up (Wake-up signal end), 014-Vcore1, 016-MBIST_EN (test enable end), 041-Regulator1 (first voltage Regulator), 043-Standby logic, 044-SVDDH+SVcore IP (Standby domain dual voltage supply IP unit), 045-SVcore IP (Standby domain supply IP unit);
(2) Normal domain, vcore2 power grid related components, including: 042-Regulator2 (second voltage Regulator), 032-Vcore2 (second core voltage terminal), 033-GPIO (general purpose IO terminal), 034-AIO (analog IO terminal), 061-VDDH+Vcore IP (standard domain dual voltage supply IP unit), 062-Vcore IP (standard domain core supply IP unit), 063-Normal logic (standard domain logic);
(3) MBIST domain, vcore3 power grid related components, including: 042-Regulator2 (second voltage Regulator), 022-mbist_dio (test digital IO terminal), 023-Vcore3 (third core voltage terminal), 024-mbist_vh (test high voltage supply terminal), 051-MBIST logic (test domain logic), 052-Non-Volatile Memory (nonvolatile Memory);
as shown in fig. 7, the reset tree relationship carding in the technology of the present invention is divided into three parts according to the Vcore ok load relationship:
(1) Vcore1ok (first core voltage power up complete flag), load includes: 043-Standby logic, 044-SVDDH+SVcore IP (Standby domain dual voltage supply IP unit), 052-Non-Volatile Memory;
(2) Vcore3 ok (third core voltage power up complete flag), load includes: 061-VDDH+Vcore IP (standard domain Dual voltage supply IP Unit), 063-Normal logic;
(3) Vcore3 ok (third core voltage power up complete flag), load includes: 051-MBIST logic, 052-Non-Volatile Memory;
the 052-Non-Volatile Memory is controlled by the Vcore1ok (first core voltage power-up completion identifier) and the Vcore3 ok (third core voltage power-up completion identifier) at the same time, so that the absolute safety of internal data of the 052-Non-Volatile Memory in the power-up process is ensured.
As shown in fig. 8, the power-on and power-off bias detail analysis in the present technology is divided into three parts according to the Vcore ok load relation:
(1) Vcore1ok (first core voltage power up complete flag), load includes: 012-SGPIO, 013-Wake up (Wake-up signal end), 016-MBIST_EN (test enable end), 044-SVDDH+SVcore IP (standby domain dual voltage supply IP unit), 033-GPIO (general purpose IO end), 022-MBIST_DIO (test digital IO end);
(2) Vcore3 ok (third core voltage power up complete flag), load includes: 033-GPIO (general purpose IO terminal), 061-VDDH+Vcore IP (standard domain dual voltage power supply IP unit);
(3) Vcore3 ok (third core voltage power up complete flag), load includes: 022-mbist_dio (test digital IO terminal);
the purpose of Vcore1ok (first core voltage power-up completion identifier) drives 033-GPIO (general purpose IO terminal) and 022-MBIST_DIO (test digital IO terminal) is to guarantee absolute security of internal power-up.
As shown in fig. 9, in the Low power consumption power-off bias detail analysis in the present invention, vcore2 and Vcore3 are turned off in Low power consumption (Low power) mode, and the main power-off loads are as follows: 042-Regulator2 (second voltage Regulator), 033-GPIO (general purpose IO terminal), 061-VDDH+Vcore IP (Standard Domain Dual-voltage supply IP Unit), 062-Vcore IP (Standard Domain core supply IP Unit), 063-Normal logic (Standard Domain logic), 022-MBIST_DIO (test digital IO terminal), 051-MBIST logic (test Domain logic), 052-Non-Volatile Memory (nonvolatile Memory);
if VDDH and Vcore are used for Power supply, when Vcore is turned off, a Power off signal bias is required, similar to the load: 042-Regulator2 (second voltage Regulator), 033-GPIO (general purpose IO terminal), 061-VDDH+Vcore IP (standard domain dual voltage supply IP unit), 022-MBIST_DIO (test digital IO terminal);
meanwhile, 08-Logic isolated bias (isolation bias logic) isolates and biases the cross-domain signal, and inhibits leakage current.
As shown in fig. 10, the isolation bias method in the present technology. A scenario is illustrated where 043-Standby logic interacts with 063-Normal logic.
Figure GDA0004253589980000191
As shown in FIG. 11, in the MBIST power-off bias detail analysis of the present invention, vcore2 in MBIST test mode is mainly power-off loaded with: 042-Regulator2 (second voltage Regulator), 033-GPIO (general purpose IO terminal), 061-vddh+vcore IP (standard domain dual voltage supply IP unit), 062-Vcore IP (standard domain core supply IP unit), 063-Normal logic (standard domain logic);
if VDDH and Vcore are used for power supply, when Vcore is turned off, mbist_en (test enable) signal bias is required, like load: 042-Regulator2 (second voltage Regulator), 033-GPIO (general purpose IO terminal), 061-vddh+vcore IP (standard domain dual voltage supply IP unit);
meanwhile, 08-Logic isolated bias (isolation bias logic) isolates and biases the cross-domain signal, and inhibits leakage current.
Mbist_en (test enable) has two methods:
(1) From the external pin 016-mbist_en (test enable);
(2) 022-MBIST_DIO (test digital IO end), 051-MBIST logic (test domain logic), 08-Isolated bias circuit and 043-Standby logic (Standby logic part) come from external communication, as shown by a dotted line box;
as shown in fig. 12, a flow of the MBIST power supply method in the present invention is specifically implemented as follows:
s1: external VDDH supplies power, and the system starts to power up;
s2: executing a Power on (Power on) process internally;
s3: until the internal power-up is completed;
s4: starting a normal working state;
s5: the MBIST test (CP test) is turned on, and the MBIST_EN (test enable) is validated by the P-off CMD or 016-MBIST_EN (test enable), respectively:
(1) From the external pin 016-mbist_en (test enable);
(2) 022-MBIST_DIO (test digital IO end), 051-MBIST logic (P-off CMD), 08-Isolated bias circuit, 043-Standby logic (Standby logic part) from external communication;
s6: vcore2 off and Vcore3 ok (third core voltage power up done flag) are in effect;
s7: vcore1 and Vcore3 can be measured in the period, the measuring current is moderate, and the measuring precision is high;
s8: completing measurement;
s9: an external voltage supply applied to 023-Vcore3 (the third core voltage terminal), the magnitude of which is the maximum value of the core voltage, typically 1.1 Vcore3;
s10: millisecond delay so that internal 1.1 vcore3 stabilizes;
s11: the Power off is asserted by the P-off CMD,
s12: the internal Vcore3 is turned off, completely controlled by the outside;
s13: entering an MBIST test flow;
s14: until the test is completed,
s15: an external voltage supply applied to 023-Vcore3 (the third core voltage terminal) having a magnitude of a minimum core voltage, typically 0.9 Vcore3;
s16: the invalidation of MBIST_EN (test enable) is caused by either P-off CMD or 016-MBIST_EN (test enable); the Power off (Power off end) is enabled by the P-off CMD;
vcore2 is turned on to power up and all loads are reset by Vcore3 ok (third core voltage powered up flag);
s17: returning to the normal working state.
As shown in fig. 13, the second flow of MBIST power supply method in the present invention is specifically implemented as follows:
s1: external VDDH supplies power, at the same time 016-MBIST_EN (test enable end) is in effect, 023-Vcore3 (third core voltage end) test voltage is in effect, and at this time, external Vcore3 is applied as long as the external Vcore3 is in a safe range, and the external Vcore3 does not need to be fixedly biased to the highest value;
s2: executing a Power on (Power on) process internally;
s3: until the internal power-up is completed; at this time, the test state is automatically switched to the MBIST test state;
s4: entering an MBIST flow;
s5: until the test is completed;
s15: an external voltage supply applied to 023-Vcore3 (the third core voltage terminal) having a magnitude of a minimum core voltage, typically 0.9 Vcore3;
s16: the invalidation of MBIST_EN (test enable) is caused by either P-off CMD or 016-MBIST_EN (test enable); the Power off (Power off end) is enabled by the P-off CMD;
vcore2 is turned on to power up and all loads are reset by Vcore3 ok (third core voltage powered up flag);
s17: returning to the normal working state.
Note that: this power supply typically does not support internal voltage measurements, at least Vcore3 measurements.
FIG. 14 illustrates a low power consumption, off-site save-restore framework in accordance with the present technique. Comprising the following steps: 013-Wake up (Wake up signal end), 043-Standby logic, 033-GPIO (general purpose IO end), 063-Normal logic, 052-Non-Volatile Memory (nonvolatile Memory), 08-Isolated bias circuit;
among them, 043-Standby logic is generally combinatorial or low speed logic;033-GPIO (general purpose IO terminal) is used for user instruction operation (User configuration operation), for example, control of 052-Non-Volatile Memory (nonvolatile Memory), interaction with 063-Normal logic (standard domain logic), which can be a general purpose protocol and a custom protocol; 033-GPIO (general purpose IO terminal) can initiate a save field instruction; 013-Wake up (Wake-up signal end) is used for waking up, and can initiate a restore field instruction.
As shown in fig. 15, the low-power-consumption power-off on-site saving and restoring process in the technology of the invention is specifically realized as follows:
s1: applying 033-GPIO (general purpose IO terminal) through external operation, and solidifying the low power consumption control program to 052-Non-Volatile Memory through 063-Normal logic (standard domain logic);
s2: there are two modes of operation:
(1) Software operation: jump to a specified program space (pre-cure save function);
(2) Hardware operation: starting a Power off (Power off signal end) hardware to write and store, and saving the site;
s3: storing the data to a Non-Volatile Memory (nonvolatile Memory) appointed position;
s4: until the preservation is completed
S5: the SOC formally enters a Power off state;
s6: the external 013-Wake up (Wake-up signal end) starts a Wake-up flow;
s7: judging whether to start restoration according to the awakening mode;
(1) If the starting is still in principle, jumping to S8;
(2) If the principle is not still met, the step S12 is skipped;
s8: there are two modes of operation:
(1) Software operation: jump to a specified program space (pre-cure reduction function);
(2) Hardware operation: starting a Power off (Power off signal end) hardware to read and store, and restoring the site;
s9: reading from a Non-Volatile Memory (nonvolatile Memory) designated location;
s10: until the reduction is completed;
s11: continuing to execute the last Power off position;
s12: the start-up procedure initializes the execution flow.
It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solutions directly or indirectly to other relevant technical fields, all of which are included in the scope of protection of the present patent.

Claims (13)

  1. A cht technology processor power management design architecture, characterized by: the power management design architecture includes: the system comprises a standby area IO ring, a test area IO ring, a standard area IO ring, a standby domain, a test domain and a standard domain;
    the standby area IO ring is connected to an analog IO end, a universal digital IO end, a wake-up signal end and a first core voltage end, and an external IO domain high-voltage power supply end, a test enabling end and a first core voltage power-up completion identifier;
    the test area IO ring is connected to an external IO domain high-voltage power supply end, a test digital IO end, a third core voltage end, a test high-voltage power supply end, a power down signal end, a first core voltage power-up completion identifier and a third core voltage power-up completion identifier;
    the standard area IO ring is connected to an external IO domain high-voltage power supply end, a second core voltage end, a general digital IO end, an analog IO end, a power-down signal end, a test enabling end, a first core voltage power-up completion identifier and a third core voltage power-up completion identifier;
    the standby domain comprises a first voltage regulator, a second voltage regulator, standby domain logic, a dual-voltage power supply IP unit and a core voltage IP unit;
    the standard domain comprises a standard domain dual-voltage power supply IP unit, a standby domain dual-voltage power supply IP unit and standard domain logic;
    the test domain comprises test domain logic and a nonvolatile memory, the test domain logic is connected to the first core voltage power-up completion identifier, the third core voltage terminal and the third core voltage power-up completion identifier, and the test domain logic is connected to a test IO port and a test enabling terminal; and when the test enabling end takes effect, the second core voltage end is closed, the second core voltage power-up completion mark takes effect, and the test domain logic enters a test state.
  2. 2. The CHT technology processor power management design architecture of claim 1, wherein the internal interface information of the design architecture comprises:
    the first voltage regulator is connected to an external IO domain high-voltage power supply end, a first core voltage end and a first core voltage power-up completion identifier;
    the second voltage regulator is connected to the external IO domain high-voltage power supply end, the first core voltage end-of-power-up identifier, the power-down signal end, the test enabling end, the second core voltage end, the third core voltage end-of-power-up identifier, the third core voltage end and the third core voltage end-of-power-up identifier.
  3. 3. The CHT technology processor power management design architecture of claim 1, further comprising an IO isolation region, wherein the standby region IO ring, the test region IO ring, and the standard region IO ring are isolated by the IO isolation region.
  4. 4. The CHT technology processor power management design architecture according to any one of claims 1 to 3, wherein said standby area IO ring is connected to an analog IO port, a general IO port, a wake-up signal port, a first core voltage port, an external IO domain high voltage power supply port, a test enable port, and uses said first core voltage power up completion flag to perform power up bias and power down bias; the minimum system of the standby area IO ring comprises: the wake-up signal end, the external IO domain high-voltage power supply end, the test enabling end and the first core voltage power-up completion identification.
  5. 5. The CHT technology processor power management design architecture of any one of claims 1 to 3, wherein said test zone IO ring is connected to said external IO domain high voltage supply terminal, test digital IO terminal, third core voltage terminal, test high voltage supply terminal, and power-up and power-down biasing is performed using a power-down signal terminal, a first core voltage power-up completion flag and a third core voltage power-up completion flag, said minimum system of said test zone IO ring comprising: and the test digital IO end, the test high-voltage power supply end, the power-down signal end and the third core voltage are provided with a power-up mark.
  6. 6. The CHT technology processor power management design architecture of any one of claims 1 to 3, wherein said standard area IO ring includes said external IO domain high voltage power supply terminal, a second core voltage terminal, a general IO terminal, an analog IO terminal, and uses a power down signal terminal, a test enable terminal, a first core voltage power up completion flag, and a second core voltage power up completion flag to perform power up bias and power down bias; the minimum system of the IO ring of the test area comprises: the general IO end, the power-down signal end, the test enabling end and the second core voltage are powered up to be identified.
  7. 7. The CHT technology processor power management design architecture of claim 1 or2, wherein the processor chip internal circuitry is cut into: the standby domain, the test domain and the standard domain are isolated and biased by the cross-domain logic interaction signal through the isolation bias logic part.
  8. 8. The CHT technology processor power management design architecture of claim 7, wherein said standby domain further comprises a standby logic portion, a standby domain dual voltage power IP unit, a standby domain core power IP unit, said standby domain IO ring being employed externally for communication, said isolation bias logic portion being employed internally for communication; the second voltage regulator is divided into parts, such as one output path of Vcore2 and the other output path of Vcore3; the minimum system of the standby domain comprises: the first voltage regulator, the second voltage regulator, and the standby logic.
  9. 9. The CHT technology processor power management design architecture of claim 7, wherein said test domain comprises said test domain logic, nonvolatile memory, and wherein said test zone IO ring is used for communication to the outside and said isolation bias logic is used for communication to the inside.
  10. 10. The CHT technology processor power management design architecture of claim 7, wherein said standard domain comprises said standard domain dual voltage power IP unit, standard domain core power IP unit, standard domain logic, said standard zone IO ring is employed for communication, said isolation bias logic is employed for communication; the minimum system of the standard domain comprises: standard domain logic.
  11. 11. The CHT technology processor power management design architecture of claim 7, wherein said test domain and standard domain communicate logically directly through a logical network of test logic blocks and standard domain logic.
  12. 12. The CHT technology processor power management design architecture of claim 7, wherein said isolation bias logic is a core of cross-domain logic communication, said isolation bias logic being dedicated to isolation bias design.
  13. 13. The CHT technology processor power management architecture of any of claims 1-3, 8-12, wherein the test enabling terminal is configured to connect with a card pin.
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