CN115599611A

CN115599611A - Memory test method and device and computer equipment

Info

Publication number: CN115599611A
Application number: CN202211171891.8A
Authority: CN
Inventors: 卫博
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2022-09-26
Filing date: 2022-09-26
Publication date: 2023-01-13

Abstract

The application provides a memory test method, which is applied to a processor and comprises the following steps: determining a first virtual address of a break point of a tested memory; resolving to the physical address of the interrupt point according to the first virtual address of the interrupt point; saving the physical address of the interrupt point to a third party memory; in case of a continuation test, reading the physical address of the interruption point from the third-party memory; mapping according to the physical address of the interrupt point to obtain a second virtual address; and starting testing from the second virtual address to finish testing the memory. The method and the device can save the test progress in real time in the test process, and still can obtain the last memory test progress after powering off and powering on again so as to realize the memory continuous test. In the face of multiple parallel tests of the memories, under the condition that the test progress of each memory is inconsistent, the breakpoint continuous test of the memories is realized, so that the resource waste and the low test efficiency caused by the fault-free secondary test of the memories due to the emptying of the test progress are avoided.

Description

Memory test method and device and computer equipment

Technical Field

The embodiment of the application relates to the technical field of memory testing, in particular to a memory testing method and device and computer equipment.

Background

In order to meet the increasing performance requirements of processor services, more and more memories are configured, and the capacity is larger and larger, wherein with the continuous development of memory technology and the continuous increase of memory capacity, a memory pressure test needs to be performed on a supply chain by a processor in order to ensure the stability of the processor when the processor leaves a factory, and the more memories, the larger capacity leads to the longer memory pressure test time. How to save the memory pressure test time is an urgent problem to be solved.

Disclosure of Invention

In order to solve the foregoing problem, embodiments of the present application provide a method, an apparatus, and a system computer device for memory testing.

In a first aspect, an embodiment of the present application provides a method for testing a memory, which is applied to a processor and determines a first virtual address of an interrupt point of a memory to be tested; resolving to the physical address of the interrupt point according to the first virtual address of the interrupt point; saving the physical address of the interruption point to a third-party memory; under the condition of continuous measurement, reading the physical address of the interruption point from the third-party memory; obtaining a second virtual address according to the physical address mapping of the interruption point; and starting testing from the second virtual address to finish testing the memory. The method and the device can save the test progress in real time in the test process, and still can obtain the last memory test progress after powering off and powering on again so as to realize the memory continuous test. In the face of multiple parallel tests of the memories, under the condition that the test progress of each memory is inconsistent, the breakpoint continuous test of the memories is realized, so that the resource waste and the low test efficiency caused by the fault-free secondary test of the memories due to the emptying of the test progress are avoided.

In some embodiments, determining a first virtual address of a break point of a memory under test comprises: in the case of a current test interrupt, determining a first virtual address of a current interrupt point of a memory to be tested, wherein the case of the test interrupt comprises one of the following cases: operating system exceptions, memory Error Check and Correction (ECC) alarms, and processor handling faults. And the current test progress can be recorded after the CPU detects memory faults in the test process or other faults, such as abnormal restart and abnormal test interruption, in the memory test process.

In some embodiments, the memory test includes a plurality of memory concurrent tests, and the address file is generated according to SN information of the plurality of memories, the SN information being used to identify each of the plurality of memories. So as to mark each memory when facing multiple parallel tests of the memories.

In some embodiments, the memory being tested includes a plurality of memories, and determining the first virtual address of the break point of the memory being tested includes: acquiring a test address of each memory in a plurality of memories in real time; recording the test address of each memory in an address file; under the condition of testing interruption, according to the test address currently recorded in the address file, a first virtual address of an interruption point of each memory in the plurality of memories is obtained. Therefore, when multiple memories are tested in parallel, the current test address can be obtained in real time, and each memory and the test progress of each memory are recorded.

In some embodiments, the memory being tested includes a plurality of memories, and determining the first virtual address of the break point of the memory being tested includes: determining a memory which completes testing in a plurality of memories; and marking the first virtual addresses of the plurality of memories which are tested as test completion marks. When a plurality of memories are tested in parallel, the current test address can be obtained in real time, the test progress of each tested memory and each memory is recorded, and resource waste and low test efficiency caused by secondary test running during continuous time are avoided.

In some embodiments, resolving to the physical address of the interrupt point from the first virtual address of the interrupt point comprises: obtaining the physical address of the interrupt point corresponding to the first virtual address according to the mapping relation table of the first memory address; the mapping relation table of the first memory address is used for recording the mapping relation between the physical address of the interrupt point and the first virtual address. Therefore, the current test address Y can be obtained in real time, converted into a physical address through the memory address mapping relation table and stored in the third-party memory, and the purpose of recording the memory test address in real time is achieved.

In some embodiments, in the case of a continuation test, reading the physical address of the interruption point from the third party memory includes: determining the condition of continuous measurement of the memory under the condition of SN information of the memory matched through the address file; and under the condition of continuous measurement, reading the physical address of the interruption point from the third-party memory according to the SN information of the memory. The method can still obtain the testing progress of each memory under the condition of secondary parallel testing of the memories, takes the condition that a retest machine is replaced by a new memory into consideration, ensures that each memory is tested from a starting point to an end point, and covers the conditions of routine error reporting, abnormal restarting and testing interruption aiming at different complete machine fault conditions, and ensures that the corresponding testing progress of the memories can be saved.

In some embodiments, deriving the second virtual address from the physical address mapping of the interrupt point comprises: obtaining a second virtual address corresponding to the physical address of the interrupt point according to the mapping relation table of the second memory address; the mapping relation table of the second memory address is used for recording the mapping relation between the physical address according to the interrupt point and the second virtual address. Therefore, the physical address saved by the third-party memory can be processed into the virtual address required by the test script process in the test, the specified test starting address X set in the test script is replaced, and the test process is executed from the last test interrupt address

In some embodiments, the memory is determined to be newly tested under the condition that the SN information of the memory is not matched through the address file; and in the case that the memory is newly tested, starting testing from the entry address of the memory. Therefore, the condition that the re-testing machine is replaced by a new memory can be considered, and each memory is ensured to be tested from the starting point to the end point.

In a second aspect, an embodiment of the present application provides an apparatus for testing a memory, where the apparatus includes: the test progress storage module is used for determining a first virtual address of an interrupt point of a tested memory; resolving to the physical address of the interrupt point according to the first virtual address of the interrupt point; the physical address of the interrupt point is saved to the third party memory. The test progress acquisition module is used for reading the physical address of the interrupt point from the third-party memory under the condition of continuous test; mapping according to the physical address of the interrupt point to obtain a second virtual address; and starting testing from the second virtual address to finish testing the memory. The beneficial effects are as described in the first aspect, and are not described herein again.

In a third aspect, embodiments of the present application provide an electronic device comprising a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the electronic device to perform the method of any of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium comprising computer program instructions which, when executed by a computer, cause the computer to perform the method of any one of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer program product comprising instructions which, when executed by a computing device, cause the computing device to perform the method of any of the first aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments disclosed in the present specification, the drawings needed to be used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments disclosed in the present specification, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

The drawings that accompany the detailed description can be briefly described as follows.

Fig. 1 is a system architecture diagram of a method for memory testing according to an embodiment of the present disclosure;

fig. 2 is an interaction schematic diagram of a memory testing method according to an embodiment of the present disclosure;

fig. 3 is a flowchart of a method for testing a memory according to an embodiment of the present disclosure;

fig. 4 is a memory test continuation flow chart of the memory test method provided in embodiment 1 of the present application;

fig. 5 is a flowchart of the interrupt point address resolution provided in embodiment 2 of the present application;

fig. 6 is a flowchart of a method for testing a memory according to embodiment 3 of the present application;

fig. 7 is a schematic diagram illustrating parallel testing of multiple memories according to embodiment 4 of the present application;

fig. 8 is a schematic diagram illustrating a specific test progress of multiple memories at a memory failure time according to embodiment 4 of the present application;

fig. 9 is a schematic view of a test progress of each memory acquired from a third-party storage according to embodiment 4 of the present application;

fig. 10 is a schematic view of a test start address of each memory at the time of interruption in a test caused by a memory fault according to embodiment 4 of the present application;

fig. 11 is a schematic view of a test start address of each memory at intermittent time in a test caused by a non-memory fault according to embodiment 4 of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings.

In the description of the embodiments of the present application, the words "exemplary," "for example," or "exemplary" are used to indicate examples, illustrations, or illustrations. Any embodiment or design described herein as "exemplary," "for example," or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary," "for example," or "exemplary" is intended to present relevant concepts in a concrete fashion.

In the description of the embodiments of the present application, the term "and/or" is only one kind of association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time. In addition, the term "plurality" means two or more unless otherwise specified. For example, the plurality of systems refers to two or more systems, and the plurality of terminals refers to two or more terminals.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the indicated technical feature. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically stated.

In the description of the embodiments of the present application, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and may be combined with each other without conflict.

In the description of the embodiments of the present application, the terms "first \ second \ third, etc. or module a, module B, module C, etc. are used merely for distinguishing between similar objects and not for indicating a particular ordering of the objects, it being understood that specific orders or sequences may be interchanged where permitted to implement the embodiments of the present application described herein in an order other than that illustrated or described herein.

In the description of the embodiments of the present application, reference numbers indicating steps, such as S110, S120 \ 8230; \8230, etc., do not necessarily indicate that the steps are performed, and the order of the steps before and after the steps may be interchanged or performed simultaneously, where allowable.

In the description of the embodiments of the present application:

memory mapping is a mechanism that maps a portion of a file or the entire file on a disk to an address range in the application address space from a file to a block of memory, and then the application can access the file on the disk in the same way as accessing dynamic memory.

Virtual memory is a technique for system memory management that allows an application to think that it has continuously available memory-a continuous complete address space, in fact a program is usually partitioned into multiple physical memory fragments, and portions are temporarily stored on external disk storage for data exchange when needed. The program is oriented to a virtual address space, and the program content can be regarded as running in the virtual address space, and the virtual address space is actually mapped to a physical address space finally. A mapping relationship table (MMU) of virtual addresses and physical addresses is stored in a Dynamic Random Access Memory (DRAM).

The switching area is actually a disk space (hard disk space), when the virtual memory is mapped with the physical memory, the code of the virtual memory is put into the switching area, when the CPU wants to execute the related instruction or data, if the memory does not exist, the CPU firstly goes to the switching area to map the required instruction and data to the physical memory, and then the CPU executes the instruction and data.

The physical address is a memory address of the CPU accessing the memory data, the CPU is required to give an address of a memory unit when accessing the memory, and each memory unit has a unique physical address. Illustratively, for an 8086CPU, physical address = segment address x16+ offset address. The segment address refers to a 16-bit address bus of 8086cpu, and the offset address also refers to a 16-bit address bus.

A script is a computer language that is made up of program code.

The memory test script is a program code for detecting a memory failure.

The SN information of the memory is a Serial Number (SN) of the memory, and is used for identifying each of the plurality of memories, and the SN information includes a model number, a version number, a capacity size, a year, a month, a day, and the like.

A Memory Controller (IMC).

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In a first scheme, an Operating System (OS) obtains a zero start address of a memory entry by running a memory test script or a third-party test tool, and starts to run a memory test program from the zero start address of the memory entry to perform a coverage test on performance, stability, and the like of a memory. If the CPU detects memory failure or detects other failures in the memory test process, including abnormal restart and abnormal test interruption, the machine processor processes the failure, and after the failure is repaired by replacing the memory or other ways and the memory test is started again, the memory test script or the third-party test tool is operated again under the operating system to enable the memory to start the test from the zero starting point address of the memory entry, namely, the memory test is started again.

In the current memory test flow, after memory replacement or other fault processing causing test interruption is completed, when the test is restarted, the previous memory test progress is cleared, so that the whole test time is prolonged.

In the actual supply chain production test process, the problems of memory Error Checking and Correcting (ECC) alarm or abnormal restart of the OS often occur in the run-out test stage of the processor complete machine. For the memory ECC alarm problem, because the memory is a multi-layer (rank) multi-chip (chip) parallel test, the following two situations often occur:

the first condition is as follows: and the processor does not immediately power off to terminate the test after the memory ECC alarm occurs, and replaces the fault component after running out one round of memory pressure test. And after the memory components are replaced by power on and power off, the testing progress is cleared, and no matter what the result is, the memory which passes through in the first round of pressure testing needs to be run for retesting in the second round. With the development of the technology, the memory capacity is larger and larger, and the influence of the test duration brought by the full allocation of the large capacity is larger.

Case two: and after detecting the memory ECC alarm, the processor immediately reports fault information and terminates the test, the test progress of each memory is different when the test is terminated, and all the memory test progress is reset after the memory components are replaced by power-on and power-off.

For test stopping after encountering other faults in the process of testing the processor, such as abnormal restart of the processor, power-on and power-off of the processor and the like including replacement of a fault part for retesting, the memory needs to be tested from the beginning, and the test efficiency is also reduced.

The memory test method provided by the embodiment of the application realizes the memory test progress preservation and the specified interrupt point address continuous test by changing the processing mechanism of the memory test when the problems such as faults and test interruption occur, thereby achieving the purposes of reducing the retest time and improving the test efficiency.

Fig. 1 is a system architecture diagram of a memory testing method according to an embodiment of the present disclosure. As shown in fig. 1, the embodiment of the present application is mainly implemented by matching a memory test script 11 and a third-party storage 12 which are disposed in an operating system.

The memory test script 11 runs in the operating system by using the virtual address of the memory, so that a larger running space is obtained, and meanwhile, the processor tests the memory through the memory test script 11 to obtain the real-time address as the virtual address.

After the processor is powered on or powered off again or restarted, the address of the memory is remapped, the virtual address is updated, the physical address is unchanged, and the physical address of the interrupt point of the memory is used as the interrupt point mark address and stored in the third-party memory.

In some embodiments, the memory test script 11 includes an address resolution module 111, an address determination module 112, and an address mapping module 113.

The address resolution module 111 is configured to obtain a physical address Y of the interrupt point by resolution according to the virtual address Y1; and storing the physical address Y of the interrupt point to a third-party memory, wherein the virtual address Y1 is the mapping of the physical address Y before the test interrupt.

The address determination module 112 is configured to, in case of a continuous test, read the physical address Y of the interrupt point from the third-party memory; and mapping the physical address Y of the interrupt point to obtain a virtual address Y2.

The memory test script 11 starts the test from the virtual address Y2, and the virtual address Y2 is the mapping of the physical address Y after the retest.

The address mapping module 113 is configured to determine a mapping relationship between the physical address Y of the interrupt point and the virtual addresses Y1 and Y2.

Fig. 2 is an interaction schematic diagram of a memory testing method according to an embodiment of the present disclosure. As shown in fig. 2, the memory address is marked to implement the interrupt point continuation test by the following steps.

S21, when the processor runs the test script after being electrified, the mapping relation table 1 is obtained from the OS, and the mapping relation between the physical address and the virtual address of the memory is determined. The mapping relationship table 1 at this time can be referred to as a first mapping relationship table.

S22, under the condition of memory test interruption, obtaining the virtual address Y1 of the memory interruption point, converting the virtual address Y1 of the interruption point into the physical address Y of the interruption point according to the mapping relation table 1, and writing the physical address Y into the third-party memory. The virtual address y1 of the interrupt point at this time may be recorded as the first virtual address.

S23, when the processor continuously measures the memory again, the updated mapping relation table 2 is obtained from the OS; the mapping relation table 2 is denoted as a second mapping relation table.

And S24, obtaining the physical address Y of the interrupt point from the third-party memory, converting the physical address Y into the virtual address Y2 through the mapping relation table 2 to obtain a second virtual address of the interrupt point, and continuously measuring from the virtual address Y2.

In the method for testing a memory provided in the embodiment of the present application, a mapping table of a virtual address and a physical address of the memory is stored in a physical memory DRAM, an OS is responsible for maintaining contents of the mapping table and transferring the page table back and forth between a disk and the physical memory, a processor converts the physical address into a virtual address of a corresponding interrupt point through the mapping table, and refreshes a value of a start X of the test to be equal to an interrupt point virtual address y. The processor executes the test process to find the memory unit of the corresponding interrupt point to start testing, continuously obtains the virtual address of the current memory test, performs mapping translation and stores the virtual address in the third-party memory to form an address file named by the corresponding SN, wherein the content of the address file comprises SN information and test address information of the memory.

Fig. 3 is a flowchart of a memory testing method according to an embodiment of the present disclosure. As shown in fig. 3. The method comprises the following steps: s31, determining a first virtual address of an interruption point of a tested memory; s32, resolving according to the first virtual address of the interrupt point to obtain the physical address of the interrupt point; s33, storing the physical address of the interruption point in a third-party memory; s34, reading the physical address of the interruption point from the third-party memory under the condition of continuous measurement; s35, mapping according to the physical address of the interrupt point to obtain a second virtual address; and S36, starting testing from the second virtual address to finish testing of the memory.

The method for testing the memory provided by the embodiment of the present application is described in detail below with respect to each of the above steps.

S31, determining a first virtual address of the break point of the tested memory.

In some embodiments, step S31 may be implemented by performing the following steps S311-S314.

S311, the processor is powered on to start running the memory test script, and a mapping relation between the physical memory address and the virtual memory address is established to obtain a mapping relation table 1 of the memory address. And recording a mapping relation table 1 of the memory address as a first mapping relation table.

Illustratively, when the processor runs the test script after being powered on, the mapping relation table 1 of the memory address is obtained from the OS to obtain the correspondence relation between the physical address and the virtual address of the memory.

In some embodiments, the method includes testing a plurality of memories in parallel, and when the processor runs the test script after being powered on, obtaining the mapping relation table 1 of the memory addresses from the OS to obtain the corresponding relation between the physical address and the virtual address of each of the plurality of memories.

S312, generating an address file according to the SN information of the memories, wherein the SN information of the memories is used for identifying each memory; and storing the address file in a third-party memory.

In some embodiments, the memory test includes a parallel test of a plurality of memories, and a plurality of address files named by SN information of the memories may be generated according to SN information of each of the plurality of memories. The content of each address file comprises SN information and a test address of the memory.

S313, in the process of testing the memory, recording the current test address y of the memory in the address file in real time. The current test address y is a virtual address.

In some embodiments, the address return value of the current test function may be obtained in real time, and the current test address y of the memory may be determined.

In some embodiments, the memory to be tested includes a plurality of memories, and the SN information of each memory and the test address y information of each memory may be recorded in an address file, where the file is named by the SN of each memory.

In some embodiments, the information of the test address y of each memory may be recorded or updated at intervals. Illustratively, the test address y may be refreshed 1 time every 5 minutes to ensure real-time performance of the address information.

S314, under the condition of test interruption, obtaining the virtual address y1 of the current interruption point of the memory according to the current test address recorded in real time.

In some embodiments, the virtual address y1 of the current interrupt point of each memory in the plurality of memories may be obtained according to the current test address recorded in the address file.

The memory test interruption condition includes test interruption caused by non-memory fault and test interruption caused by memory fault.

Illustratively, test interrupts caused by non-memory faults include operating system exceptions, processor processing faults, abnormal power down or abnormal restart, and the like.

Illustratively, the test interruptions caused by memory failures include memory Error Checking and Correction (ECC) alarms, and the like.

For test interruption caused by non-memory failure, the last updated test address is taken as the virtual address y1 of the interruption point. Illustratively, the test address of the last recording update is 53H, and the virtual address of the discontinuity is y1=53H.

For test interruption caused by memory failure, the memory needs to be replaced by a new memory or be subjected to other processing such as plug replacement, and the zero address of the memory entry can be the virtual address y1. Illustratively, the zero address of the memory/new memory is 00H, then the virtual address of the interrupt point y1=00H.

In some embodiments, the memory to be tested includes a plurality of memories, and the memory of the plurality of memories, which has been tested, is determined in the case of test interruption; and marking the virtual addresses y1 of the plurality of memories which are tested to be test completion identifications.

For example, the virtual address y1 of the break point of the memory for completing the test may be set to y1= Z, where Z is a test completion flag.

For example, the virtual address y1 of the interrupt point of the memory where the test is completed may be set to y1=0ffh,0ffh as the test completion flag.

S32, resolving according to the first virtual address of the interruption point to obtain the physical address of the interruption point.

In some embodiments, step S32 determines the physical address of the interruption point by the following step S321.

S321, obtaining the physical address Y of the interrupt point corresponding to the virtual address Y1 according to the mapping relation table 1 of the memory addresses; the mapping relation table 1 of the memory address is used for recording the mapping relation between the physical address of the interrupt point and the virtual address y1.

Illustratively, the virtual address of the interrupt point is Y1=53H, and the corresponding physical address Y =0B153H is obtained according to the mapping relation table 1 of the memory addresses.

In some embodiments, when multiple memories are interrupted, the physical address of each interruption point corresponding to the virtual address y1 of the multiple memories may be obtained according to the mapping relation table 1 of the memory addresses.

Exemplarily, in the memories, the memory 1 is a non-memory fault, which causes test interruption, the virtual address is Y1=53H, and the corresponding physical address Y1=0B153H is obtained according to the mapping relation table 1 of the memory addresses; the memory 2 is interrupted due to memory failure, the virtual address is Y1=00H, and the corresponding physical address Y1=0B000H is obtained according to the mapping relation table 1 of the memory addresses; the memory 3 is tested, the virtual address is Y1=0FFH, and the corresponding physical address Y1=0FFFFH or Y1= Z is obtained according to the mapping relation table 1 of the memory addresses.

And S33, saving the physical address of the interruption point to a third-party memory.

In some embodiments, the physical address of each interrupt point corresponding to multiple memories may be saved to a third party storage.

It should be noted that, if the processor cannot normally run and cannot record the current state and the physical address of the interrupt point, the physical address Y of the interrupt point stored in the third-party memory last time is defined as the criterion.

For test interruption caused by memory failure, a Basic Input Output System (BIOS) BIOS of a processor can locate a specific memory failure, and for the type of failure, memory replacement is necessary, the memory is replaced with a new memory, and after power-on recovery test, the start test of the memory can be determined according to SN information of the memory stored in a history.

And S34, reading the physical address of the interrupt point from the third-party memory under the condition of continuous measurement.

In some embodiments, step S34 determines that the current memory is a retest condition through steps S341-S342 below.

S341, after powering on again, the processor obtains the updated mapping relationship table 2 from the OS, where the mapping relationship table 2 is used to record the mapping relationship between the physical address Y and the virtual address Y2 according to the interrupt point.

And S342, determining the continuous testing condition of the memory test according to the SN information of the memory.

In some embodiments, the processor configures a plurality of memories, the processor calls the history records stored in the address file to obtain SN information of the plurality of memories after the processor is powered on again, and the SN information of the memory matched with the address file can determine the condition of continuous testing of the memory test.

Under the condition that the SN information of the memory is matched by the address file, it is determined that the memory is continuously tested, and S343 is performed.

If the SN information of the memory is not matched with the address file, it indicates that the memory is a new memory, and it may be determined that the new memory is to be tested, and S35 is executed.

And S343, under the condition of continuously testing the memory, reading the physical address Y of the interrupt point corresponding to the memory from the third-party memory according to the SN information of the memory.

In some embodiments, in the case of continuously testing the memory, the physical address Y corresponding to the interrupt point of the memory is read from the third-party storage according to the SN information of the memory, and if the value of the physical address Y is the memory test completion flag, it indicates that the memory has completed the test, and the memory is no longer tested.

Illustratively, the physical address Y =0B153H of the interrupt point of the corresponding memory is read from the third-party storage according to the SN information of the memory.

For example, the memory test completion flag may be set to Z or 0FFFFH, and the physical address Y = Z or Y =0 ffffffh of the break point of the corresponding memory is read from the third-party storage, which indicates that the memory has been tested and may not be tested any more.

In some embodiments, the processor configures a plurality of memories, the third-party storage stores interrupt point information of the plurality of memories, and physical addresses corresponding to interrupt points of the plurality of memories can be read from the third-party storage according to SN information of the memories.

Illustratively, the physical address Y1=0B153H of the interrupt point of the memory 1 is read from the third party storage according to the SN information of the memory 1; and reading the physical address Y2=0FFFFH of the interruption point of the memory 2 from the third-party storage according to the SN information of the memory 2.

And S35, mapping the physical address of the interrupt point to obtain a virtual address y2.

In some embodiments, the virtual address y2 corresponding to the physical address of the interrupt point may be obtained according to the mapping relation table 2; the mapping relation table 2 of the memory addresses is used for recording the mapping relation between the physical address Y and the virtual address Y2 according to the interrupt point.

Illustratively, the physical address of the interrupt point of the corresponding memory read from the third-party storage according to the SN information of the memory is Y =0B153H, and the virtual address of the corresponding interrupt point obtained according to the mapping relation table 2 of the memory addresses is Y2=10H.

In some embodiments, in the case that the memory is newly tested, the default entry address of the memory is used as the test start address X.

Illustratively, the virtual address of the break point of the memory may be set to y2=00H, and the test starts from the beginning.

In some embodiments, when the multiple memories are interrupted, the virtual address y2 corresponding to the physical address of the interruption point of each memory in the multiple memories may be obtained according to the mapping relation table 2 of the memory addresses.

Exemplarily, in the multiple memories, the physical address Y1=0B153H of the memory 1 obtains the virtual address of the corresponding interrupt point according to the mapping relation table 2, and the virtual address is Y2=10H; the physical address Y2=0FFFFH or Y1= Z of the memory 2, and the virtual address corresponding to the interrupt point is obtained as Y2=0FFH according to the mapping relation table 2 of the memory addresses.

And S36, starting testing from the second virtual address to finish testing of the memory.

Illustratively, if the memory 1 is a non-memory fault, which causes the test to be interrupted, the virtual address y2=10H, and the test is started from 10H until the test of the memory is completed. The memory 2 is a new memory which is replaced after the test is interrupted due to the memory fault, and the test is started from the entry address of the memory 2 until the test of the memory is completed when the virtual address y2= 00H. The memory 3 is a memory which has already been tested, and if the virtual address y2=0FFH, no test is required.

The memory testing method provided by the embodiment of the application can be used for storing the testing progress of the memory in real time in the testing process, and still obtaining the last testing progress of the memory after the middle power-off and the power-on are carried out again so as to realize the continuous testing of the memory. In the face of multiple parallel tests of the memories, under the condition that the test progress of each memory is inconsistent, resource waste and low test efficiency caused by fault-free secondary memory test accompanying caused by test progress emptying are avoided by realizing memory breakpoint continuous test. The method for testing the memory can realize efficient gapless testing of the whole area of the memory.

Example 1

Fig. 4 is a memory test continuation flow chart of the memory test method provided in embodiment 1 of the present application. As shown in fig. 4, the determination of the interrupt point address in the memory test includes the following steps:

and S41, powering on to run the memory test script.

S42, setting the test starting address of each memory as X, wherein X is the starting address of the memory test.

S43, determining whether the current memory is a measurement-continuing memory, and if the current memory is a measurement-continuing memory, executing S44. If the determination result is that the memory is not tested continuously, S45 is executed.

For example, the SN information of the memory may be matched according to the history record stored in the address file, if the SN information of the memory is stored in the history record, the current memory is a continuous memory, and if the SN information of the memory is not stored in the history record, the current memory is a non-continuous memory/a new memory.

And S44, the physical address Y of the interrupt point of the current memory is obtained from the third-party memory.

Specifically, the physical address Y of the interrupt point corresponding to the current memory may be obtained from the third-party storage through the SN information of the memory.

And S45, converting the physical address Y of the interruption point into a virtual address Y through the mapping relation table.

S46, addressing with a starting address of X = Y by a Memory Controller (IMC), and finding a virtual address Y corresponding to the break point physical address Y of the Memory.

S47, the test script continues to execute the test from the virtual address y.

S48, testing the memory from the beginning, wherein the testing starting address X is the default entry address of the memory.

The memory is tested through the steps S41-S48.

The memories are tested in parallel, and the interrupt point address Y corresponding to each memory configured by the machine is refreshed in the actual operation process.

Example 2

Fig. 5 is a flowchart of the interrupt point address resolution provided in embodiment 2 of the present application. When the processor executes the memory test script to test the memory, the current test address y is obtained in real time, and is converted into a physical address through the mapping module 113 to be stored in the address file, so that the purpose of recording the test address of the memory module in real time is achieved. As shown in fig. 5. The method comprises the following steps:

and S51, starting the test, namely recording the current test address Y in real time every 5 minutes.

And S52, judging whether the test interruption occurs or not. If the judgment result is "yes", the step S53 is executed; and if the judgment result is 'no', executing the test script until the test is finished.

Specifically, the test interruption includes one of a test interruption caused by a non-memory failure and a test interruption caused by a memory failure.

S53, judging whether the processor normally operates, and if so, executing S54; if the judgment result is "no", S56 is executed.

S54, judging whether to continue the memory test, and if so, executing S55; if the judgment result is "no", S57 is executed.

And S55, normally testing the memories until the memories are finished, recording the testing address Y of each memory at the moment when the final testing is finished, and if the whole memory is tested, recording the physical address Y = Z in an address file of a third-party memory, wherein Z is a mark that the memory is tested.

S56, the test is finished, the test address y of the latest interruption point is recorded, and S58-S59 are executed.

And S57, after the test is finished, recording the test address y of the interrupt point of the current abnormal point memory, and executing S58-S59.

And S58, converting the test address Y into a physical address Y according to the mapping relation table 2 of the memory address.

And S59, storing the physical address Y in a third-party memory.

In some embodiments, if a test interrupt caused by a non-memory failure occurs, the following steps S521-S522 may be performed, respectively.

And S521, when the machine processor normally runs and the memory test continues until the test is finished, recording the test address y of each memory bank at the last test completion moment, and when the whole memory finishes the test, recording the test address y = Z to indicate that the memory finishes the test.

S522, under the condition that the machine processor is running and the memory test is interrupted, recording the test address y of each memory interrupt point at the current test interrupt time, and if the current entire memory bank has been tested, recording the test address y = Z, which indicates that the memory has been tested.

S522, the machine processor runs abnormally, and if the processor fails to run normally after the test is finished, the test address Y of the current memory cannot be recorded, and the physical address Y of the interrupt point stored in the third-party memory last time is defined as the criterion.

In some embodiments, if a memory failure occurs during the test process, such as a memory ECC failure, the following steps S523 to S525 are performed respectively.

S523, when the processor normally operates, the memories are continuously tested, and until the test is completed, the test address y of each memory at the current time is recorded for the multiple memories, and if the memory space of the memory 1 has completely completed the test, the test address y = Z of the memory 1 is recorded, which indicates that the memory 1 has completed the test; for the memory 2 with a fault, because a new memory needs to be replaced or a test needs to be performed by plugging again, the entry address of the memory 2 may be the test address y of the interrupt point.

S524, under the conditions that the processor normally runs, the memory test is interrupted, and the test process is finished, recording the test address y of each memory at the current interruption moment for a plurality of memories, and recording the test address y of the interruption point of the memory 1 at the current interruption moment if the current memory 1 is normal and has no fault; for the memory 2 with memory failure, because a new memory needs to be replaced or a new memory needs to be plugged and unplugged again, the entry address of the memory 2 may be the test address y of the interrupt point.

S525, under the conditions that the processor runs abnormally, the memory test is interrupted, and the test is finished, for a plurality of memories, because the processor cannot run normally, the current test state and the breakpoint address cannot be recorded, the test address Y of the interruption point of the memory 1 is determined according to the physical address Y of the interruption point of the memory 1 stored on the third-party memory last time; the processor cannot normally operate due to the memory 2 failure, the BIOS locates a specific memory failure, and the memory 2 needs to be replaced for the type of failure.

In some embodiments, when the processor runs the test script to test the memory, the address return value of the current test function, that is, the current test address y of the memory, may be obtained in real time, and when the memory is tested, the SN information of each memory and the test address y of each memory are recorded in an address file, where the address file is named by the SN of each memory, and the test address y of each memory is refreshed 1 time at intervals to ensure the real-time performance of the address information.

Example 3

Fig. 6 is a flowchart of a memory testing method according to embodiment 3 of the present application. As shown in fig. 6, after the processor powers on and starts the memory test script, the following steps are performed:

s61, after the processor is powered on and started, a mapping relation table of the memory physical address and the virtual address is established, and a mapping relation table 1 of the memory address is obtained.

And S62, judging whether the current memory is the memory to be tested continuously, if not, executing S63. If the determination result is "yes", the current memory is the memory to be tested, and S64 is executed.

S63, starting the test from the initial address X of the memory.

And S64, the processor carries out continuous testing, and the initial address X = Y of the memory test is refreshed. Includes the following steps S641-S644:

s641, reading the physical address Y of the breakpoint from the third-party memory.

S642, determining the physical address Y of the interrupt point of each memory according to the SN information of the memory, and refreshing the test starting address X = Y of each memory.

S643, each memory starts testing from the second virtual address corresponding to the physical address Y of the break point.

S644, if the test interruption happens in the test process, the test address y is continuously updated, if the test is normally finished, the memory test completion mark Z is updated, and the whole test process is finished.

And S65, acquiring the current test address y of the memory in real time in the process of testing the memory.

And S66, judging whether the test interruption occurs, if so, executing S67, and if not, executing S67.

And S67, recording the current test address Y under the condition of test interruption or memory error, mapping the test address Y into a physical address Y and storing the physical address Y in a third-party memory.

S68, if no test interruption condition or memory error report problem occurs until the test is finished, completing a normal one-time test, and updating the test address y of the memory to be the test completion mark Z. The physical address Y of the interrupt point is updated to the test completion flag Z.

Example 4

In the method for testing a memory according to embodiment 4 of the present application, the following steps S71 to S74 are performed to implement a parallel test of multiple memories.

S71, after the processor is powered on for the first time, a parallel test is started from the entry address of each memory.

As shown in FIG. 7, the processor is configured with DIMMs 1-8, for a total of 8 memories, with X defaulting to the starting address.

And S72, in the process of parallel testing, testing interruption caused by memory faults, and recording the physical address Y of an interruption point in a third-party memory to obtain the testing progress at the moment of testing interruption.

As shown in fig. 8, at the time of a memory failure, the specific test progress of each memory is different, the test progress is identified by a gray block, and the position where the gray block arrives indicates the virtual address of the break point in each memory.

Illustratively, at the time of a memory failure, the specific test progress of each memory in DIMMs 1-DIMM8 is Y1-Y8, respectively, and the physical addresses Y1-Y8 of the interruption points of DIMMs 1-DIMM8 at the time of the memory failure can be stored in the third party memory when the processor is operating normally. Wherein DIMM5 is the memory that has been tested normally, DIMM7 is the memory that has failed the memory, DIMM8 is the memory that has been tested from the beginning.

And S73, after the plugging and unplugging processing is carried out on the failed memory DIMM7, the processor is powered on again for testing, and the updated memory address mapping table 2 is obtained from the OS. And the processor acquires the initial test address of each memory from the third-party memory according to the SN information of the memory.

As shown in FIG. 9, according to the test progress of each memory obtained from the third party storage, the test start address of each memory in DIMM1-DIMM8 is X1-X8, and X1-X8 are virtual addresses mapped to the physical addresses Y1-Y8 of DIMM1-DIMM8 stored in the third party storage. The DIMM7 is a memory with memory failure, and its test start address X is an entry address.

It should be noted that, for the failed DIMM7, the test is started again by default when the memory is replaced with a new memory or other processes such as plug-in replacement are performed; for memories interrupted in other normal test processes, starting the test from the breakpoint address X = Y; for a memory with X = Z, the memory has already been tested and does not need to be tested again. Therefore, the memory test method provided by the application can improve the efficiency of memory test.

In some embodiments, the memory failure processing, memory replacement, or plug-in processing may be performed after the test is completed.

As shown in fig. 10, after the memory failure processing performed after the test is completed, DIMMs 1-DIMM6 and DIMM8 are all tested, wherein the breakpoint addresses are both X = Z, and the processor is re-powered on to test only the failed memory DMM7 starting from the entry address.

And S74, if the test is abnormally interrupted due to non-memory faults, such as abnormal power failure or abnormal restart of the processor, and the processor cannot record the current state in time, taking the physical address Y which is stored in the third-party memory and tested at the latest moment as an interrupt point address.

As shown in fig. 11, after the processor is re-tested, the physical address Y of the interrupt point recorded at the previous time is read from the third-party memory, the test address X corresponding to each memory bank is refreshed according to the address mapping table 2, and the test is continued from the start address X of the interrupt point. Such as.

The memory testing method provided by the embodiment of the application does not limit and control the number of the memories, and can realize the interrupt point continuous testing of the memories for parallel testing or serial testing.

The method for testing the memory provided by the embodiment of the application continuously saves the testing progress of the memory in the testing process, and can still obtain the last testing progress of the memory after the middle power-off and the power-on are carried out again, so that the continuous testing of the memory is realized.

The memory testing method provided by the embodiment of the application is used for the memory multi-Rank parallel testing, and under the condition that the testing progress of each memory is inconsistent, resource waste caused by fault-free memory secondary testing running due to the fact that the testing progress is empty is avoided and the testing efficiency is reduced by realizing the break-point continuous testing in the memories. Compared with the method for testing the memory from the starting point to the full test, the method for testing the memory provided by the embodiment of the application has no difference in fault excitation, and can realize the test of the memory in the full area.

The embodiment of the application establishes a mechanism for reading and storing the test address in real time in the process of testing the memory, processes the stored physical address into the virtual address required by the process of the test script in the next test, and replaces the content of the specified test starting address X set in the test script, so that the test process is executed from the last test interrupt address. The method solves the problem that the memory test progress can not be stored in the machine and the system, and further realizes that the memory area can be appointed to execute the test content.

The embodiment of the application provides a device for testing a memory, which comprises: the test progress storage module is used for determining a first virtual address of an interrupt point of a tested memory; resolving to the physical address of the interruption point according to the first virtual address of the interruption point; saving the physical address of the interrupt point to a third party memory; the test progress acquisition module is used for reading the physical address of the interrupt point from the third-party memory under the condition of continuous test; mapping according to the physical address of the interrupt point to obtain a second virtual address; and starting testing from the second virtual address to finish testing the memory.

The embodiment of the application provides an electronic device, which comprises a processor and a memory; the processor is configured to execute the instructions stored in the memory to cause the electronic device to perform the method according to any of the above embodiments.

A computer-readable storage medium includes computer program instructions, and when the computer program instructions are executed by a computer, the computer executes the method according to any one of the above embodiments.

The present application provides a computer program product containing instructions, which when executed by a computing device, cause the computing device to perform the method according to any one of the above embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

Moreover, various aspects or features of embodiments of the application may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips, etc.), optical disks (e.g., compact Disk (CD), digital Versatile Disk (DVD), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROM), card, stick, key drive, etc.). In addition, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

It should be understood that, in various embodiments of the present application, the sequence numbers of the above-mentioned processes do not imply any order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not limit the implementation processes of the embodiments of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application, which essentially or partly contribute to the prior art, may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or an access network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present application, and all the changes or substitutions should be covered by the scope of the embodiments of the present application.

Claims

1. A method for testing a memory, applied to a processor, the method comprising:

determining a first virtual address of a break point of a tested memory;

resolving to the physical address of the interrupt point according to the first virtual address of the interrupt point;

saving the physical address of the interrupt point to a third party memory;

in case of a continuation test, reading the physical address of the interruption point from the third-party memory;

mapping according to the physical address of the interrupt point to obtain a second virtual address;

and starting testing from the second virtual address to finish testing the memory.

2. The method of claim 1, wherein determining the first virtual address of the break point of the memory under test comprises:

determining a first virtual address of a current interrupt point of the tested memory in case of a current test interrupt, wherein the case of the test interrupt includes one of the following cases: operating system exceptions, memory Error Check and Correction (ECC) alarms, and processor handling faults.

3. The method according to any of claims 1-2, wherein the memory test comprises a plurality of memory concurrent tests, and wherein an address file is generated according to SN information of the plurality of memories, the SN information identifying each of the plurality of memories.

4. The method of claim 3, wherein the tested memory comprises a plurality of memories, and wherein determining the first virtual address of the break point of the tested memory comprises:

acquiring a test address of each memory in the plurality of memories in real time;

recording the test address of each memory in the address file;

and under the condition of test interruption, acquiring the interruption point first virtual address of each memory in the plurality of memories according to the test address currently recorded by the address file.

5. The method according to any one of claims 1-4, wherein the memory under test comprises a plurality of memories, and the determining the first virtual address of the break point of the memory under test comprises:

determining a memory which completes the test in the plurality of memories;

and marking the first virtual addresses of the plurality of memories which are tested as test completion marks.

6. The method according to any of claims 1-5, wherein resolving to a physical address of a break point from the first virtual address of the break point comprises:

obtaining the physical address of the interrupt point corresponding to the first virtual address according to a mapping relation table of the first memory address; and the mapping relation table of the first memory address is used for recording the mapping relation between the physical address of the interruption point and the first virtual address.

7. The method according to claims 1-6, wherein reading the physical address of the breakpoint from the third party memory in case of a continuation test comprises:

determining the condition of continuous measurement of the memory under the condition of SN information of the memory matched through the address file;

and under the condition of continuous measurement, reading the physical address of the interruption point from the third-party memory according to the SN information of the memory.

8. The method according to claims 1-7, wherein deriving a second virtual address from a physical address mapping of the interrupt point comprises:

obtaining a second virtual address corresponding to the physical address of the interrupt point according to the mapping relation table of the second memory address; and the mapping relation table of the second memory address is used for recording the mapping relation between the physical address and the second virtual address according to the interrupt point.

9. The method of claim 7, comprising:

determining the memory as a newly-measured condition under the condition that the SN information of the memory is not matched through an address file; and under the condition that the memory is newly tested, starting testing from the entry address of the memory.

10. An apparatus for memory testing, the apparatus comprising:

the test progress storage module is used for determining a first virtual address of an interrupt point of a tested memory; resolving to the physical address of the interrupt point according to the first virtual address of the interrupt point; saving the physical address of the interruption point to a third party memory.

The test progress acquisition module is used for reading the physical address of the interruption point from the third-party memory under the condition of continuous test; mapping according to the physical address of the interrupt point to obtain a second virtual address; and starting testing from the second virtual address to finish testing the memory.

11. An electronic device comprising a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the electronic device to perform the method of any of claims 1-9.

12. A computer-readable storage medium comprising computer program instructions which, when executed by a computer, cause the computer to perform the method of any one of claims 1-9.

13. A computer program product comprising instructions which, when executed by a computing device, cause the computing device to perform the method of any of claims 1-9.