CN115598495A

CN115598495A - Chip test configuration generation method, test method and device and electronic equipment

Info

Publication number: CN115598495A
Application number: CN202211130656.6A
Authority: CN
Inventors: 许荣峰; 林哲民
Original assignee: Shenzhen Qipule Chip Technology Co ltd
Current assignee: Shenzhen Qipule Chip Technology Co ltd
Priority date: 2022-09-16
Filing date: 2022-09-16
Publication date: 2023-01-13
Anticipated expiration: 2042-09-16
Also published as: CN115598495B

Abstract

The application discloses a chip test configuration generation method, a test method, a device and electronic equipment, wherein the chip test configuration generation method is based on a chip with a programmable interconnection network, and can automatically generate a wiring configuration information set comprising at least one item of wiring configuration information by acquiring a configuration information set to be tested comprising at least one item of configuration information to be tested and executing wiring processing on each item of configuration information to be tested in the configuration information set to be tested, and each item of configuration information to be tested corresponds to one item of wiring configuration information, so that the automatic design of a packaging interface can be quickly realized, and if RMA analysis after testing does not meet requirements, only the configuration information set to be tested needs to be revised again, and a new wiring configuration information set is automatically generated, thereby reducing hardware change risks and reducing development period and cost.

Description

Chip test configuration generation method, test method and device and electronic equipment

Technical Field

The present application relates to the field of chip testing technologies, and in particular, to a chip test configuration production method, a chip test configuration device, an electronic apparatus, a computer-readable storage medium, and a computer program product.

Background

A chip, also called microcircuit, microchip or integrated circuit, refers to a silicon chip containing an integrated circuit, has a small volume, and is an important component of electronic equipment such as computers. Because the chip structure is fine, the manufacturing process is complex, the flow is tedious, potential defects are inevitably left in the production process, the manufactured chip cannot meet the requirements, and faults can occur due to various reasons at any time.

Therefore, in order to ensure the quality of the chip, the packaged chip is usually tested, and whether the test coverage of the chip meets the requirement is determined according to the test result. However, the test scheme in the related art takes a long time, and the development cycle of the whole chip is prolonged.

Disclosure of Invention

The present application is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the application provides a chip test configuration generation method, a test method, a device and electronic equipment, so as to reduce the time required by chip test and shorten the chip development cycle.

An embodiment of a first aspect of the present application provides a method for generating a chip test configuration, where the chip includes: the chip comprises an interposer with a programmable interconnection network, at least one packaging pin connected with the programmable interconnection network and at least one core grain, wherein each core grain is provided with at least one core grain pin used for being connected with the programmable interconnection network; the method comprises the following steps: acquiring a configuration information set to be tested comprising at least one item of configuration information to be tested; and executing wiring processing on each item of configuration information to be tested in the configuration information set to be tested so as to generate a wiring configuration information set comprising at least one item of wiring configuration information, wherein each item of configuration information to be tested corresponds to one item of wiring configuration information.

An embodiment of a second aspect of the present application provides a testing method, including: acquiring a wiring configuration information set, wherein the wiring configuration information set is generated by a test configuration generation method based on the chip according to any one of the embodiments; configuring a programmable interconnect network of the chip based on the wiring configuration information set; test excitation is input to the chip through a packaging pin of the chip, and a test result is collected.

An embodiment of a third aspect of the present application provides a test configuration generating apparatus for a chip, where the chip includes: the chip comprises an interposer with a programmable interconnection network, at least one packaging pin connected with the programmable interconnection network and at least one core grain, wherein each core grain is provided with at least one core grain pin used for being connected with the programmable interconnection network; the device comprises: a first acquisition unit configured to acquire a configuration information set to be tested including at least one item of configuration information to be tested; and a wiring unit configured to perform wiring processing on each item of configuration information to be tested in the set of configuration information to be tested to generate a set of wiring configuration information including at least one item of wiring configuration information, wherein each item of configuration information to be tested corresponds to one item of wiring configuration information.

An embodiment of a fourth aspect of the present application provides a test apparatus, comprising: a second acquisition unit configured to acquire a wiring configuration information set based on the chip test configuration generation method according to any one of the embodiments; a configuration unit configured to configure a programmable interconnect network of the chip based on the set of wiring configuration information; the detection unit is configured to input test excitation to the chip through a packaging pin of the chip and collect output data of the chip generated aiming at the test excitation so as to generate a test result.

An embodiment of a fifth aspect of the present application provides an electronic device, including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the method as described in any of the embodiments above via execution of executable instructions.

Embodiments of a sixth aspect of the present application provide a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the method according to any one of the above embodiments.

An embodiment of a seventh aspect of the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the method according to any of the embodiments above.

The chip test configuration generation method, the test method, the device and the electronic equipment provided by the embodiment of the application are based on a chip with a programmable internet, the wiring configuration information set comprising at least one item of wiring configuration information can be automatically generated by acquiring the configuration information set to be tested comprising at least one item of configuration information to be tested and executing wiring processing on each item of configuration information to be tested in the configuration information set to be tested, and each item of configuration information to be tested corresponds to one item of wiring configuration information, so that the automatic design of a packaging interface can be quickly realized, and if RMA analysis after testing does not meet requirements, only the configuration information set to be tested needs to be revised again, and a new wiring configuration information set is automatically generated, so that the hardware change risk can be reduced, and the development period and the development cost can be reduced.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

FIG. 1 is a flow chart of a method for generating a chip test configuration according to an embodiment of the present application;

FIG. 2 is a block diagram of a test architecture according to one embodiment of the present application;

FIG. 3 is a flow diagram of a routing process according to one embodiment of the present application;

FIG. 4 is a data structure variation diagram of a chip test configuration generation method according to an embodiment of the present application;

FIG. 5 is a flow diagram of a routing process according to one embodiment of the present application;

FIG. 6 is a flow diagram of a routing process according to another embodiment of the present application;

FIG. 7 is a flow diagram of a testing method according to one embodiment of the present application;

FIG. 8 is a block diagram of a chip test configuration generation apparatus according to one embodiment of the present application;

FIG. 9 is a block diagram of a test setup according to one embodiment of the present application;

FIG. 10 is a block diagram of an electronic device according to one embodiment of the present application.

Description of reference numerals:

300: a chip; 310: core particles;

311: a core particle pin; 320: a programmable interconnect network;

321: a switch node; 330: an interposer;

340: an Internet controller; 350: a self-test module;

360: a power management module; 370: a storage module;

371：OTP； 372：NVRAM；

373: a RAM; 400: and testing the controller.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

For a conventional Multi-chip module (MCM) and a System In Package (SIP), tests of internal components need to be considered In Package design, and since test coverage after packaging has a significant influence on Reliability/maintainability analysis (RMA) of a final product, a test scheme design after packaging takes a relatively long time In the whole design cycle, and In addition, initial start-up and testing of basic functions of the System may take additional time. And, if the coverage of the test results fails to meet the requirements, further iterations of the design and manufacturing cycle may result.

The chip development cycle of the related art roughly includes the following processes: (1) carrying out core particle type selection; (2) Completing the design requirements of an Automatic Test (ATE) and a core particle Test (CORE) on the substrate; (3) designing a substrate and a test carrier plate; (4) Manufacturing a chip (manufacturing a substrate and packaging a chip and the substrate) and a test carrier plate; (5) testing; (6) RMA analysis. Each step in the steps (2) to (4) usually takes several weeks, and if the test coverage after the final RMA analysis cannot meet the requirement, the step (2) is returned to again complete the design requirements of the integrated circuit automatic test and the core grain test on the substrate, and then the steps (3) to (6) are performed again, the substrate needs to be redesigned and manufactured, so that the risk of hardware modification of the chip packaging interface and the test carrier plate is large, the whole development period is long, and the cost is high.

In order to solve at least one of the above problems, embodiments of the present application provide a method, a device, and an electronic device for generating a chip test configuration, where based on a chip with a programmable interconnect network, a configuration information set to be tested including at least one item of configuration information to be tested is obtained, and a wiring process is performed on each item of configuration information to be tested in the configuration information set to be tested, so that a wiring configuration information set can be automatically generated, thereby quickly implementing an automatic design of a package interface.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings. FIG. 1 is a flow chart of a method for generating a chip test configuration according to an embodiment of the present application; FIG. 2 is a block diagram of a test architecture according to one embodiment of the present application. Referring to fig. 1 and fig. 2, a chip test configuration generating method 100 is provided in the present embodiment for testing a chip 300.

The chip 300 includes: an interposer 330 having a programmable interconnect network 320, at least one package pin (not shown) connected to the programmable interconnect network 320, and at least one core die 310, each core die 310 being provided with at least one core die pin 311 for connection to the programmable interconnect network 320.

As shown in fig. 2, interposer 330 may be the substrate of chip 300, which may be made of a semiconductor material, such as silicon. The chip 300 may be provided with at least one core particle 310, the core particle 310 may be provided on an interposer 330, the core particle 310 may be a functional module in the chip 300, and the core particle 310 may be a circuit structure capable of providing functionality of processing function, storage function, sensing function, actuation function, reception function, transmission function, or a combination thereof. The number and type of core particles 310 may be selected as desired.

Each core grain 310 may have at least one core grain pin 311 thereon, for example, fig. 2 shows that the chip 300 includes a core grain 1, a core grain 2, a core grain 3 and a core grain 4, taking the core grain 1 as an example, it may have two core grain pins 311 of s1 and s2, the core grain 2 has three core grain pins 311 of r1 to r3, the core grain 3 has five core grain pins 311 of m1 to m5, and the core grain 4 has six core grain pins 311 of p1 to p 6.

The interposer 330 may also be provided with a programmable interconnect network 320, and the programmable interconnect network 320 may be programmably configured in the field at the time of manufacture or during runtime. It will be appreciated that programmable interconnect network 320 may include a plurality of vias that can be programmed to be switched on and off to achieve different wiring configurations. In some embodiments, the programmable interconnect network 320 in fig. 2 may be implemented using a programmable crossbar switch, the crossbar switch may include a plurality of switch nodes 321, each of the core particles 310 may be connected to a switch contact 321 of the programmable control network 320 through a core particle pin 311, and the interconnection between the core particles 310 and the connection of the core particles 310 to other external interfaces may be implemented by configuring the programmable interconnect network 320, such as by turning on or off the switch nodes 321.

In addition, the chip 300 may further have an internet controller 340, the internet controller 340 may be a common structure capable of implementing a control function, and the programmable internet 320 may be configured by the internet controller 340, for example, to control on/off states of the switch nodes 321.

Package pins may be provided on interposer 330, which may be connected to programmable interconnect network 320 to connect packaged chip 300 to external components or signals. The number of package pins may be one or more. It is understood that the programmable interconnect network 320 has a plurality of pads exposed to the interposer 330, and package pins may be disposed on at least some of the pads, i.e., the number of package pins may be less than or equal to the number of pads, and each package pin may be connected to one pad.

In some embodiments, chip 300 also has a self-test module 350 and a power management module 360, self-test module 350 can be used to implement self-testing of chip 300, and power management module 360 can be used to provide power and efficiently distribute power to the different components of chip 300.

Taking the test architecture shown in fig. 2 as an example, the chip test configuration generating method 100 includes the following steps S110 and S120.

Step S110, obtaining a to-be-tested configuration information set including at least one item of to-be-tested configuration information.

Step S120, performing a routing process on each item of configuration information to be tested in the configuration information set to be tested to generate a routing configuration information set including at least one item of routing configuration information, where each item of configuration information to be tested corresponds to one item of routing configuration information. The configuration information set to be tested may be a test requirement set, which may include one or more pieces of configuration information to be tested, and each piece of configuration information to be tested may be one test requirement in the test requirement set, for example, the connection between the core grain 1 and the core grain 2, or the connection between the core grain 1 and an external interface, and so on. The set of configuration information to be tested may be set according to the user's requirements for the functions of the chip 300.

In step S120, each item of configuration information to be tested in the configuration information set to be tested may be subjected to a wiring process, so as to obtain a wiring configuration information set of the programmable interconnect network 320. Generally, each item of configuration information to be tested can generate a piece of wiring configuration information corresponding to the item of configuration information to be tested, and at least one item of wiring configuration information generated by the set of configuration information to be tested is collected to form a set of wiring configuration information.

It is understood that based on the method 100, the testing process of the chip 300 can be changed to the following process: (1) carrying out core particle type selection; (2) Obtaining a chip test configuration (wiring configuration information set) that meets design requirements by the method 100; (3) testing the design of a carrier plate; (4) mounting the core particle 310 to the interposer 330; (5) Writing the chip test configuration into the chip 300 and testing; (6) RMA analysis.

In the method 100, the wiring process is performed on each item of configuration information to be tested in the configuration information set to be tested, so that the wiring configuration information set meeting the design requirement can be automatically generated, and therefore, the process only takes about 1 day, which greatly reduces the time required for completing the process of the design requirement of the integrated circuit automatic test and the core grain test on the substrate in the related art. Moreover, because the chip 300 with the programmable interconnect network 320 is adopted, the design of the chip 300 is more dependent on programming, and the interposer 330 can adopt a general-purpose module without performing unique substrate design and manufacturing for the selected core particles as in the related art, so that the installation of the core particles 310 to the interposer 330 only needs several days, further reducing the time and cost consumed by the test process, and reducing the development period.

In addition, if the test coverage of the chip does not meet the requirement after RMA analysis, the chip test configuration (wiring configuration information set) may be updated by generating a new test requirement, and then written into the chip 300 for retesting, which is a manner that, compared with the test flow in the related art, when the test coverage does not meet the requirement, the manufacturing substrate does not need to be redesigned, which may reduce hardware changes of the chip 300 and the test carrier board, and further reduce the iteration cycle and cost of the chip 300.

FIG. 3 is a flow diagram of a routing process according to one embodiment of the present application; referring to fig. 3, in some embodiments, as shown in fig. 3, the wiring process includes the following steps S121 to S124.

Step S121, a core particle set in each item of configuration information to be tested and a core particle pin set corresponding to each core particle in the core particle set are obtained.

Step S122, configuring the state of the core particles and the core particle pins not involved in the core particle set and the core particle pin set corresponding to the configuration information to be tested into an off state.

Step S123, searching for the routing configuration information corresponding to the item of configuration information to be tested in the programmable internet, where the routing configuration information can connect the core pins in the core pin set corresponding to the item of configuration information to be tested to the package pins in the package pin set, and the package pin set is a set of package pins that can be used for testing.

Step S124, in response to the searched wiring configuration information, determining that the item of configuration information to be tested is configured successfully, and adding the wiring configuration information corresponding to the item of configuration information to be tested to the wiring configuration information set.

Specifically, step S121 in the routing process may acquire a core grain set and a core grain pin set of one item of configuration information to be tested currently executing the routing process. It is to be understood that the configuration information to be tested may include a core grain set and a core grain pin set related to the test requirement, for convenience of description, the core grain set of the configuration information to be tested includes a core grain 1 and a core grain 2 as an example, and the configuration information to be tested may further include a pin set { s1, s2} corresponding to the core grain 1 and a pin set { r1, r2, r3} corresponding to the core grain 2. Of course, the pin set of the core particle 1 may include only s1 or s2, and the pin set of the core particle 2 may include at least one of r1, r2, and r3, which may be specifically set according to the test requirement.

In step S122, the states of the core grains 310 and the core grain pins 311 that are not involved in the item of configuration information to be tested may be configured as an off state. If the core particle pin set included in the configuration information to be tested is the pin set { s1, s2} corresponding to the core particle 1 and the pin set { r1, r2, r3} corresponding to the core particle 2, the other core particles 310 (the core particles 3 and 4) except the core particles 1 and 2 may be set to the off state. If the core pin set included in the configuration information to be tested is { s1} or { r1}, the switch nodes 321 corresponding to the core pins s2, r2, and r3 need to be configured to be in the off state in addition to the states of the core 3 and the core 4.

In step S123, it is necessary to search the programmable internet 320 for the routing configuration information corresponding to the item of configuration information to be tested, where the routing configuration information can connect the core die pin in the core die pin set corresponding to the item of configuration information to be tested to the package pin in the package pin set. Where the package pins may include package pins that can be used for testing, it is understood that chip 300 may have one or more package pins, at least some of which may be used for testing. For example, chip 300 includes 5 package pins, a1 to a5 respectively, where the package pins of a4 and a5 can be used for testing, and then the package pin set may include two package pins 310 of { a4, a5 }.

Taking the core grain pin set included in the configuration information to be tested as the pin set { S1, S2} corresponding to the core grain 1 and the pin set { r1, r2, r3} corresponding to the core grain 2 as an example, step S123 may search for the wiring configuration information in which { S1, S2} and { r1, r2, r3} are connected to { a4, a5}, it can be understood that the wiring configuration information may include one or more paths, which may be set by a test requirement, and is not limited herein.

The method for searching the routing configuration information in the programmable internet 320 may be a common path algorithm, and the like, and may include, for example, a conventional algorithm (Dijkstra algorithm, a star algorithm, and the like), an intelligent algorithm (PSO algorithm, genetic algorithm, reinforcement learning, and the like), or a conventional algorithm combined with intelligence.

In step S124, if the routing configuration information is searched, it may be determined that the configuration of the item of configuration information to be tested is successful, and meanwhile, the routing configuration information corresponding to the item of configuration information to be tested may be stored in the routing configuration information set.

Through steps S121 to S124, a wiring configuration information set meeting the design requirements can be automatically generated, automatic design of a package interface can be realized, and development cycle and cost are reduced.

It is to be understood that in some other embodiments, the routing process may generate all connection routes from each core die in the core die set to each core die pin in the core die pin set by permutation and combination, and generate the routing configuration information by testing whether each connection route is successfully connected, thereby generating the routing configuration information set.

FIG. 4 is a data structure variation diagram of a chip test configuration generation method according to an embodiment of the present application; referring to fig. 4, the left side is a configuration information set to be tested based on the test requirement set, and Cfgnum M represents the number of items of configuration information to be tested in the configuration information set to be tested is M. Test _ cfg _0 represents the 0 th item of configuration information to be tested in the configuration information set to be tested, chiplet _ id0 represents the kernel 310 with id number 0, bump [ ] below chiplet _id0represents the kernel pin set of the kernel 310, and chiplet _ id0, chiplet _ id1, … … and chiplet _ idx can form the kernel set. Similarly, the Test _ cfg _1 may be the 1 st configuration information to be tested, and the like. The initial ball [ ] identifies the package pin set.

The right side of fig. 4 is a data structure of data subjected to wiring processing, the data stores, in addition to each item of configuration information to be tested, also stores, for each item of configuration information to be tested, fabric _ config [ ] and testbump2ball _ map [ ], the fabric _ config [ ] represents wiring configuration information generated by the item of configuration information to be tested, and the testbump2ball _ map [ ] is a set of package pins used by the item of configuration information to be tested. The final ball [ ] represents the final routed package pin set, and it can be understood that the initial ball [ ] and the final ball [ ] may be different because the package pin set may be changed during the routing process, which will be explained in the following embodiments.

FIG. 5 is a flow diagram of a routing process according to one embodiment of the present application; referring to fig. 4 and 5, in an embodiment, a configuration information set to be tested, a number of items Cfgnum of the configuration information to be tested in the configuration information set to be tested, and an initial package pin set ball [ ] may be obtained first. In addition, in order to subject each item of configuration information to be measured to wiring processing, a variable i may be set, and initial i may be 0.

And then judging whether i is smaller than Cfgnum, if not, indicating that each item in the configuration information set to be tested is subjected to wiring treatment, and ending the process. If yes, the relevant information in the ith item of configuration information to be tested is acquired, including the core particle set chip [ ] of the core particles 310 involved in the item of test and the core particle pin sets bump [ ] involved in the core particles 310.

The state of the core die 310 and the core die pins 311, which are not related to the configuration information to be tested, may then be set to an off state.

Then, the programmable interconnect network 320 searches for wiring configuration information that can communicate the bump [ ] to the ball [ ], and if the wiring configuration information is searched, the wiring is successful, and the wiring configuration information is stored in the wiring configuration information set.

And adding 1 to the numerical value of the variable i, then jumping to the step of judging whether i is smaller than Cfgnum, and continuing to perform wiring processing on the next configuration information to be tested.

Fig. 6 is a flowchart of a routing process according to another embodiment of the present application, and referring to fig. 6, in some embodiments, the routing process may further include a step S125, determining that the configuration information to be tested fails to be configured in response to that no routing configuration information is searched and package pins are connected to all pads in the programmable interconnect network.

It is understood that package pins may be connected to pads of programmable interconnect network 320. One pad may correspond to each package pin.

Referring to fig. 5, if the wiring is unsuccessful, that is, the wiring configuration information is not searched, it may be determined whether all pads in the programmable interconnect network 320 are connected to package pins, and if so, all pads are already provided with package pins, it may be determined that the configuration of the configuration information to be tested fails, that is, the test requirement cannot be met. Therefore, whether the design requirements can be met or not can be detected in advance before hardware manufacturing through the chip test configuration generation method of the embodiment, and therefore the risk of later-stage modification is reduced.

With continued reference to fig. 6, in some embodiments, the routing process may further include step S126, in response to that no routing configuration information is searched and there is a free pad in the programmable interconnect network 320 to which a package pin is not connected, setting a new package pin for the free pad; and adding a new packaging pin to the packaging pin set, and returning to execute the step of searching the programmable internet 320 for the wiring configuration information corresponding to the item of configuration information to be tested.

The spare pad may be a pad of the programmable interconnect network 320 that is not configured with a package pin. It can be understood that, for the chip 300, during packaging, a package pin is not set for each pad in the programmable interconnect network 320, and only a certain number of package pins are set under the condition of ensuring the basic configuration, so that the number of package pins is small, and the simplicity of the chip 300 can be ensured. During testing, a package pin set which can be used for testing in the package pins can be added, if wiring configuration information is not searched, whether an idle bonding pad exists or not can be judged, if the wiring configuration information exists, an idle bonding pad can be added to the package pin set, and then the step S123 is executed again until the configuration of the configuration information to be tested is determined to be successful or failed, so that the package pins can be added according to requirements, and the simplicity of the chip 300 is ensured.

As shown in fig. 5, if the wiring is unsuccessful, it may be determined whether all pads in the programmable interconnect network 320 are connected with package pins, and if not, a new package pin may be set for an idle pad not connected with a package pin, the new package pin is added to ball [ ], and then a step of searching for wiring configuration information capable of communicating bump [ ] to ball [ ] in the programmable interconnect network 320 is skipped until the wiring is successful or it is determined that the configuration of the configuration information to be tested fails.

In addition, since the chip test configuration generation method of the embodiment is performed in the design stage before packaging, repeated modification of hardware during packaging pin installation can be reduced.

In some embodiments, programmable interconnect network 320 has switch node 321 connected to chip pin 311; step S122 configures the states of the core particles and the core particle pins not involved in the core particle set and the core particle pin set corresponding to the configuration information to be tested into an off state, which may include: configuring the power-on state of the core particles 310 not involved in the core particle set corresponding to the configuration information to be tested into a power-off state; and/or configuring the switch node 321 connected to the core grain pin 311 which is not involved in the core grain pin set corresponding to the configuration information to be tested to be in an off state.

It can be understood that, if the core particle set of the item of configuration information to be tested includes the core particle 1 and the core particle 2, and the core particle pin sets are the pin set { S1, S2} corresponding to the core particle 1 and the pin set { r1, r2, r3} corresponding to the core particle 2, step S122 may set the other core particles 310 (the core particle 3 and the core particle 4) except the core particle 1 and the core particle 2 to the off state, that is, the power supply of the core particle 3 and the core particle 4 is cut off, so that the core particles are in the non-power supply state. Alternatively, the switching nodes 321 to which the core pin (m 1 to m 5) of the core 3 and the core pin (p 1 to p 6) of the core 4 are connected may be in an open state, that is, the lines connected to the core pins 311 are in an open state. Alternatively, core grain 3 and core grain 4 are in a non-power supply state, and switch node 321 corresponding to the core grain pins of both are in an off state.

If the pin sets of the core particles included in the configuration information to be tested are { s1} and { r1}, the power supply of the core particles 3 and 4 can be cut off at this time, so that the core particles are in a non-power supply state. Meanwhile, the switch nodes 321 corresponding to the core die pins s2, r2, and r3 may be configured to be in an off state. Alternatively, the switching node 321 corresponding to the core particle pins s2, r2, and r3 is configured to be in the off state, while the core particle pins m1 to m5 and p1 to p6 corresponding to the core particles 3 and 4 are configured to be in the off state.

In one embodiment, cutting off power to the core pellet may be accomplished through the power management door module 360.

The method can configure other core particles and core particle pins except the configuration information to be tested into a disconnected state, thereby reducing the searching difficulty of subsequent wiring configuration information and improving the efficiency.

In some embodiments, after performing routing processing on each item of configuration information to be tested in the set of configuration information to be tested in step S120 to generate a set of routing configuration information including at least one item of routing configuration information, the method 100 further includes: and in response to the existence of the to-be-tested configuration information which is not configured successfully, updating the to-be-tested configuration information set, and returning to the step of executing the wiring processing on each item of to-be-tested configuration information in the to-be-tested configuration information set until all the to-be-tested configuration information in the updated to-be-tested configuration information set is configured successfully.

It can be understood that, if any one or several items of wiring configuration information cannot be searched in the generation process of the wiring configuration information, it is considered that one or several items of test requirement configuration fails, the configuration information set to be tested may be updated, and the configuration information set to be tested may include one or several items of new configuration information to be tested for the failed test requirement, and then the step S120 is returned to be executed, and the wiring configuration information set corresponding to the new configuration information set to be tested is searched again until all the configuration information to be tested in the new configuration information set to be tested is successfully configured, so that the shortage of the test requirement may be made up, and the wiring configuration information set meeting the new test requirement may be automatically generated.

It is understood that the wiring configuration information set may include the wiring configuration information generated in the previous step S120 and the wiring configuration information generated in the step S120 after the current modification of the configuration information set to be tested.

Of course, in some embodiments, the test requirement may be redesigned, and the new test configuration information set may cover the previous successful test requirement and the previous failed test requirement, that is, the wiring configuration information set generated in the previous step S120 is abandoned, and a new wiring configuration information set is regenerated.

Fig. 7 is a flowchart of a testing method according to an embodiment of the present application, please refer to fig. 7, and the embodiment of the present application further provides a testing method 200, where the method 200 includes the following steps S210 to S230.

Step S210, obtaining a wiring configuration information set, where the wiring configuration information set is generated based on any one of the chip test configuration generation methods 200.

In step S220, the programmable interconnect network 320 of the chip 300 is configured based on the set of wiring configuration information.

Step S230, inputting a test stimulus to the chip through a package pin of the chip, and collecting a test result.

Referring to fig. 2, in some embodiments, a test controller 400 is further disposed in the test framework, and the test controller 400 may be mounted in the chip 300, but it may also be disposed in a test carrier, or in other devices such as a computer, and the test controller 400 may be used to test the chip 300. In this embodiment, the test controller 400 may be relied upon to obtain a wiring configuration information set, which may be generated based on any of the chip test configuration generation methods 200 described above.

In some embodiments, the step 210 of obtaining the set of routing configuration information may include: the wiring configuration information set is acquired through the external configuration interface A1. For example, the external configuration interface A1 may be a joint test task group (JTAG) interface or a Serial Debug (SWD) interface, or the like. It is understood that the wiring configuration information set may be generated by other external devices such as a computer, and the test controller 400 may have an external configuration interface A1, and may be connected to the external devices through the external configuration interface A1, so that the wiring configuration information set may be obtained from the outside.

In other embodiments, the set of wiring configuration information may also be generated by the test controller 400.

With continued reference to fig. 7, in some embodiments, chip 300 further includes: the storage module 370, the storage module 370 includes at least One of a One Time Programmable (OTP) Memory 371, a Non-volatile Random Access Memory (NVRAM) 372, and a Random Access Memory (RAM) 373. The storage module 370 may be disposed on the interposer 330, and the storage module 370 may also be connected with the test controller 400. The wiring configuration information may be stored in the storage module 370, for example, in the OTP 371, or in the NVRAM 372, or in the RAM 373, or in any two or three of these. Step S210 of acquiring a set of wiring configuration information may include: the set of wiring configuration information is retrieved from the storage module 370.

The above various manners may all achieve the acquisition of the wiring configuration information set, and specifically, one or more of the manners may be selected according to actual situations.

Step S220 may configure the set of wiring configuration information into the programmable interconnect network 320 of the chip 300.

In some embodiments, test controller 400 may be coupled to interconnect network controller 340. Step S220 configures the programmable interconnect network of the chip based on the wiring configuration information set, which may include: the wiring configuration information set is configured into the interconnect network controller 340 of the chip 300, and the interconnect network controller 340 is used for configuring the programmable interconnect network 320 of the chip. The wiring configuration information is configured into the internet controller 340 through the test controller 400, so that the configuration of the programmable internet 320 is realized, that is, the test configuration is written into the chip 300, so that the test controller 400 and the internet controller 340 can respectively execute different functions, and the configuration efficiency is improved.

In step S230, the test controller 400 may further input a test stimulus to the chip 300 through the package pin, where the test stimulus may be selected according to a test mode, and the test mode may include Scan (Scan) or built-in self test (Bist). By inputting a test stimulus to chip 300, a feedback output signal of chip 300 to the test stimulus may be received, which may be collected as a test result.

After the test results are collected, RMA analysis can be carried out on the design results, so that whether the test coverage rate meets the requirement or not is judged.

By the testing method provided by the embodiment, since the wiring configuration information set generated by the chip testing configuration generating method 100 is used to configure the programmable interconnect network 320 of the chip 300, hardware changes of the chip 300 and the test carrier board can be reduced, and the design and iteration cycle and cost of the chip 300 are further reduced.

In some embodiments, the method 200 may further include: and in response to the test coverage of the test result not meeting the target test coverage, updating the wiring configuration information set based on the new configuration information set to be tested, and returning to the step of executing the programmable interconnection network for configuring the chip based on the wiring configuration information set until the test coverage of the test result meets the target test coverage.

Wherein the test coverage represents a measure of the completion of the test. The execution condition of the test case is usually measured according to a preset coverage criterion to judge whether the test is executed sufficiently. If the test coverage cannot meet the requirements after performing RMA analysis on the test results, the test engineer may change the test requirements to determine a new configuration set of information to be tested corresponding to the new test requirements, where the new configuration set of information to be tested may include one or more items of new configuration information to be tested for the test requirements that cannot be met, or may be a newly designed configuration set of information to be tested that can cover all the test requirements.

By acquiring the new configuration information set to be tested and then updating the wiring configuration information set based on the new configuration information set to be tested, the method for updating the wiring configuration information set may refer to the chip test configuration generation method in the above embodiment, which is not described herein again. Then, steps S220 and S230 may be executed again until the test coverage of the test result satisfies the target test coverage.

In this embodiment, if the test coverage of the chip does not meet the requirement after RMA analysis, the chip test configuration (wiring configuration information set) may be updated by generating a new test requirement, and then written into the chip 300 for retesting, which is a manner that, compared to the test flow in the related art, when the test coverage does not meet the requirement, the manufacturing substrate does not need to be redesigned, which may reduce hardware changes of the chip 300 and the test carrier, and further reduce the iteration cycle and cost of the chip 300.

In some embodiments, the step S220 of configuring the programmable interconnect network of the chip based on the wiring configuration information set includes: acquiring working modes of the chip 300, wherein the working modes comprise a normal working mode and a test mode; responding to the working mode as a test mode, and configuring the programmable interconnection network of the chip based on the wiring configuration information set; in response to the operating mode being a normal operating mode, the chip 300 is switched to a test mode and the programmable interconnect network of the chip is configured based on the set of wiring configuration information.

Referring to fig. 2, the test control board 400 may further have a working mode control interface A2, where the working mode control interface A2 may be used to control whether the current chip 300 is in a normal working mode or a test mode, if in the test mode, the wiring configuration information set may be configured to the programmable internet 320 of the chip 300, and if in the normal working mode, the chip 300 may be first switched to the test mode, and then the wiring configuration information set may be configured to the programmable internet 320 of the chip 300. The working mode control interface A2 may be dedicated IO control, or may be an interface configured by I2C/SPI or the like. In addition, the operating mode control interface A2 may also be used to select a subclass of test modes, thereby inputting different test stimuli to the chip 300.

By judging the working mode of the chip 300 and performing subsequent tests according to the working mode, the normal working mode and the test mode can be distinguished, so that the normal work and the test of the chip 300 are not influenced mutually, and the test reliability is improved.

In some embodiments, the testing method may further comprise: acquiring the acquisition state of the test result; and outputting indication information corresponding to the acquisition state.

With continued reference to fig. 2, the test control board 400 may further have a status indication interface A3, for example, the status indication interface A3 may output different indication signals according to the collection status of the test result, such as collection in progress or collection completed, etc.

The indication information can be any one or more of various information such as characters, signals, sounds and the like, and the test engineer can conveniently and quickly know the test state, the test result and the like through the indication information.

It is understood that the test controller 400 is used as an example to describe the test method 200, and in other embodiments, the test method 200 may be performed by other devices.

FIG. 8 is a block diagram of a chip test configuration generation apparatus according to one embodiment of the present application; referring to fig. 8, an embodiment of the present application provides a chip test configuration generating apparatus 500, where the chip includes: the chip comprises an interposer with a programmable interconnection network, at least one packaging pin connected with the programmable interconnection network and at least one core grain, wherein each core grain is provided with at least one core grain pin used for being connected with the programmable interconnection network; the apparatus 500 includes the following elements.

A first obtaining unit 501 configured to obtain a set of configuration information to be tested including at least one piece of configuration information to be tested.

The routing unit 502 is configured to perform routing processing on each item of configuration information to be tested in the set of configuration information to be tested to generate a set of routing configuration information including at least one item of routing configuration information, wherein each item of configuration information to be tested corresponds to one item of routing configuration information.

In some embodiments, the routing unit 502, when performing routing processing, is further configured to: acquiring a core grain set in each item of configuration information to be tested and a core grain pin set corresponding to each core grain in the core grain set; configuring the states of the core particles and the core particle pins which are not involved in the core particle set and the core particle pin set corresponding to the configuration information to be tested into an off state; searching the wiring configuration information corresponding to the configuration information to be tested in the programmable internet, wherein the wiring configuration information can connect the core grain pins in the core grain pin set corresponding to the configuration information to be tested to the packaging pins in the packaging pin set, and the packaging pin set is a set of packaging pins which can be used for testing; and responding to the searched wiring configuration information, determining that the item of configuration information to be tested is successfully configured, and adding the wiring configuration information corresponding to the item of configuration information to be tested to the wiring configuration information set.

In some embodiments, the routing unit 502, when performing routing processing, is further configured to determine that the configuration information to be tested fails to be configured in response to no routing configuration information being searched and package pins being connected to all pads in the programmable interconnect network.

In some embodiments, the routing unit 502, when performing routing processing, is further configured to set a new package pin for a free pad in response to no routing configuration information being searched and a free pad with no package pin connected exists in the programmable interconnect network; and adding a new packaging pin to the packaging pin set, and returning to execute the step of searching the routing configuration information corresponding to the item of configuration information to be tested in the programmable internet.

In some embodiments, the programmable interconnect network has a switch node connected to a chip pin; the wiring unit 502 is further configured to configure the power-on state of the core particles not involved in the core particle set corresponding to the item of configuration information to be tested to be an off state when performing the configuration to configure the states of the core particles and the core particle pins not involved in the core particle set and the core particle pin set corresponding to the item of configuration information to be tested to be an off state; and/or configuring a switch node connected with a core grain pin which is not involved in the core grain pin set corresponding to the configuration information to be tested into a disconnected state.

In some embodiments, after performing the routing processing on each piece of configuration information to be tested in the set of configuration information to be tested to generate the set of routing configuration information including at least one piece of routing configuration information, the routing unit 502 is further configured to, in response to the existence of the configuration information to be tested that is not successfully configured, re-acquire the set of configuration information to be tested, and return to the step of performing the routing processing on each piece of configuration information to be tested in the set of configuration information to be tested until all the configuration information to be tested in the updated set of configuration information to be tested is successfully configured.

The working principle and function of the chip test configuration generating apparatus in this embodiment are the same as those of the chip test configuration generating method in the above embodiments, and reference may be made to the above embodiments specifically, and details are not repeated here.

FIG. 9 is a block diagram of a test setup according to one embodiment of the present application; referring to fig. 9, an embodiment of the present application further provides a testing apparatus 600, which includes the following units.

A second obtaining unit 601 configured to obtain a wiring configuration information set based on the chip test configuration generation method of any one of the above embodiments.

A configuration unit 602 configured to configure the programmable interconnect network of the chip based on the set of wiring configuration information.

The detection unit 603 is configured to input a test stimulus to the chip through a package pin of the chip, and collect output data of the chip generated for the test stimulus to generate a test result.

In some embodiments, the test device 600 further comprises: and the third acquisition unit is configured to respond to the test coverage of the test result not meeting the target test coverage, update the wiring configuration information set based on the new information configuration set to be tested, and return to the step of executing the programmable interconnection network for configuring the chip based on the wiring configuration information set until the test coverage of the test result meets the target test coverage.

In some embodiments, the configuration unit 602, when executing the programmable interconnect network configuring the chip based on the wiring configuration information set, is further configured to obtain an operation mode of the chip, where the operation mode includes a normal operation mode and a test mode; responding to the working mode as a test mode, and configuring the programmable interconnection network of the chip based on the wiring configuration information set; and responding to the normal working mode of the working mode, switching the chip to a test mode, and configuring the programmable interconnection network of the chip based on the wiring configuration information set.

In some embodiments, the configuration unit 602, when executing configuring the programmable interconnect network of the chip based on the set of routing configuration information, is further configured to: and configuring the wiring configuration information set into an interconnection network controller of the chip, wherein the interconnection network controller is used for configuring the programmable interconnection network of the chip.

In some embodiments, the chip further comprises: a storage module including at least one of a one-time programmable memory, a non-volatile memory, and a random access memory; the second obtaining unit 601, when performing obtaining the wiring configuration information set, is further configured to obtain the wiring configuration information set from the storage module.

In some embodiments, the second obtaining unit 601, when performing obtaining the wiring configuration information set, is further configured to obtain the wiring configuration information set through an external configuration interface.

The working principle and function of the testing apparatus in this embodiment are the same as those of the testing method in the above embodiments, and reference may be made to the above embodiments specifically, and no further description is given here.

An embodiment of the present application further provides an electronic device including: a processor and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the chip test configuration generation method or the test method of any of the above embodiments via execution of the executable instructions.

Embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored, and when executed by a processor, the computer program implements executing executable instructions to execute the chip test configuration generating method or the chip test configuration testing method according to any one of the above embodiments.

Embodiments of the present application also provide a computer program product comprising a computer program that, when executed by a processor, implements executable instructions to perform a chip test configuration generation method or a test method as in any of the above embodiments.

Fig. 10 is a block diagram of an electronic device according to an embodiment of the present application, and referring to fig. 10, a block diagram of an electronic device 700 that may be a server or a client of the present application, which is an example of a hardware device that may be applied to aspects of the present application, will now be described. Electronic device is intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.

As shown in fig. 10, the device 700 comprises a computing unit 701, which may perform various suitable actions and processes according to a computer program stored in a read only memory (ROM 702) or a computer program loaded from a storage unit 708 into a second random access memory (second RAM 703). In the second RAM 703, various programs and data required for the operation of the device 700 can also be stored. The calculation unit 701, the ROM 702, and the second RAM 703 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

A number of components in the device 700 are connected to the I/O interface 705, including:an input unit 706, an output unit 707, a storage unit 708, and a communication unit 709. The input unit 706 may be any type of device capable of inputting information to the device 700, and the input unit 706 may receive input numeric or character information and generate key signal inputs related to user settings and/or function controls of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and/or a remote controller. Output unit 707 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, a video/audio output terminal, a vibrator, and/or a printer. Storage unit 708 may include, but is not limited to, magnetic or optical disks. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and/or a chipset, such as bluetooth ^TM Devices, 1302.11 devices, wiFi devices, wiMax devices, cellular communication devices, and/or the like.

Computing unit 701 may be a variety of general purpose and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The calculation unit 701 executes the respective methods and processes described above, such as the chip test configuration generation method or the test method. For example, in some embodiments, the chip test configuration method or test method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of a computer program may be loaded onto and/or installed onto device 700 via ROM 702 and/or communications unit 709. When the computer program is loaded into the second RAM 703 and executed by the computing unit 701, one or more steps of the chip test configuration generation method or the test method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the chip test configuration method or the test method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present application may be executed in parallel, or may be executed sequentially or in different orders, as long as the desired results of the technical solutions disclosed in the present application can be achieved, and the present invention is not limited thereto.

Although embodiments or examples of the present application have been described with reference to the accompanying drawings, it is to be understood that the above-described methods, systems and apparatus are merely illustrative embodiments or examples and that the scope of the invention is not to be limited by these embodiments or examples, but only by the claims as issued and their equivalents. Various elements in the embodiments or examples may be omitted or may be replaced with equivalents thereof. Further, the steps may be performed in an order different from that described in the present application. Further, various elements in the embodiments or examples may be combined in various ways. It is important that as technology evolves, many of the elements described herein may be replaced by equivalent elements that appear after the application.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are exemplary and should not be construed as limiting the present application and that changes, modifications, substitutions and alterations in the above embodiments may be made by those of ordinary skill in the art within the scope of the present application.

Claims

1. A chip test configuration generation method is characterized in that a chip comprises: the chip comprises an interposer with a programmable interconnection network, at least one packaging pin connected with the programmable interconnection network and at least one core grain, wherein each core grain is provided with at least one core grain pin used for being connected with the programmable interconnection network; the method comprises the following steps:

acquiring a configuration information set to be tested comprising at least one item of configuration information to be tested; and

and executing wiring processing on each item of the configuration information to be tested in the configuration information set to be tested so as to generate a wiring configuration information set comprising at least one item of wiring configuration information, wherein each item of the configuration information to be tested corresponds to one item of the wiring configuration information.

2. The method of claim 1, wherein the routing process comprises:

acquiring a core grain set in each item of configuration information to be tested and a core grain pin set corresponding to each core grain in the core grain set;

configuring the states of the core grains and the core grain pins which are not related in the core grain set and the core grain pin set corresponding to the configuration information to be tested into an off state;

searching the programmable internet for the wiring configuration information corresponding to the configuration information to be tested, wherein the wiring configuration information can connect the core grain pins in the core grain pin set corresponding to the configuration information to be tested to the package pins in the package pin set, and the package pin set is the set of the package pins which can be used for testing; and

and responding to the searched wiring configuration information, determining that the item of the configuration information to be tested is successfully configured, and adding the wiring configuration information corresponding to the item of the configuration information to be tested to the wiring configuration information set.

3. The method of claim 2, wherein the routing process further comprises:

and determining that the configuration of the configuration information to be tested fails in response to the situation that the wiring configuration information is not searched and all the pads in the programmable internet are connected with the packaging pins.

4. The method of claim 2, wherein the routing process further comprises:

in response to the wiring configuration information is not searched and an idle pad which is not connected with the packaging pin exists in the programmable internet, setting a new packaging pin for the idle pad;

and adding the new packaging pin to the packaging pin set, and returning to execute the step of searching the wiring configuration information corresponding to the item of the configuration information to be tested in the programmable internet.

5. The method of any of claims 2-4, wherein the programmable interconnect network has a switch node connected to the chip pin;

configuring the state of the core grain and the core grain pins which are not involved in the core grain set and the core grain pin set corresponding to the configuration information to be tested into a disconnected state, including:

configuring the power-on state of the core particles which are not involved in the core particle set and correspond to the configuration information to be tested into the disconnection state; and/or the presence of a gas in the gas,

configuring the switch node connected with the core grain pin not involved in the core grain pin set corresponding to the configuration information to be tested to be in the disconnection state.

6. The method according to any one of claims 2-4, wherein after performing routing processing on each of the set of configuration information to be tested to generate a set of routing configuration information including at least one item of routing configuration information, the method further comprises:

responding to the to-be-tested configuration information which is not configured successfully, updating the to-be-tested configuration information set, and returning to execute the step of executing wiring processing on each item of to-be-tested configuration information in the to-be-tested configuration information set until all the to-be-tested configuration information in the updated to-be-tested configuration information set is configured successfully.

7. A method of testing, comprising:

acquiring a wiring configuration information set generated based on the chip test configuration generation method of any one of claims 1 to 6;

configuring a programmable interconnect network of the chip based on the set of wiring configuration information;

and inputting test excitation to the chip through a packaging pin of the chip, and collecting a test result.

8. The method of claim 7, further comprising:

and in response to the test coverage of the test result not meeting the target test coverage, updating the wiring configuration information set based on the new information configuration set to be tested, and returning to execute the step of configuring the programmable interconnection network of the chip based on the wiring configuration information set until the test coverage of the test result meets the target test coverage.

9. The method of claim 7, wherein configuring the programmable interconnect network of the chip based on the set of wiring configuration information comprises:

acquiring a working mode of the chip, wherein the working mode comprises a normal working mode and a test mode;

responding to the working mode as a test mode, and configuring the programmable interconnection network of the chip based on the wiring configuration information set;

and responding to the working mode as a normal working mode, switching the chip to the test mode, and configuring the programmable interconnection network of the chip based on the wiring configuration information set.

10. The method of claim 7, wherein configuring the programmable interconnect network of the chip based on the set of wiring configuration information comprises:

and configuring the wiring configuration information set into an interconnection network controller of the chip, wherein the interconnection network controller is used for configuring a programmable interconnection network of the chip.

11. The method of any of claims 7-10, wherein the chip further comprises: a storage module including at least one of a one-time programmable memory, a non-volatile memory, and a random access memory;

the acquiring of the wiring configuration information set comprises: and acquiring the wiring configuration information set from the storage module.

12. The method according to any of claims 7-10, wherein the obtaining the wiring configuration information set comprises: and acquiring the wiring configuration information set through an external configuration interface.

13. A chip test configuration generation apparatus, the chip comprising: the chip comprises an interposer with a programmable interconnection network, at least one packaging pin connected with the programmable interconnection network and at least one core grain, wherein each core grain is provided with at least one core grain pin used for being connected with the programmable interconnection network; the device comprises:

a first acquisition unit configured to acquire a configuration information set to be tested including at least one item of configuration information to be tested; and

the wiring unit is configured to perform wiring processing on each item of the configuration information to be tested in the configuration information set to be tested so as to generate a wiring configuration information set comprising at least one item of wiring configuration information, wherein each item of the configuration information to be tested corresponds to one item of the wiring configuration information.

14. A test apparatus, comprising:

a second acquisition unit configured to acquire a wiring configuration information set based on the chip test configuration generation method of any one of claims 1 to 6;

a configuration unit configured to configure a programmable interconnect network of the chip based on the set of wiring configuration information;

the detection unit is configured to input test excitation to the chip through a packaging pin of the chip and collect output data of the chip generated aiming at the test excitation so as to generate a test result.

15. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the method of any of claims 1-6 or 7-12 via execution of the executable instructions.

16. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, implements the method of any of claims 1-6 or 7-12.

17. A computer program product comprising a computer program, characterized in that the computer program realizes the method of any of claims 1-6 or 7-12 when executed by a processor.