CN115598395A

CN115598395A - Hall sensing circuit

Info

Publication number: CN115598395A
Application number: CN202211082343.8A
Authority: CN
Inventors: 秦文辉; 盛云
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2023-01-13
Anticipated expiration: 2040-11-20
Also published as: CN112526191A; CN112526191B; CN115598395B; CN115290957A

Abstract

The invention belongs to the field of measurement, and discloses a Hall sensing circuit which comprises a Hall sensor; the rotary switch circuit is connected with the Hall sensor and periodically excites two ports in the Hall sensor and simultaneously receives output signals of the other two ports; the rotary switch circuit simultaneously outputs the output voltage of the Hall switch to the text wave elimination chopper amplifier; the text wave elimination chopper amplifier and the rotary switch circuit use a synchronous clock signal generator as a clock signal source, and the text wave elimination chopper amplifier comprises a text wave elimination loop for inhibiting text wave signals. The technical scheme realizes high bandwidth, high response speed, high measurement precision, low noise and low offset voltage.

Description

Hall sensing circuit

Technical Field

The invention belongs to the field of measurement, and particularly relates to an improvement of a Hall sensing circuit.

Background

Current monitoring is widely used in high power circuit systems, such as motor or load control, inverter circuits, power factor correction and power monitoring systems, etc. In these systems, a current of several amperes to several hundreds or even thousands or tens of thousands of amperes needs to be monitored, and the conventional current monitoring method of monitoring the voltage on the resistor through the series resistor causes great energy loss.

High current systems are typically monitored using hall sensors. According to the magnetic effect of the current, the conducting wire with the current forms a magnetic field which is proportional to the current, the size of the magnetic field can be detected through the Hall effect, and then the size of the current in the conducting wire can be monitored, and the current monitoring system based on the electromagnetic effect is widely applied to high-power circuit systems. Hall sensors are an important component in magnetic sensors among others. The Hall sensor has the characteristics of high linearity and good consistency compared with other magnetic sensors, but the sensitivity of the Hall sensor is general, the offset voltage is large relative to an induction signal, and the measurement precision of the Hall sensor is seriously limited.

Methods for reducing the influence of the offset voltage of the hall sensor on the measurement are mainly classified into two types, static methods and dynamic methods. In the static method, a plurality of Hall sensors are connected in parallel to enable offset voltages of the Hall sensors to offset each other, but the method still has the offset voltage close to the amplitude of the induction signal with a common effect. The dynamic method can modulate the offset voltage of the hall sensor to high frequency, and then the offset voltage becomes a high-frequency Ripple superimposed on the signal, and some methods are still needed to eliminate the Ripple (Ripple).

The dynamic method is divided into two types according to different processing methods of the text wave signals. The common methods mainly have two schemes, the first adopts a low-pass filter for filtering, and the second adopts a wave trap based on sampling for removing.

Referring to fig. 1 and 2, using the low pass filter LPF scheme, the dynamic method employs the rotary switch circuit 104 to excite two of the four ports of the hall sensor 102 by the clock CLK/CLKN or periodic rotation and correspondingly performs voltage detection on the other two ports. The fire port is driven by the CLK clock signal and the output port is driven with the CLK clock inverted signal CLKN.

The output waveform Vo1 includes two portions. The first part is a signal voltage Vh induced by the Hall sensor, the other part is a high-frequency signal converted from an offset voltage Vos after Hall modulation, the high-frequency signal is represented as a square wave at a rotation frequency, and the effective signal frequency of the Hall sensor is unchanged Vh. Vo1 is amplified by a Low Offset amplifier 106 (Low Offset Amp) of the subsequent stage to output Vo2, and Vo2 is filtered by a Low Pass Filter (LPF) of the subsequent stage to output (via VOP/VON port). A Low Pass Filter (LPF) 108 filters out the modulated offset voltage and retains the signal Vo3.

In order to suppress the ripple caused by Vos completely, the bandwidth of the LPF needs to be much smaller than the rotation frequency, which limits the signal bandwidth and makes the response speed of the signal path slow and the response time long. To suppress the ripple better, a second or higher order low pass filter is required, which further deteriorates the response speed.

Referring to fig. 3, a scheme employing a Notch Filter (NF) 110 using a low pass Filter. Unlike a low-pass filter, a trap is used to filter ripples instead of the low-pass filter, and the efficiency of the trap to filter ripples is much higher than that of the low-pass filter.

The effect of the trap filter 110 is related to the trap frequency point, and when the trap frequency is identical to the SPIN Freq, the filter can effectively filter the ripple, and if there is a difference between the two frequencies, the filtering effect will be greatly reduced. Therefore, the trap is generally implemented by using a switched capacitor sampling method, and the sampling frequency is synchronized with the SPIN Freq, so that the trap frequency and the SPIN Freq can be completely the same. However, the switched capacitor sampling causes noise aliasing, deteriorates in-band noise, and limits the response time, the output is changed when the sampling clock is turned over, the response time is limited by the sampling frequency, and the response speed is slow.

Disclosure of Invention

In order to solve the above technical problems, an object of the present invention is to provide a hall sensor circuit that removes ripples, does not limit a response speed, does not alias noise, has a low offset voltage, has low noise, and has a high response speed.

The invention relates to a Hall sensing circuit, comprising: the device comprises a Hall sensor, a rotary switch circuit, a synchronous clock signal generator and a text wave elimination chopper amplifier;

the rotary switch circuit is connected with the Hall sensor and periodically excites two ports in the Hall sensor and simultaneously receives output signals of the other two ports;

the rotary switch circuit outputs an output signal of the Hall sensor to the chopper amplifier for eliminating the Weak wave; the text wave elimination chopper amplifier and the rotary switch circuit use a synchronous clock signal generator as a clock signal source;

the chopping amplifier for eliminating the acoustic wave comprises an acoustic wave eliminating loop and a differential amplifier consisting of a first operational amplifier and a second operational amplifier;

the first operational amplifier or the second operational amplifier comprises a first feedback port, and the first feedback port is connected with the output end of the text wave elimination loop;

the input end of the diploma elimination loop is connected with the output ends of the first operational amplifier and the second operational amplifier.

As a further improvement of an embodiment of the present invention, the operational amplifier includes a first amplifier, a second amplifier, and a first negative feedback transconductance amplifier;

the first amplifier comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier;

the input end of the first chopper is used as the input end of the operational amplifier, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback transconductance amplifier is connected with the first feedback port of the operational amplifier, and the output end of the first negative feedback transconductance amplifier is connected with the output end of the first transconductance amplifier.

As a further refinement of an embodiment of the present invention, the rotary switch circuit periodically 2-phase energizes the hall sensor.

As a further improvement of an embodiment of the present invention, the operational amplifier further includes a second negative feedback transconductance amplifier, a third chopper, and a second feedback port;

the input end of the second negative feedback transconductance amplifier is connected with the second feedback port, and the second negative feedback transconductance amplifier is connected with the input end of the second transconductance amplifier through a third chopper.

As a further improvement of an embodiment of the present invention, the chopping amplifier for removing an acoustic wave includes an acoustic wave removing loop, and the second feedback port is connected to an output end of the acoustic wave removing loop;

As a further improvement of an embodiment of the present invention, the rotary switch circuit periodically excites the hall sensor in 4 phases; or periodically 2-phase exciting the hall sensor, wherein the wiener cancellation loop, the second transconductance amplifier, and the third chopper are electrically shielded.

As a further improvement of an embodiment of the present invention, for "periodically 4-phase energizing the hall sensors", the synchronous clock signal generator generates: a first clock and a first clock inverted signal drive the first chopper and the second chopper;

for "periodically 2-phase energizing the hall sensor", a synchronous clock signal generator generates: the first chopper and the second chopper are driven by the first clock and the first clock inverted signal, and the third chopper is driven by the second clock and the second clock inverted signal;

wherein the clock period of the second clock is twice the clock period of the first clock.

As a further improvement of an embodiment of the present invention, the output terminals of the first operational amplifier and the second operational amplifier are connected in series with three resistors; the input end of the first operational amplifier is connected with the first end of the second resistor, and the input end of the second operational amplifier is connected with the first end of the third resistor.

As a further improvement of an embodiment of the present invention, the cancellation loop includes:

the first diploma elimination loop comprises a chopper and an integrator, wherein the chopper ch is connected with the input end of the integrator Int;

or comprises the following steps:

the second text wave elimination loop comprises a chopper, an integrator and a preamplifier; the chopper is connected with the input end of the integrator Int; the output end of the preamplifier is connected with the input end of the chopper;

or comprises the following steps:

the third text wave elimination loop comprises a chopper, an integrator, a preamplifier and a high-pass filter, and the high-pass filter is connected with the input end of the preamplifier; the output end of the preamplifier is connected with the input end of the chopper; the chopper is connected with the input end of the integrator;

or comprises the following steps:

the fourth text wave elimination loop comprises a chopper, a transconductance amplifier and a transconductance integrator, wherein the output end of the chopper is connected with the input end of the transconductance amplifier, and the output end of the transconductance amplifier is connected with the input end of the transconductance integrator;

or comprises the following steps:

the fifth diploe eliminating loop comprises a chopper, a transconductance amplifier and a transconductance integrator, wherein the input end of the chopper is connected with the output end of the transconductance amplifier, and the output end of the chopper is connected with the input end of the transconductance integrator.

As a further improvement of an embodiment of the present invention, the chopper includes a first switch group connected to the input and output terminals in a forward direction and a second switch group connected to the input and output terminals in a reverse direction, and the first switch group drives the clock source to be a first clock or a second clock; the second switch group drives the clock source to be a first clock inverted signal or a second clock inverted signal, and the output signal of the chopper is continuously reversed along with the clock signal.

Compared with the prior art, the invention has the advantages that the ripple signal is removed by the ripple removing circuit based on the chopping amplifying circuit and the synchronous clock, the response speed is not limited, the noise is not mixed, and the Hall sensor circuit with low offset voltage, low noise and high response speed is realized.

Drawings

FIG. 1 is a block diagram of a prior art Hall sensor rotary excitation scheme incorporating a low pass filter and low pass amplifier;

FIG. 2 is a timing diagram of signals for a prior art Hall sensor rotary excitation in combination with a low pass filter and a low pass amplifier;

FIG. 3 is a prior art frame diagram of a Hall sensor rotating excitation combined low pass filter and trap scheme;

FIG. 4 is a block diagram of a Hall sensor rotary excitation scheme of the present application;

FIG. 5 is a schematic diagram of the circuit structure of the rotary switch of the present application;

FIG. 6 is a timing diagram of the two-phase excitation clock signal and switch control of the present application;

FIG. 7 is a timing diagram of the four phase activation clock signals and switch control of the present application;

FIG. 8 is a schematic diagram of a first embodiment of a chopper amplifier for diploma cancellation;

FIG. 9 is a schematic diagram of five embodiments of a cancellation loop;

FIG. 10 is a schematic diagram of the chopper structure;

FIG. 11 is a schematic diagram of a second embodiment of a chopper amplifier for diploma cancellation;

fig. 12 is a schematic diagram of an operational amplifier implementation in a text wave canceling chopper amplifier.

Detailed Description

The following detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings to assist those skilled in the art in understanding the present invention. In this application, "bank" is used to represent a plurality of electronic devices of the same type, for example, a sampling capacitor bank represents a plurality of sampling capacitors, and a switch bank represents a plurality of switches having the same function or switches driven by the same clock. In this application, "input" means a positive input port and a negative input port, and "output" means a positive output port and a negative output port.

Referring to fig. 4, a Hall sensing circuit framework architecture diagram is shown, which includes a Hall sensor (Hall) 402 and associated circuitry coupled to the Hall sensor 402, as well as circuitry for processing the Hall sensor 402 signal. A hall sensing circuit, a westerncancellation chopper amplifier 406, is included, and in the figure is a single hall sensor 402. To further reduce offset signals, one skilled in the art may optionally connect multiple hall sensors 402 in parallel.

The hall sensing circuit includes a combination of a hall sensor 402, a rotary switch circuit 404, and an westerncancellation chopper amplifier 406. The hall sensor 402 includes four ports, two for inputting excitation signals and two for outputting sensing signals. Four ports of the hall sensor 402 are connected to first, second, third, and fourth ports (a, b, c, d) of the rotary switch circuit 404, respectively. The rotary switch circuit 404 periodically energizes two ports in the hall sensor 402 while receiving output signals of the other two ports; the rotary switch circuit 404 outputs signals output by the other two ports to the diploe elimination chopper amplifier 406; the text wave canceling chopper amplifier 406 and the rotary switch circuit 404 use a synchronous clock signal generator 408 as a clock signal source.

At least one chopper circuit in the chopping amplifier 406 for eliminating the text wave can eliminate the text wave signal, and the synchronous clock signal used by the chopping amplifier 406 for eliminating the text wave and the rotary switch circuit 404 as the driving signal source has good synchronous response speed.

Referring to fig. 5, a schematic diagram of an embodiment of the rotary switch circuit 404 is shown, in which the switches with the same reference number are the switch sets with the same operation timing, i.e. simultaneously turned on or simultaneously turned off. The operation sequence of the reference numbers with S suffix and the reference numbers without S suffix is the same, such as the operation sequence of P1/P1S and P2/P2S.

The rotary switch circuit 404 is composed of an excitation switch group 502 for controlling an excitation signal and a sensing signal output switch group 504. The hall sensor 402 comprises a first port a, a second port b, a third port c and a fourth port d; the excitation switch group 502 includes: a first switch group P1 for forming an excitation signal loop at the first port a and the third port c, and a second switch group P2 for forming an excitation loop at the second port b and the fourth port d; a third switch group P3 for forming an excitation signal loop at the third port c and the first port a and a fourth switch group P4 for forming an excitation signal loop at the fourth port d and the second port b; the output switch set 504 includes: a first output switch group P1S for forming an output loop at the second port b and the fourth port d, and a second output switch group P2S for forming an output loop at the third port c and the first port a; a third output switch group P3S for forming an output loop at the fourth port d and the second port, and a fourth switch group P4S for forming an output loop at the first port a and the third port c. And the first to fourth switch groups respectively comprise a switch connected with the excitation signal port and a switch to the ground. The specific connection mode of the excitation switch group 502 and the output switch group 504 with the switches is as follows: (for simplicity, only switch numbers are identified) the first port a is connected to P1, P3, P4S, P2S, the second port b is connected to P2, P4, P1S, P3S, the third port c is connected to P3, P1, P2S, P4S, and the fourth port d is connected to P4, P2, P3S, P1S.

The output switch group 504 of the rotary switch circuit 404 is connected to an output capacitor Cs, a first pole of the output capacitor Cs is a positive output terminal VOP of the rotary switch circuit 404, and a second pole of the output capacitor Cs is a negative output terminal VON of the rotary switch. The output capacitor Cs is used for sampling the output voltage generated by the hall sensor 402, and the output voltage Vo1 is the sum of the voltage Vh and the voltage Vos of the effective signal Vh of the hall sensor 402.

The rotary switch circuit 404 performs four-phase or two-phase excitation on the hall sensor 402 and receives signals through two other ports except for an excitation port under the action of the excitation switch group 502 and the output switch group 504 under the switch control timing. The following table is made according to the mapping relation between the phase and the excitation port and direction, the mapping relation between the sampling direction and the offset voltage direction, and the mapping relation between the phase and the offset voltage direction and the excitation port and direction, and between the sampling port and direction and the signal direction and between the sampling port and the offset voltage direction:

in the table, "+, -" indicates the direction of the hall voltage Vh and the offset voltage Vos, and "- >" indicates the direction of the voltage of the excitation port or the output port.

Fig. 5 and 6 are clock signals generated by the synchronous clock signal generator 408, and control timings of the above-described switching components. The synchronous clock signal generator 408 generates a first clock C1 and a second clock C2, wherein the clock C2 period of the second clock is twice the clock C1 period of the first clock. The activation process of the rotary switch circuit 404 is further described below in conjunction with a clock and control timing.

Fig. 6 shows the control timing of the two-phase rotary switch, and the synchronous clock signal generator 408 generates the clock signal C1 and the clock signal inversion driving signal C1N. And in a first clock period t1, the switches P1 and P1S are closed, the excitation ports and the direction are a- > c, the first port a and the third port c form an excitation loop, the output ports and the direction are b- > d, and the Hall voltage Vh and the offset voltage Vos are both output in the positive direction. And in a second clock period t2, the switches P1 and P1S are opened while the switches P2 and P2S are closed, the excitation port and the direction are b- > d, namely the second port b and the fourth port d form an excitation loop, the output port and the direction are c- > a, the Hall voltage Vh is output in a positive direction, and the offset voltage Vos is output in a negative direction.

Therefore, the offset voltage Vos changes along with the direction of the clock signal C1, the signal is modulated into a high-frequency signal with the same frequency as the clock signal, the high-frequency signal is superposed on the hall voltage Vh signal in a mode of a text wave signal to form the output signal Vo1 of the rotary switch circuit, and the high-frequency signal is convenient for subsequent processing in a mode of filtering and the like.

In fig. 6, the switches P3, P4, P3S and P4S are always kept in an open state, i.e. the excitation signals of the two phases c- > a.d- > b and the corresponding output signals thereof are shielded by means of a control timing. In fig. 7, the four-phase rotary switch circuit 404 further includes the two-phase excitation signal and the corresponding output signal.

Four different timings are included in the four-phase rotary switch circuit 404. The timing of the activation of the switch bank 502 and the output switch bank 504 in the first clock cycle t1 and the second clock cycle t2 is different from the timing of the operation of the two-phase rotary switch shown in fig. 3. In a third clock period t3, the P3 and the P3S are closed, and the excitation port and the direction are c- > a output port and d- > b; in four clock cycles t4, P4S close the excitation ports and direction d- > b and the output ports and direction a- > c. It can be seen that the sign of the offset signal Vos output at the 4-phase rotary switch circuit 404 changes with the direction of the clock signal and is superimposed on the hall voltage Vh signal in a square wave signal to form the four-phase rotary switch circuit output signal Vo1.

It should be noted that the two-phase rotary switch circuit or the four-phase rotary switch circuit has a certain time delay (as labeled d1 to d4 in fig. 6 and 7) to the control timing of the excitation and output switch groups. The falling edges of the output switch sets P1S-P4S lead the corresponding excitations P1-P4 a little and the rising edges lag the corresponding excitations P1-P4 a little. Because the falling/rising edges of P1-P4 mean that the switch is in the switching process, and the output of the HALL is not established at this time, P1S-P4S has a dead time at the position corresponding to the edge of P1-P4, and the error caused by amplifying the output which is not established by the HALL by the later stage sampling is avoided. Meanwhile, the clock of the later-stage ripple cancellation chopper amplifier needs to be aligned with the falling edges of P1S-P4S, so that the modulated Vh can be well suppressed by the ripple cancellation loop of the later-stage amplifier.

Referring to fig. 4 and 8, the positive and negative input ports (VIP, VIN) of the text wave cancellation chopper amplifier 406 are connected to the positive and negative output ports (VOP, VON) of the rotary switch circuit 404, respectively. Text wave canceling chopper amplifier 406 includes a variety of implementations, and this application illustrates two exemplary implementations.

Fig. 8 shows a first implementation of dipleg canceling chopper amplifier 406. It comprises a first amplifier 802, a second amplifier 804 and a first negative feedback circuit 806 connected in series; the first amplifier 802 includes a first transconductance amplifier GM1 and a first chopper ch1 connected to an input end of the first transconductance amplifier GM1, an input end of the first chopper ch1 serves as an input end of the text wave cancellation chopper amplifier 406, and the chopper ch1 is configured to cancel an offset voltage of the first transconductance amplifier GM 1.

The second amplifier 804 comprises a second transconductance amplifier GM2 and a second chopper ch2 connected with the input end of the second transconductance amplifier GM 2; the input end of the second chopper ch2 is connected with the output end of the first transconductance amplifier GM 1; the input terminal of the first negative feedback circuit 806 is connected to the output terminal of the second transconductance amplifier GM2.

The first negative feedback circuit 806 is used to suppress the second transconductance amplifier GM2 diploe output. The amplifier comprises a text wave elimination loop RRL and a transconductance amplifier GMa connected with the text wave elimination loop RRL, and the output end of the transconductance amplifier GMa is used as a first negative feedback circuit output end 806. The input end of the transconductance amplifier GMa is connected with the output end of the ripple wave eliminating loop RRL, and the ripple wave signal in the output signal collected by the text wave eliminating loop RRL is demodulated and amplified and negatively fed back to the output port of the first transconductance amplifier GM1 through the transconductance amplifier GMa to inhibit the ripple wave output by the second transconductance amplifier GM2.

In fig. 8, if the rotating switch circuit 404 performs four-phase sampling, the text wave canceling chopper amplifier 406 further comprises a second negative feedback circuit 808, an input end of the second negative feedback circuit 808 is connected with an output end of the second transconductance amplifier GM2, and an output end of the second negative feedback circuit 808 is connected with an input end of the second transconductance amplifier GM2. The structure of the second negative feedback circuit 808 is the same as that of the first negative feedback circuit 806, the output end of the diploma elimination loop RRL is connected with the input end of the third chopper ch3, and the output end of the third chopper ch3 is connected with the input end of the second-stage transconductance amplifier GM2.

For the four-phase rotary switch circuit, the first clock C1 and the first clock inversion signal C1N drive the first chopper ch1 and the second chopper ch2, the second clock signal C2 has a clock period twice as long as the clock period of the first clock signal C1, and the second clock signal C2 and the second clock inversion signal C2N are used to drive the third chopper. So that the ripple cancellation path of the second negative feedback circuit 808 can effectively suppress the ripple at half the rotation frequency. For a two-phase rotary switch circuit, the second negative feedback circuit 808 may be removed or electrically turned off.

Referring to fig. 9, several typical implementations of the RRL are listed, and the RRL has a common feature that the RRL mainly includes a chopper and an integrator, the chopper can demodulate the ripple in the output signal back to DC, the ripple is amplified by the integrator and fed back to the signal path, and the RRL can suppress the output ripple of the amplifier to be negligible relative to the hall signal through negative feedback.

With continued reference to fig. 9, first venturi cancellation loop 902 includes a chopper ch connected to an input of integrator Int and integrator Int. The second dipleg elimination loop 904 adds a preamplifier GM2 whose output is connected to the input of said chopper ch, on the basis of the first dipleg elimination loop RRL.

For the first ripple cancellation loop 902, whose residual ripple is determined by the offset voltage of the amplifier in the integrator Int, a pre-amplifier GM2 is added before the chopper ch, which can further reduce the ripple and suppress it by the gain of the pre-amplifier GM2 at the chopping frequency.

The third dipleg loop 906 adds a high pass filter HPF to the second dipleg loop 904, the high pass filter HPF being connected to the preamplifier AO input. The high pass filter HPF is an RC structure as shown in the figure. The high pass filter HPF may allow the high frequency ripple signal to pass and block the hall signal Vh before the preamplifier so that the RRL processes the hall signal Vh less, only the ripple. Since the hall signal Vh, which has a frequency lower than the chopping frequency, is modulated by the chopper ch to the chopping frequency and is suppressed by the low-pass characteristic of the integrator Int while passing through the integrator, the RRL does not feed back the useful hall signal Vh, but feeds back only the ripple and suppresses the ripple.

The fourth dipleg elimination loop 908 dipleg elimination loop comprises a chopper ch, a transconductance amplifier GM1 and a transconductance integrator Int ', wherein the output end of the chopper ch is connected with the input end of the transconductance amplifier, and the output end of the transconductance amplifier GM1 is connected with the input end of the transconductance integrator Int'.

The fifth text wave elimination loop 910 includes a chopper ch, a transconductance amplifier GM1, and a transconductance integrator Int ', wherein an input end of the chopper ch is connected to an output end of the transconductance amplifier GM1, and an output end of the chopper ch is connected to an input end of the transconductance integrator Int'. Chopper ch of fifth text wave cancellation loop 910 may be moved from across the input to the output of the amplifier to help reduce the residual ripple amplitude.

Referring to the implementation manner of the chopper shown in fig. 10, the chopper includes a first switch group S1 forward connected to the input and output terminals and a second switch group S2 backward connected to the input and output terminals, the first switch group drives the clock source to be C1 or C2, correspondingly, the second switch group drives the clock source to be C1N or C2N, and the switching output signal of the chopper is continuously commutated along with the clock signal.

Fig. 11 shows a second implementation of the chopping-wave cancellation chopper amplifier 406, in which the implementation of the chopper and the chopping-wave cancellation loop RRL is the same as the implementation of the first chopping-wave cancellation chopper amplifier 406.

The acoustic wave canceling chopper amplifier 406 includes a differential amplifier composed of a first operational amplifier OPAMP1 and a second operational amplifier OPAMP2, and an acoustic wave canceling circuit RRL. The output ends of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are connected with three resistors (R1, R2 and R3) in series; the input end of the first operational amplifier OPAMP1 is connected with a second resistor R2, and the input end of the second operational amplifier OPAMP2 is connected with a third resistor R3; the first operational amplifier OPAMP1 or the second operational amplifier OPAMP2 comprises a first feedback port VIP1/VIN1, the positive input VIP1 and the negative input VIN1 of the first feedback port VIP1/VIN1 being connected to the positive output VOP and the negative output VON, respectively, of the wenbo cancellation loop RRL, the positive input VIP and the negative input VIN of the wenbo cancellation loop RRL being connected to the outputs of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP 2.

The operational amplifiers (OPAMP 1/OPAMP 2) described with reference to fig. 12 comprise a first amplifier 1202, a second amplifier 1204 and a first degeneration transconductance amplifier GMa; the first amplifier 1202 comprises a first transconductance amplifier GM1 and a first chopper ch1 connected with an input end of the first transconductance amplifier GM1, and the second amplifier 1204 comprises a second transconductance amplifier GM2 and a second chopper ch2 connected with an input end of the second transconductance amplifier GM 2; the input end of the first chopper ch1 is used as the input end of an operational amplifier, and the input end of the second chopper ch2 is connected with the output end of the first transconductance amplifier GM 1; the input end of the first negative feedback transconductance amplifier Gma is connected with a first feedback port VIP1/VIN1 of the operational amplifier, and the output end of the first negative feedback transconductance amplifier Gma is connected with the output end of the first transconductance amplifier GM 1.

Referring to fig. 11 and 2, if the rotary switch circuit is 4-phase energized, the operational amplifier further includes an output connection of an westernelimination loop RRL 'connected to the second feedback port VIP2/VIN2, an input of the westernelimination loop RRL' being connected to the outputs of the first and second operational amplifiers OPAMP1 and OPAMP 2. Correspondingly, a second negative feedback transconductance amplifier GMb with the input end connected with the second feedback port VIP2/VIN2 is included inside the operational amplifier, and the second negative feedback transconductance amplifier GMb is connected with the input end of the second transconductance amplifier Gm2 through a third chopper ch 3; the first clock C1 and the first clock inverted signal C1N drive the first chopper ch1 and the second chopper ch2; the second clock C2 and the second clock inverted signal C2N drive the third chopper ch3. The weg cancellation loop RRL', the second transconductance amplifier Gmb and the third chopper ch3 may be electrically shielded or deleted from the circuit if the rotary switch circuit is 2-phase excited.

In summary, the present invention cooperates with the rotating switch circuit and the switching clock and clock edge of the post-stage ripple cancellation chopper amplifier, and the ripple cancellation loop in the post-stage ripple cancellation chopper amplifier is used to cancel the offset voltage modulated by the hall element. The two-phase rotary switch circuit and the four-phase rotary switch circuit can be compatible through a reasonable switching sequence. Through 2 loops, ripples at the rotating frequency and at the half position of the rotating frequency are respectively suppressed, and ripples caused by four-phase rotation can be effectively eliminated.

According to the invention, a low-pass or high-order low-pass filter with low cut-off frequency is not added in a signal path, a switch sampling circuit is not added, the bandwidth and delay time of the signal path are not influenced, and the noise aliasing effect caused by switch sampling is avoided, so that the high bandwidth, the high response speed, the high measurement precision, the small noise and the small offset voltage are realized. The measurement precision and the delay time are short enough, and when the detected system current is over-current, the system can quickly receive an over-current signal and start protective measures to protect the safety of the whole system.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims

1. A hall sensing circuit, comprising: the device comprises a Hall sensor (402), a rotary switch circuit (404), a synchronous clock signal generator (408) and a text wave elimination chopper amplifier (406);

the rotary switch circuit (404) is connected with the Hall sensor (402), and the rotary switch circuit (404) periodically excites two ports of the Hall sensor (402) and simultaneously receives output signals of the other two ports;

the rotary switch circuit (404) outputs an output signal of the Hall sensor (402) to the Venturi wave elimination chopper amplifier (406); the text wave cancellation chopper amplifier (406) and the rotary switch circuit (404) use a synchronous clock signal generator (408) as a clock signal source;

the acoustic wave cancellation chopper amplifier (406) comprises an acoustic wave cancellation circuit (RRL), and a differential amplifier consisting of a first operational amplifier (OPAMP 1) and a second operational amplifier (OPAMP 2);

the first operational amplifier (OPAMP 1) or the second operational amplifier (OPAMP 2) comprises a first feedback port (VIP 1/VIN 1), and the first feedback port (VIP 1/VIN 1) is connected with the output end of the Weak cancellation loop (RRL);

the input end of the loop (RRL) is connected with the output ends of the first operational amplifier (OPAMP 1) and the second operational amplifier (OPAMP 2).

2. The hall sensing circuit of claim 1 wherein the operational amplifier (OPAMP 1/OPAMP 2) comprises a first amplifier (1202), a second amplifier (1204), and a first degeneration transconductance amplifier (GMa);

the first amplifier (1202) comprises a first transconductance amplifier (GM 1) and a first chopper (ch 1) connected to an input of the first transconductance amplifier (GM 1); the second amplifier 1204 comprises a second transconductance amplifier (GM 2) and a second chopper (ch 2) connected with the input end of the second transconductance amplifier (GM 2);

an input terminal of a first chopper (ch 1) is used as an input terminal of an operational amplifier (OPAMP 1/OPAMP 2), and an input terminal of the second chopper (ch 2) is connected with an output terminal of the first transconductance amplifier (GM 1); the input end of the first negative feedback transconductance amplifier (GMa) is connected with the first feedback port (VIP 1/VIN 1) of the operational amplifier (OPAMP 1/OPAMP 2), and the output end of the first negative feedback transconductance amplifier (GMa) is connected with the output end of the first transconductance amplifier (GM 1).

3. The hall sensing circuit of claim 2, wherein the rotary switch circuit (404) periodically 2-phase energizes the hall sensor (402).

4. The hall sensing circuit of claim 2, wherein the operational amplifier (OPAMP 1/OPAMP 2) further comprises a second degeneration transconductance amplifier (GMb), a third chopper (ch 3), and a second feedback port VIP2/VIN2;

the input of the second negative feedback transconductance amplifier (GMb) is connected to the second feedback port (VIP 2/VIN 2), and the second negative feedback transconductance amplifier (GMb) is connected to the input of the second transconductance amplifier (GM 2) through a third chopper (ch 3).

5. The Hall sensing circuit according to claim 4, wherein the chopping amplifier (406) comprises a Weak cancellation loop (RRL '), the second feedback port (VIP 2/VIN 2) being connected to the output of the Weak cancellation loop (RRL');

the input end of the loop (RRL') is connected with the output ends of the first operational amplifier (OPAMP 1) and the second operational amplifier (OPAMP 2).

6. The Hall sensing circuit according to claim 5, wherein the rotary switch circuit (404) periodically 4-phase energizes the Hall sensor (402); or periodically 2-phase energizing the Hall sensor (402), wherein the wiener cancellation loop (RRL'), the second transconductance amplifier (GMb), and the third chopper (ch 3) are electrically shielded.

7. The Hall sensing circuit of claim 6,

for "periodically 4-phase energizing the hall sensor (402)", the synchronous clock signal generator (408) generates: a first clock (C1) and a first clock inversion signal (C1N) drive the first chopper (ch 1) and the second chopper (ch 2);

for "periodically 2-phase energizing the hall sensor (402)", the synchronous clock signal generator (408) generates: a first clock (C1) and a first clock inverted signal (C1N) drive the first chopper (ch 1) and the second chopper (ch 2), and a second clock (C2) and a second clock inverted signal (C2N) drive the third chopper (ch 3);

wherein the second clock (C2) has twice the clock period of the first clock (C1).

8. The Hall sensing circuit according to claim 5, wherein the output terminals of the first operational amplifier (OPAMP 1) and the second operational amplifier (OPAMP 2) are connected in series with three resistors (R1, R2, R3); the input terminal of the first operational amplifier (OPAMP 1) is connected to the first terminal of the second resistor (R2), and the input terminal of the second operational amplifier (OPAMP 2) is connected to the first terminal of the third resistor (R3).

9. The Hall sensing circuit according to claim 1 or 5, characterized in that the cancellation loop (RRL/RRL') comprises:

a first dipleg elimination loop (902) comprising a chopper (ch) and an integrator (Int), said chopper (ch) being connected to the input of the integrator (Int);

or comprises the following steps:

a second wavelet cancellation loop (904) comprising a chopper (ch), and integrator (Int) and preamplifier (GM 2); the chopper (ch) is connected with the input end of the integrator (Int); the output end of the preamplifier (GM 2) is connected with the input end of the chopper (ch);

or comprises the following steps:

a third text wave elimination loop (906) comprising a chopper (ch), and integrator (Int), a preamplifier (Ao) and a High Pass Filter (HPF); a High Pass Filter (HPF) is connected with the input end of the preamplifier (Ao); the output end of the preamplifier (GM 2) is connected with the input end of the chopper (ch); the chopper (ch) is connected with the input end of the integrator (Int);

or comprises the following steps:

a fourth text wave elimination loop (908) comprising a chopper (ch), a transconductance amplifier (GM 1) and a transconductance integrator (Int'); the output end of the chopper (ch) is connected with the input end of a transconductance amplifier (GM 1), and the output end of the transconductance amplifier (GM 1) is connected with the input end of a transconductance integrator (Int');

or comprises the following steps:

the fifth text wave elimination loop (910) comprises a chopper (ch), a transconductance amplifier (GM 1) and a transconductance integrator (Int '), wherein the input end of the chopper (ch) is connected with the output end of the transconductance amplifier (GM 1), and the output end of the chopper (ch) is connected with the input end of the transconductance integrator (Int').

10. The hall sensing circuit according to claim 9, wherein the chopper (ch) comprises a first switch group (S1) connected to the input and output terminals in a forward direction and a second switch group (S2) connected to the input and output terminals in a reverse direction, the first switch group (S1) driving a clock source to be a first clock (C1) or a second clock (C2); the second switch group (S2) drives the clock source to be a first clock inverted signal (C1N) or a second clock inverted signal (C2N), and the output signal of the chopper is continuously reversed along with the clock signal.