CN112526191A

CN112526191A - Hall sensing circuit

Info

Publication number: CN112526191A
Application number: CN202011314470.7A
Authority: CN
Inventors: 秦文辉; 盛云
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2021-03-19
Anticipated expiration: 2040-11-20
Also published as: CN115598395B; CN115598395A; CN112526191B; CN115290957A

Abstract

The invention belongs to the field of measurement and discloses a Hall sensing circuit which comprises a Hall sensor; the rotary switch circuit is connected with the Hall sensor and periodically excites two ports in the Hall sensor and simultaneously receives output signals of the other two ports; the rotary switch circuit simultaneously outputs the output voltage of the Hall switch to the chopper amplifier for eliminating the Weak wave; the text wave elimination chopper amplifier and the rotary switch circuit use a synchronous clock signal generator as a clock signal source. The technical scheme realizes high bandwidth, high response speed, high measurement precision, low noise and low offset voltage.

Description

Hall sensing circuit

Technical Field

The invention belongs to the field of measurement, and particularly relates to an improvement of a Hall sensing circuit.

Background

Current monitoring is widely used in high power circuit systems, such as motor or load control, inverter circuits, power factor correction and power monitoring systems, etc. In these systems, a current of several amperes to hundreds of even thousands or tens of thousands of amperes needs to be monitored, and the conventional current monitoring method for monitoring the voltage on the resistor through the series resistor causes great energy loss.

High current systems are typically monitored using hall sensors. According to the magnetic effect of the current, the conducting wire with the current forms a magnetic field proportional to the current around, the size of the magnetic field can be detected through the Hall effect, and then the size of the current in the conducting wire can be monitored. Hall sensors are an important component in magnetic sensors among others. The Hall sensor has the characteristics of high linearity and good consistency compared with other magnetic sensors, but the sensitivity of the Hall sensor is general, the offset voltage is large relative to an induction signal, and the measurement precision of the Hall sensor is seriously limited.

Methods for reducing the influence of the offset voltage of the hall sensor on the measurement are mainly classified into two types, static methods and dynamic methods. In the static method, a plurality of Hall sensors are connected in parallel to enable offset voltages of the Hall sensors to offset each other, but the method still has the offset voltage close to the amplitude of the induction signal with a common effect. The dynamic method can modulate the offset voltage of the hall sensor to high frequency, and the offset voltage becomes a high-frequency Ripple superimposed on the signal, and some methods are still needed to eliminate the Ripple (Ripple).

The dynamic method is divided into two types according to different processing methods of the text wave signals. The common methods mainly have two schemes, the first adopts a low-pass filter for filtering, and the second adopts a trap filter based on sampling for removing.

Referring to fig. 1 and 2, using the low pass filter LPF scheme, the dynamic method employs the rotary switch circuit 104 to excite two of the four ports of the hall sensor 102 by the clock CLK/CLKN or periodic rotation and correspondingly performs voltage detection on the other two ports. The fire port is driven by the CLK clock signal and the output port is driven with the CLK clock inverted signal CLKN.

The output waveform Vo1 includes two portions. The first part is a signal voltage Vh induced by the Hall sensor, the other part is a high-frequency signal converted from an offset voltage Vos after Hall modulation, the high-frequency signal is represented as a square wave at a rotation frequency, and the effective signal frequency of the Hall sensor is unchanged Vh. Vo1 is amplified by the Low Offset amplifier 106(Low Offset Amp) of the subsequent stage to output Vo2, and Vo2 is filtered by the Low Pass Filter (LPF) of the subsequent stage to output (through the VOP/VON port). A Low Pass Filter (LPF)108 filters out the modulated offset voltage and retains the signal Vo 3.

In order to suppress the ripple caused by Vos completely, the bandwidth of the LPF needs to be much smaller than the rotation frequency, which limits the signal bandwidth and makes the response speed of the signal path slow and the response time long. To better suppress the ripple, a second or higher order low pass filter is required, which further deteriorates the response speed.

Referring to fig. 3, a scheme employing a Notch Filter (NF) 110 using a low pass Filter. Unlike low pass filters, traps are used to filter out ripple instead of low pass filters, and traps filter out ripple much more efficiently than low pass filters.

The effect of the trap filter 110 is related to the trap frequency point, and when the trap frequency is identical to the SPIN Freq, the ripple can be effectively filtered, and if the two frequencies have a difference, the filtering effect can be greatly reduced. Therefore, the trap is generally implemented by using a switched capacitor sampling method, and the sampling frequency is synchronized with the SPIN Freq, so that the trap frequency and the SPIN Freq can be completely the same. However, the switched capacitor sampling causes noise aliasing, deteriorates in-band noise, and limits the response time, the output is changed when the sampling clock is turned over, the response time is limited by the sampling frequency, and the response speed is slow.

Disclosure of Invention

In order to solve the above-mentioned technical problems, an object of the present invention is to provide a hall sensor circuit that removes ripples, and has no limitation on response speed, no aliasing noise, low offset voltage, low noise, and high response speed.

The invention relates to a Hall sensing circuit, comprising: a Hall sensor;

the rotary switch circuit is connected with the Hall sensor and periodically excites two ports in the Hall sensor and simultaneously receives output signals of the other two ports;

the rotary switch circuit simultaneously outputs the output voltage of the Hall switch to the chopper amplifier for eliminating the Weak wave; the text wave elimination chopper amplifier and the rotary switch circuit use a synchronous clock signal generator as a clock signal source.

As a further improvement of an embodiment of the present invention, the rotary switch circuit includes an excitation switch set and an output switch set, and the hall sensor includes a first port, a second port, a third port, and a fourth port; the excitation switch group includes: the first switch group is used for forming an excitation signal loop at the first port and the third port, and the second switch group is used for forming an excitation loop at the second port and the fourth port; the output switch group includes: the first output switch group is used for forming an output loop at the second port and the fourth port, and the second output switch group is used for forming an output loop at the third port and the first port.

As a further improvement of an embodiment of the present invention, the excitation switch group includes: a third switch set for forming an excitation signal loop at the third port and the first port and a fourth switch set for forming an excitation signal loop at the fourth port and the second port; the output switch group includes: a third output switch set for forming an output loop at the fourth port and the second port and for forming an output loop at the first port and the third port.

As a further improvement of an embodiment of the present invention, the output switch group of the rotary switch circuit is connected to an output capacitor, a first pole of the output capacitor is a positive output terminal of the rotary switch circuit, and a second pole of the output capacitor is a negative output terminal of the rotary switch.

As a further improvement of an embodiment of the present invention, the text wave cancellation chopper amplifier includes a first wave amplifier, a second amplifier and a first negative feedback circuit connected in series; the first wave amplifier comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier; the input end of the first chopper is used as the input end of the chopping amplifier for eliminating the text wave, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback circuit is connected with the output end of the second transconductance amplifier, and the output end of the first negative feedback circuit is connected with the output end of the first transconductance amplifier and used for eliminating the output end diplonic signal of the first transconductance amplifier.

As a further improvement of one embodiment of the present invention, the diploe canceling chopper amplifier includes a second negative feedback circuit, an input end of the second negative feedback circuit is connected to an output end of the second transconductance amplifier, and an output end of the second negative feedback circuit is connected to an input end of the second transconductance amplifier, and is configured to cancel the diploe signal at the input end of the second transconductance amplifier.

As a further improvement of an embodiment of the present invention, the second negative feedback circuit is connected to an input terminal of the second transconductance amplifier through a third chopper; the synchronous clock signal generator generates a first clock and a second clock, and the clock period of the second clock is twice that of the first clock; the first clock and the first clock inverted signal drive the first chopper and the second chopper; the second clock and the second clock inverted signal drive the third chopper.

As a further improvement of one embodiment of the present invention, the first negative feedback circuit or the second negative feedback circuit includes an diploe elimination loop and a transconductance amplifier connected to the diploe elimination loop, and an output end of the transconductance amplifier is used as an output end of the first negative feedback circuit or the second negative feedback circuit.

As a further improvement of an embodiment of the present invention, the diploe cancellation chopper amplifier includes a differential amplifier composed of a first operational amplifier and a second operational amplifier, and a diploe cancellation loop; the output ends of the first operational amplifier and the second operational amplifier are connected with three resistors in series; the input end of the first operational amplifier is connected with the second resistor, and the input end of the second operational amplifier is connected with the third resistor; the first operational amplifier or the second operational amplifier comprises a first feedback port, the first feedback port is connected with the output end of the acoustic wave elimination loop, and the input end of the acoustic wave elimination loop is connected with the output ends of the first operational amplifier and the second operational amplifier.

As a further improvement of an embodiment of the present invention, the operational amplifier includes a first amplifier, a second amplifier, and a first negative feedback transconductance amplifier; the first amplifier comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier; the input end of the first chopper is used as the input end of an operational amplifier, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback transconductance amplifier is connected with the first feedback port of the operational amplifier, and the output end of the first negative feedback transconductance amplifier is connected with the output end of the first transconductance amplifier.

As a further improvement of an embodiment of the present invention, said second feedback port said first feedback port is connected to an output of an acoustic wave cancellation loop, and an input of said acoustic wave cancellation loop is connected to outputs of said first and second operational amplifiers.

As a further improvement of an embodiment of the present invention, the operational amplifier includes a second negative feedback transconductance amplifier whose input end is connected to the second feedback port, and the second negative feedback transconductance amplifier is connected to the input end of the second transconductance amplifier through a third chopper of the chopper; the synchronous clock signal generator generates a first clock and a second clock, and the clock period of the second clock is twice that of the first clock; the first clock and the first clock inverted signal drive the first chopper and the second chopper; the second clock and the second clock inverted signal drive the third chopper.

As a further improvement of an embodiment of the present invention, the diploma elimination loop includes a chopper and an integrator, and the chopper is connected with an input end of the integrator.

As a further improvement of an embodiment of the present invention, said dipleg elimination loop includes a preamplifier having an output connected to an input of said chopper.

As a further improvement of one embodiment of the present invention, said text wave elimination loop comprises a high pass filter connected to an input of said preamplifier.

As a further improvement of an embodiment of the present invention, the diploe elimination loop includes a chopper, a transconductance amplifier and a transconductance integrator, an output end of the chopper is connected to an input end of the transconductance amplifier, and an output end of the transconductance amplifier is connected to an input end of the transconductance integrator.

As a further improvement of one embodiment of the present invention, the diploe elimination loop includes a chopper, a transconductance amplifier and a transconductance integrator, an input end of the chopper is connected to an output end of the transconductance amplifier, and an output end of the chopper is connected to an input end of the transconductance integrator.

Compared with the prior art, the invention has the advantages that the ripple wave removing circuit is realized on the basis of the chopping wave amplifying circuit and the synchronous clock, the response speed is not limited, the aliasing noise is avoided, and the Hall sensor circuit with low offset voltage, low noise and high response speed is realized.

Drawings

FIG. 1 is a block diagram of a prior art Hall sensor rotary excitation scheme incorporating a low pass filter and low pass amplifier;

FIG. 2 is a timing diagram of signals for a prior art Hall sensor rotary excitation in combination with a low pass filter and a low pass amplifier;

FIG. 3 is a block diagram of a prior art Hall sensor rotational excitation in combination with a low pass filter and trap scheme;

FIG. 4 is a block diagram of a Hall sensor rotary excitation scheme of the present application;

FIG. 5 is a schematic diagram of the circuit structure of the rotary switch of the present application;

FIG. 6 is a timing diagram of the two-phase excitation clock signal and switch control of the present application;

FIG. 7 is a timing diagram of the four phase activation clock signals and switch control of the present application;

FIG. 8 is a schematic diagram of a first embodiment of a chopper amplifier for diploma cancellation;

FIG. 9 is a schematic diagram of six embodiments of a cancellation loop;

FIG. 10 is a schematic diagram of the chopper structure;

FIG. 11 is a schematic diagram of a second embodiment of a chopper amplifier for diploma cancellation;

fig. 12 is a schematic diagram of an operational amplifier implementation in a text wave canceling chopper amplifier.

Detailed Description

The following detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings to assist those skilled in the art in understanding the present invention. In this application, "bank" is used to represent a plurality of electronic devices of the same type, for example, a sampling capacitor bank represents a plurality of sampling capacitors, and a switch bank represents a plurality of switches having the same function or switches driven by the same clock. In this application, "input" means a positive input port and a negative input port, and "output" means a positive output port and a negative output port.

Referring to fig. 4, a Hall sensing circuit framework architecture diagram is shown, which includes a Hall sensor (Hall)402 and associated circuitry coupled to the Hall sensor 402, as well as circuitry for processing the Hall sensor 402 signal. A hall sensing circuit, a westerncancellation chopper amplifier 406, and in the figure a single hall sensor 402, are included, and optionally a plurality of hall sensors 402 may be connected in parallel by one skilled in the art to further reduce offset signals.

The hall sensing circuit includes a combination of a hall sensor 402, a rotary switch circuit 404, and an westerncancellation chopper amplifier 406. The hall sensor 402 includes four ports, two for inputting excitation signals and two for outputting sensing signals. The four ports of the hall sensor 402 are connected to the first, second, third, and fourth ports (a, b, c, d) of the rotary switch circuit 404, respectively. The rotary switch circuit 404 periodically energizes two ports in the hall sensor 402 while receiving output signals of the other two ports; the rotary switch circuit 404 outputs signals output by the other two ports to the diploe elimination chopper amplifier 406; the text wave canceling chopper amplifier 406 and the rotary switch circuit 404 use a synchronous clock signal generator 408 as a clock signal source.

At least one chopper circuit in the text wave elimination chopper amplifier 406 can eliminate text wave signals, and the text wave elimination chopper amplifier 406 and the rotary switch circuit 404 have good synchronous response speed by using synchronous clock signals as driving signal source signals.

Referring to fig. 5, a schematic diagram of an embodiment of the rotary switch circuit 404 is shown, wherein the switches with the same reference number are the switch sets with the same operation timing, i.e. simultaneously turned on or simultaneously turned off. The operation sequence of the reference numbers with the S suffix is the same as that of the reference numbers without the S suffix, such as the operation sequence of P1/P1S and P2/P2S.

The rotary switch circuit 404 is composed of an excitation switch group 502 that controls an excitation signal and a sensing signal output switch group 504. The hall sensor 402 comprises a first port a, a second port b, a third port c and a fourth port d; the excitation switch group 502 includes: a first switch group P1 for forming an excitation signal loop at the first port a and the third port c, and a second switch group P2 for forming an excitation loop at the second port b and the fourth port d; a third switch group P3 for forming an excitation signal loop at the third port c and the first port a and a fourth switch group P4 for forming an excitation signal loop at the fourth port d and the second port b; the output switch set 504 includes: a first output switch group P1S for forming an output loop at the second port b and the fourth port d, a second output switch group P2S for forming an output loop at the third port c and the first port a; a third output switch group P3S for forming an output loop at the fourth port d and the second port, and a fourth switch group P4S for forming an output loop at the first port a and the third port c. And the first to fourth switch groups respectively comprise a switch connected with the excitation signal port and a switch to the ground. The specific connection mode of the excitation switch group 502 and the output switch group 504 with the switches is as follows: (for simplicity, only switch numbers are identified) the first port a is connected with P1, P3, P4S and P2S, the second port b is connected with P2, P4, P1S and P3S, the third port c is connected with P3, P1, P2S and P4S, and the fourth port d is connected with P4, P2, P3S and P1S.

The output switch group 504 of the rotary switch circuit 404 is connected to an output capacitor Cs, a first pole of the output capacitor Cs is a positive output terminal VOP of the rotary switch circuit 404, and a second pole of the output capacitor Cs is a negative output terminal VON of the rotary switch. The output capacitor Cs is used for sampling the output voltage generated by the hall sensor 402, and the output voltage Vo1 is the sum of the voltage Vh and the voltage Vos of the effective signal Vh of the hall sensor 402.

The rotary switch circuit 404 performs four-phase or two-phase excitation on the hall sensor 402 and receives signals through two other ports except for an excitation port under the action of the excitation switch group 502 and the output switch group 504 under the switch control timing. The following table is prepared according to the mapping relation of the phase, the excitation port and the direction, the sampling port and the direction, the signal direction and the offset voltage direction:

in the table, "+, -" indicates the direction of the hall voltage Vh and the offset voltage Vos, and "→" indicates the direction of the voltage of the excitation port or the output port.

Fig. 5 and 6 are clock signals generated by the synchronous clock signal generator 408, and control timings of the above-described switching components. The synchronous clock signal generator 408 generates a first clock C1 and a second clock C2, the clock C1 period of the second clock being twice the clock C2 period of the first clock. The activation process of the rotary switch circuit 404 is further described below with reference to a clock and control timing.

In FIG. 6, which shows the control timing of the two-phase rotary switch, the synchronous clock signal generator 408 generates the clock signal C1 and the clock signal inversion driving signal C1N. In the first clock period t1, the switches P1 and P1S are closed, the excitation port and the direction are a → c, the first port a and the third port c form an excitation loop, the output port and the direction are b → d, and the hall voltage Vh and the offset voltage Vos are both output in the positive direction. In the second clock period t2, the switches P1 and P1S are opened while the switches P2 and P2S are closed, the excitation port and direction is b → d, i.e. the second port b and the fourth port d form an excitation loop, the output port and direction is c → a, the hall voltage Vh is outputted in a positive direction and the offset voltage Vos is outputted in a negative direction.

It can be seen that the offset voltage Vos changes with the direction of the clock signal C1, and the signal is modulated into a high frequency signal with the same frequency as the clock signal, which is superimposed on the hall voltage Vh signal in the form of a square wave signal to form the rotary switch circuit output signal Vo1, and the high frequency signal is convenient for subsequent processing such as filtering.

In fig. 6, the switches P3, P4, P3S and P4S are always kept open, i.e., the excitation signals of the two phases c → a and d → b and the corresponding output signals are shielded by means of controlling the timing. In fig. 7, the four-phase rotary switch circuit 404 further includes the two-phase excitation signal and the corresponding output signal.

Four different timings are included in the four-phase rotary switch circuit 404. The timing of the activation of switch bank 502 and output switch bank 504 at the first clock cycle t1 and second clock cycle t2 is different from the timing of the operation of the two-phase rotary switch shown in fig. 3. In a third clock cycle t3 the P3, P3S are closed, with the stimulus port and direction c → a output port and direction d → b; the P4, P4S close the excitation port and direction d → b and the output port and direction a → c at four clock cycles t 4. It can be seen that the sign of the offset signal Vos output at the 4-phase rotary switch circuit 404 changes with the direction of the clock signal and is superimposed on the hall voltage Vh signal in a square wave signal to form the four-phase rotary switch circuit output signal Vo 1.

It should be noted that the two-phase rotary switch circuit or the four-phase rotary switch circuit has a certain time delay (as labeled d 1-d 4 in fig. 6 and 7) to the control timing of the excitation and output switch groups. The falling edges of the output switch groups P1S-P4S lead the corresponding excitations P1-P4 a bit and the rising edges lag the corresponding excitations P1-P4. Because the falling/rising edges of P1-P4 mean that the switch is in the switching process, and the output of the HALL is not established at this time, P1S-P4S has a dead time at the position corresponding to the edge of P1-P4, and the error caused by amplifying the output which is not established by the HALL by the later stage sampling is avoided. At the same time, the clock of the later stage ripple cancellation chopper amplifier needs to be aligned with the falling edge of P1S-P4S, so that the modulated Vh can be well suppressed by the ripple cancellation loop of the later stage amplifier.

Referring to fig. 4 and 8, positive and negative input ports (VIP, VIN) of the text wave cancellation chopper amplifier 406 are connected to positive and negative output ports (VOP, VON) of the rotary switch circuit 404, respectively. Text wave canceling chopper amplifier 406 includes a variety of implementations, and this application illustrates two exemplary implementations.

Fig. 8 shows a first implementation of dipleg canceling chopper amplifier 406. It comprises a first amplifier 802, a second amplifier 804 and a first negative feedback circuit 806 connected in series; the first amplifier 802 comprises a first transconductance amplifier GM1 and a first chopper Ch1 connected with the input end of the first transconductance amplifier GM1, the input end of the first chopper Ch1 is used as the input end of the diploe elimination chopper amplifier 406, and the chopper Ch1 is used for eliminating the offset voltage of the first transconductance amplifier GM 1.

The second amplifier 804 comprises a second transconductance amplifier GM2 and a second chopper Ch2 connected with the input end of the second transconductance amplifier GM 2; the input end of the second chopper Ch2 is connected with the output end of the first transconductance amplifier GM 1; an input terminal of the first negative feedback circuit 806 is connected to an output terminal of the second transconductance amplifier GM 2.

The first negative feedback circuit 806 is used to suppress the output of the second transconductance amplifier GM 2. The output end of the diplex cancellation loop RRL and the output end of the transconductance amplifier GMa connected to the diplex cancellation loop RRL are included as the first negative feedback circuit output end 806. The input end of the transconductance amplifier GMa is connected with the output end of the ripple wave eliminating loop RRL, and the ripple wave signal in the output signal collected by the text wave eliminating loop RRL is demodulated, amplified and negatively fed back to the output port of the first transconductance amplifier GM1 to suppress the output ripple wave.

In fig. 8, if the rotary switch circuit 404 performs four-phase sampling, the chopping text wave cancellation chopper amplifier 406 further comprises a second negative feedback circuit 808, an input end of the second negative feedback circuit 808 is connected with an output end of the second transconductance amplifier GM2, and an output end of the second negative feedback circuit 808 is connected with an input end of the second transconductance amplifier GM 2. The second negative feedback circuit 808 has the same structure as the first negative feedback circuit 806, and the output end of the second negative feedback circuit 808 is connected with the input end of a third chopper Ch3, and the output end of the third chopper Ch3 is connected with the input end of a second-stage transconductance amplifier GM 2.

For the four-phase rotary switch circuit, the first clock C1 and the first clock inversion signal C1N drive the first chopper Ch1 and the second chopper Ch2, and the second clock signal C2 has twice the clock cycle of the first clock signal C1 and drives the third chopper. So that the dipleg cancellation path of the second negative feedback circuit 808 can effectively suppress the ripple at one-half of the rotation frequency. For a two-phase rotary switch circuit, the second negative feedback circuit 808 may be removed or electrically turned off.

Referring to fig. 9, several typical implementations of the RRL are listed, and the RRL has a common feature that the RRL mainly includes a chopper and an integrator, the chopper can demodulate the ripple in the output signal back to DC, the ripple is amplified by the integrator and fed back to the signal path, and the RRL can suppress the output ripple of the amplifier to be negligible relative to the hall signal through negative feedback.

With continued reference to fig. 9, first venturi cancellation loop 902 includes a chopper ch connected to an input of integrator Int and integrator Int. The second loop 904 adds a preamplifier GM2, the output of which is connected to the input of said chopper Ch, on the basis of the first loop RRL.

For the first ripple cancellation loop 902, whose residual ripple is determined by the offset voltage of the amplifier in the integrator Int, a pre-amplifier GM2 is added before the chopper Ch, which can further reduce the ripple and suppress it by the gain of the pre-amplifier GM2 at the chopping frequency.

The third dipleg elimination loop 906 adds a high pass filter HPF to the second dipleg elimination loop 904, the high pass filter HPF being connected to the preamplifier GM2 input. The high pass filter HPF is an RC structure as shown in the figure. The high pass filter HPF may allow the high frequency text wave signal to pass through and block the hall signal Vh before the preamplifier so that the RRL processes the hall signal Vh less, only the ripple. For the hall signal Vh, since its frequency is lower than the chopping frequency, modulated by the chopper ch to the chopping frequency, and suppressed by the low-pass characteristic of the integrator Int while passing through the integrator, the RRL does not feed back the useful hall signal Vh, but feeds back only the ripple and suppresses the ripple.

Fourth dipleg elimination loop 908 dipleg elimination loop includes chopper Ch, transconductance amplifier GM1, and transconductance integrator Int ', the output terminal of chopper Ch being connected to the input terminal of the transconductance amplifier, and the output terminal of transconductance amplifier GM1 being connected to the input terminal of the transconductance integrator Int'.

The fifth dipleg canceling loop 910 comprises a chopper Ch, a transconductance amplifier GM1 and a transconductance integrator Int ', an input terminal of the chopper Ch being connected to an output terminal of the transconductance amplifier GM1, and an output terminal of the chopper Ch being connected to an input terminal of the transconductance integrator Int'. Chopper Ch of fifth dipleg cancellation loop 910 may be moved from the input across to the amplifier to the output, helping to reduce the residual ripple amplitude.

Referring to the implementation of the chopper shown in fig. 10, which includes a first switch group S1 connected to the input and output terminals in the forward direction and a second switch group S2 connected to the output and output terminals in the reverse direction, the first switch group drives the clock source to be C1 or C2, and correspondingly the second switch group drives the clock source to be C1N or C2N, and the chopper switching output signal is continuously commutated with the clock signal.

Fig. 11 shows a second implementation of the chopper amplifier 406 for removing text waves, wherein the implementation of the chopper and the text wave removal loop RRL is the same as the implementation of the first chopper amplifier 406 for removing text waves.

The diploe canceling chopper amplifier 406 includes a differential amplifier formed by a first operational amplifier OPAMP1 and a second operational amplifier OPAMP2, and a diploe canceling loop RRL. The output ends of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are connected with three resistors (R1, R2 and R3) in series; the input end of the first operational amplifier OPAMP1 is connected with a second resistor R2, and the input end of the second operational amplifier OPAMP2 is connected with a third resistor R3; the first operational amplifier OPAMP1 or the second operational amplifier OPAMP2 includes a first feedback port VIP1/VIN1, a positive input VIP1 and a negative input VIN1 of the first feedback port VIP1/VIN1 are connected to a positive output VOP and a negative output VON of a venturi cancellation loop RRL, respectively, the positive input VIP and the negative input VIN of the venturi cancellation loop RRL being connected to the outputs of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP 2.

The operational amplifiers (OPAMP1/OPAMP1) described with reference to FIG. 12 include a first amplifier 1202, a second amplifier 1204, and a first degeneration transconductance amplifier GMa; the first amplifier 1202 comprises a first transconductance amplifier GM1 and a first chopper Ch1 connected with the input end of the first transconductance amplifier GM1, and the second amplifier 1204 comprises a second transconductance amplifier GM2 and a second chopper Ch2 connected with the input end of the second transconductance amplifier GMb; the input end of the first chopper Ch1 is used as the input end of an operational amplifier, and the input end of the second chopper Ch2 is connected with the output end of the first transconductance amplifier GM 1; the input end of the first negative feedback transconductance amplifier Gma is connected with the first feedback port VIP1/VIN2 of the operational amplifier, and the output end of the first negative feedback transconductance amplifier Gma is connected with the output end of the first transconductance amplifier GM 1.

Referring to fig. 11 and 2 if the rotary switch circuit is 4-phase driven, the operational amplifier further comprises an output connection of an venturi cancellation loop RRL 'connected to the second feedback port VIP2/VIN2, an input of the venturi cancellation loop RRL' being connected to the outputs of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP 2. Correspondingly, a second negative feedback transconductance amplifier GMb connected with the second feedback port VIP2/VIN2 at the internal input terminal of the operational amplifier, the second negative feedback transconductance amplifier GMb is connected with the input terminal of the second transconductance amplifier Gmb through a third chopper Ch 3; a first clock C1 and a first clock inversion signal C1N drive the first chopper Ch1 and a second chopper Ch 2; the second clock C2 and the second clock inverted signal C2N drive the third chopper Ch 3. The dipleg cancellation loop RRL', the second transconductance amplifier Gmb, and the third chopper Ch3 may be electrically shielded or deleted from the circuit if the rotary switch circuit is 2-phase excited.

In summary, the present invention cooperates with the rotating switch circuit and the switching clock and clock edge of the post-stage ripple cancellation chopper amplifier, and the ripple cancellation loop in the post-stage ripple cancellation chopper amplifier is used to cancel the offset voltage modulated by the hall element. The two-phase rotary switch circuit and the four-phase rotary switch circuit can be compatible through a reasonable switching sequence. Through 2 loops, ripples at the rotating frequency and at the half position of the rotating frequency are respectively suppressed, and ripples caused by four-phase rotation can be effectively eliminated.

According to the invention, a low-pass or high-order low-pass filter with low cut-off frequency is not added in a signal path, a switch sampling circuit is not added, the bandwidth and delay time of the signal path are not influenced, and the noise aliasing effect caused by switch sampling is avoided, so that the high bandwidth, the high response speed, the high measurement precision, the small noise and the small offset voltage are realized. The measurement precision and the delay time are short enough, and when the detected system current is over-current, the system can quickly receive an over-current signal and start protective measures to protect the safety of the whole system.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims

1. A hall sensing circuit, comprising: a Hall sensor and a synchronous clock signal generator;

the rotary switch circuit is characterized in that the rotary switch circuit simultaneously outputs the output voltage of the Hall sensor to the chopper amplifier for eliminating the Weak wave; the text wave elimination chopper amplifier and the rotary switch circuit use a synchronous clock signal generator as a clock signal source.

2. The hall sensing circuit of claim 1 wherein the rotary switch circuit comprises an excitation switch set and an output switch set, and wherein the hall sensor comprises a first port, a second port, a third port, and a fourth port; the excitation switch group includes: the first switch group is used for forming an excitation signal loop at the first port and the third port, and the second switch group is used for forming an excitation loop at the second port and the fourth port; the output switch group includes: the first output switch group is used for forming an output loop at the second port and the fourth port, and the second output switch group is used for forming an output loop at the third port and the first port.

3. The hall sensing circuit of claim 2 wherein the set of excitation switches comprises: a third switch set for forming an excitation signal loop at the third port and the first port and a fourth switch set for forming an excitation signal loop at the fourth port and the second port; the output switch group includes: a third output switch set for forming an output loop at the fourth port and the second port and for forming an output loop at the first port and the third port.

4. The Hall sensing circuit according to claim 2 or claim 3, wherein the output switch set of the rotary switch circuit is connected to an output capacitor, a first pole of the output capacitor is a positive output terminal of the rotary switch circuit, and a second pole of the output capacitor is a negative output terminal of the rotary switch circuit.

5. The hall sensing circuit of claim 1 wherein the chopping amplifier comprises, in series, a first amplifier, a second amplifier, and a first negative feedback circuit; the first amplifier is a chopper amplifier and comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier; the input end of the first chopper is used as the input end of the chopping amplifier for eliminating the text wave, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback circuit is connected with the output end of the second transconductance amplifier, and the output end of the first negative feedback circuit is connected with the output end of the first transconductance amplifier and used for eliminating the output end diplonic signal of the first transconductance amplifier.

6. The Hall sensing circuit according to claim 5, wherein the chopping amplifier for eliminating the Weathering wave comprises a second negative feedback circuit, an input end of the second negative feedback circuit is connected with an output end of the second transconductance amplifier; the output end of the second negative feedback circuit is connected with the input end of the second transconductance amplifier and is used for eliminating the diploe signal at the input end of the second transconductance amplifier.

7. The Hall sensing circuit according to claim 6, wherein said second negative feedback circuit is connected to an input terminal of a second transconductance amplifier through a third chopper; the synchronous clock signal generator generates a first clock and a second clock, and the clock period of the second clock is twice that of the first clock; the first clock and the first clock inverted signal drive the first chopper and the second chopper; the second clock and the second clock inverted signal drive the third chopper.

8. The Hall sensing circuit according to claim 7, wherein said first or second negative feedback circuit comprises an dipleg canceling loop and a transconductance amplifier connected to said dipleg canceling loop, an output of said transconductance amplifier serving as an output of said first or second negative feedback circuit.

9. The hall sensing circuit of claim 1 wherein the chopping amplifier comprises a differential amplifier consisting of a first operational amplifier and a second operational amplifier and an westerncancellation loop; the output ends of the first operational amplifier and the second operational amplifier are connected with three resistors in series; the input end of the first operational amplifier is connected with the second resistor, and the input end of the second operational amplifier is connected with the third resistor; the first operational amplifier or the second operational amplifier comprises a first feedback port, the first feedback port is connected with the output end of the acoustic wave elimination loop, and the input end of the acoustic wave elimination loop is connected with the output ends of the first operational amplifier and the second operational amplifier.

10. The hall sensing circuit of claim 9 wherein the operational amplifier comprises a first amplifier, a second amplifier and a first negative feedback transconductance amplifier; the first amplifier is a chopper amplifier and comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier; the input end of the first chopper is used as the input end of an operational amplifier, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback transconductance amplifier is connected with the first feedback port of the operational amplifier, and the output end of the first negative feedback transconductance amplifier is connected with the output end of the first transconductance amplifier.

11. A hall sensing circuit according to claim 10, the first or second operational amplifier including a second feedback port, the second feedback port being connected to the output of the cancellation loop, the input of the cancellation loop being connected to the outputs of the first and second operational amplifiers.

12. The hall sensing circuit of claim 11 wherein the operational amplifier comprises a second negative feedback transconductance amplifier having an input connected to the second feedback port, the second negative feedback transconductance amplifier being connected to the input of the second transconductance amplifier via a third chopper; the synchronous clock signal generator generates a first clock and a second clock, and the clock period of the second clock is twice that of the first clock; the first clock and the first clock inverted signal drive the first chopper and the second chopper; the second clock and the second clock inverted signal drive the third chopper.

13. The hall sensing circuit of any one of claims 8 to 12 wherein the loop for removing the cultural waves comprises a chopper and an integrator, the chopper being connected to the input of the integrator.

14. The hall sensing circuit of claim 13 wherein the loop for removing the evanescent wave comprises a preamplifier having an output connected to an input of the chopper.

15. The hall sensing circuit of claim 14 wherein the dither circuit includes a high pass filter coupled to the preamplifier input.

16. The hall sensing circuit of any one of claims 8 to 12 wherein the dipleg cancellation loop comprises a chopper, a transconductance amplifier and a transconductance integrator, an output of the chopper being connected to an input of the transconductance amplifier, and an output of the transconductance amplifier being connected to an input of the transconductance integrator.

17. A hall sensing circuit as claimed in any one of claims 8 to 12, wherein the loop comprises a chopper, a transconductance amplifier and a transconductance integrator, an input terminal of the chopper being connected to an output terminal of the transconductance amplifier, and an output terminal of the chopper being connected to an input terminal of the transconductance integrator.