CN115579348A - Adapter plate structure and preparation method thereof - Google Patents
Adapter plate structure and preparation method thereof Download PDFInfo
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- CN115579348A CN115579348A CN202211318454.4A CN202211318454A CN115579348A CN 115579348 A CN115579348 A CN 115579348A CN 202211318454 A CN202211318454 A CN 202211318454A CN 115579348 A CN115579348 A CN 115579348A
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H01—ELECTRIC ELEMENTS
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Abstract
The invention provides an adapter plate structure and a preparation method thereof, wherein the adapter plate structure comprises: a substrate layer; a trench structure located in the partial thickness substrate layer; the groove structure comprises a first circle of continuous grooves to an Nth circle of continuous grooves which are distributed from the center of the groove structure to the edge of the side part of the groove structure, and N is an integer which is greater than or equal to 2; the lower electrode film covers the inner walls of the first circle of grooves to the Nth circle of grooves; the capacitor dielectric film is positioned on the surface of one side, away from the inner wall of the groove structure, of the lower electrode film; the upper electrode film is positioned on the surface of one side of the capacitor dielectric film, which is far away from the lower electrode film; and the inductance structure is positioned in the first-turn groove to the Nth-turn groove, and the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film. The adapter plate structure provided by the invention can improve the integration level of the adapter plate structure, reduce the dielectric loss and improve the quality factor of the inductance structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an adapter plate structure and a preparation method thereof.
Background
In recent years, capacitors are indispensable elements in microwave rf circuits, and have functions such as dc isolation, filtering, coupling, tuning, and rectification. As integrated circuits operate at higher and higher frequencies and at higher and higher speeds, the need for high density capacitors and low parasitic inductance capacitors has increased. With the rapid development of the wireless communication market, the demand for low-cost and high-performance on-chip rf devices is increasing, and in order to meet the requirements of low loss and high integration, on-chip integrated inductors have become important components in many communication modules, such as voltage-controlled oscillators, low-noise amplifiers, mixers, and filters.
The structure of the transfer board in the prior art includes a capacitor structure formed by the sidewall of the hole-type trench and an inductor structure in a spiral shape. This results in a low integration level and a high dielectric loss of the interposer structure, and the planar spiral inductor structure also results in a low quality factor of the inductor structure.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defects of low integration level, high dielectric loss and small quality factor of the inductor structure of the interposer in the prior art, so as to provide an interposer structure and a manufacturing method thereof.
The invention provides an adapter plate structure, comprising: a substrate layer; a trench structure in the substrate layer of partial thickness; the groove structure comprises a first ring of continuous grooves to an Nth ring of continuous grooves which are distributed from the center of the groove structure to the side edge of the groove structure, and N is an integer greater than or equal to 2; the lower electrode film covers the inner walls of the first circle of grooves to the Nth circle of grooves; the capacitor dielectric film is positioned on the surface of one side, away from the inner wall of the groove structure, of the lower electrode film; the upper electrode film is positioned on the surface of one side, away from the lower electrode film, of the capacitor dielectric film; and the inductance structure is positioned in the first-turn groove to the Nth-turn groove, and the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film.
Optionally, the method further includes: a first conductive member and a second conductive member both penetrating the substrate layer, the first conductive member and the second conductive member being located at a side portion of the trench structure and spaced apart from the trench structure; a first rewiring layer and a second rewiring layer on a side of the substrate layer having a trench structure, the first rewiring layer being electrically connected to the lower electrode film and the first conductive member, the second rewiring layer being electrically connected to the upper electrode film and the second conductive member; the first rewiring layer is electrically connected with the inductance structure in the first ring of grooves, and the second rewiring layer is electrically connected with the inductance structure in the Nth ring of grooves; or, the first redistribution layer is electrically connected with the inductance structure in the nth groove, and the second redistribution layer is electrically connected with the inductance structure in the first groove.
Optionally, the method further includes: and the third redistribution structure is positioned on one side of the substrate layer, the first conductive piece and the second conductive piece, which is far away from the first redistribution layer.
Optionally, the substrate layer has a first through hole and a second through hole; the first conductive member is located in the first through hole, and the second conductive member is located in the second through hole.
Optionally, the method further includes: a first insulating layer located between the lower electrode film and an inner wall surface of the trench structure; and the second insulating layers are positioned between the inductance structure and the upper electrode film, between the inner wall of the first through hole and the first conductive piece and between the inner wall of the second through hole and the second conductive piece.
Optionally, the first insulating layer further covers a top surface of a substrate layer between the first to nth turn trenches, a top surface of the substrate layer between the nth turn trench and the first via, and a top surface of the substrate layer between the nth turn trench and the second via; the lower electrode film further extends to an upper surface of the substrate layer away from the first insulating layer; the capacitor dielectric film also extends to an upper surface of the lower electrode film facing away from a top surface of the substrate layer; the upper electrode film also extends to an upper surface of the capacitor dielectric film facing away from a top surface of the substrate layer; the second insulating layer also extends to an upper surface of the upper electrode film facing away from a top surface of the substrate layer.
Optionally, the method further includes: the first connecting pieces are located between the first redistribution layer and the inductor structure, between the first redistribution layer and the lower electrode film, and between the first redistribution layer and the first conductive piece, and the second connecting pieces are located between the second redistribution layer and the upper electrode film, between the second redistribution layer and the inductor structure, and between the second redistribution layer and the second conductive piece.
The invention also provides a preparation method of the adapter plate structure, which comprises the following steps: providing a substrate layer; forming a trench structure in the substrate layer of a partial thickness; the groove structure comprises a first ring of continuous grooves to an Nth ring of continuous grooves which are distributed from the center of the groove structure to the side edge of the groove structure, and N is an integer greater than or equal to 2; forming a lower electrode film on the inner walls of the first circle of grooves to the Nth circle of grooves; forming a capacitor dielectric film on the surface of one side, away from the inner wall of the groove structure, of the lower electrode film; forming an upper electrode film on the surface of one side of the capacitor dielectric film, which is far away from the lower electrode film; and forming an inductance structure in the first-Nth circles of grooves, wherein the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film.
Optionally, the method further includes: after forming the upper electrode film, forming a first through hole and a second through hole in the substrate layer, wherein the first through hole and the second through hole are positioned at the side part of the groove structure and are spaced from the groove structure; forming a first conductive member in the first via hole and a second conductive member in the second via hole; forming a first rewiring layer and a second rewiring layer on one side of the substrate layer having a trench structure, the first rewiring layer being electrically connected to the lower electrode film and the first conductive member, the second rewiring layer being electrically connected to the upper electrode film and the second conductive member; the first rewiring layer is electrically connected with the inductance structure in the first ring of grooves, and the second rewiring layer is electrically connected with the inductance structure in the Nth ring of grooves; or, the first redistribution layer is electrically connected with the inductance structure in the nth groove, and the second redistribution layer is electrically connected with the inductance structure in the first groove.
Optionally, the first conductive member and the second conductive member are formed at the same time as the inductor structure is formed.
Optionally, the method further includes: after forming the first and second redistribution layers, a third redistribution structure is formed on a side of the substrate layer, the first conductive member, and the second conductive member facing away from the first redistribution layer.
Optionally, the method further includes: and before forming the lower electrode film on the inner walls of the first-turn grooves to the Nth-turn grooves, forming a first insulating layer on the inner wall surface of the groove structure.
Optionally, the method further includes: before forming the first conductive piece, the second conductive piece and the inductance structure, forming a second insulating layer on the surface of one side of the upper electrode film, which is far away from the capacitance dielectric film, and the inner wall surfaces of the first through hole and the second through hole.
The invention has the beneficial effects that:
the technical scheme of the invention provides an adapter plate structure, wherein a groove structure is arranged in a substrate layer with partial thickness, a lower electrode film, a capacitor dielectric film and an upper electrode film are positioned in the groove structure, and the lower electrode film, the capacitor dielectric film and the upper electrode film form the capacitor structure. Because the capacitor structure is a groove type capacitor, the lower electrode film covers the inner walls of the first circle of groove to the Nth circle of groove, the upper electrode film is positioned on the surface of one side of the capacitor dielectric film, which is far away from the lower electrode film, and the area of the lower electrode film opposite to the upper electrode film is larger, so that the capacitor density of the capacitor structure is improved. Secondly, the inductance structure is also located in the groove structure, the surrounding direction of the inductance structure is consistent with the surrounding direction from the first circle of grooves to the Nth circle of grooves, and the longitudinal space of the groove structure is fully utilized by the inductance structure, so that the planar area occupied by the inductance structure can be reduced, and the integration level of the inductance structure is improved. And secondly, the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film, a lower electrode film and an upper electrode film are arranged between the inductance structure and the substrate layer, and the lower electrode film and the upper electrode film are utilized to improve the isolation between the inductance structure and the substrate layer, so that the dielectric loss of the capacitor dielectric film is reduced. In conclusion, the integration level of the adapter plate structure is improved and the dielectric loss is reduced. And thirdly, the longitudinal space of the groove structure is fully utilized by the inductance structure, so that the size of the inductance structure in the longitudinal direction is larger, and the quality factor of the inductance structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a cross-sectional view of a transfer plate structure in example 1 of the present invention;
FIG. 2 is a top view of the adapter plate structure of FIG. 1;
FIG. 3 is a schematic flow chart of a method for manufacturing a transfer board structure according to embodiment 2 of the present invention;
fig. 4 to 14 are schematic structural views illustrating a process of manufacturing a transfer sheet structure in example 2 of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
Referring to fig. 1 and 2, fig. 1 is a cross-sectional view taken along a cutting line M-N in fig. 2, and this embodiment provides an interposer structure, including: a substrate layer 1; a trench structure 2 (refer to fig. 3) located in a partial thickness of the substrate layer 1; the groove structure 2 comprises a first circle of continuous grooves to an Nth circle of continuous grooves which are arranged from the center of the groove structure 2 to the side edge of the groove structure 2; the lower electrode film 4 covers the inner walls of the first circle of grooves to the Nth circle of grooves; the capacitor dielectric film 5 is positioned on the surface of one side, away from the inner wall of the groove structure 2, of the lower electrode film 4; the upper electrode film 6 is positioned on the surface of one side of the capacitor dielectric film 5, which is far away from the lower electrode film 4; and the inductance structure 8 is positioned in the first-turn groove to the Nth-turn groove, and the side wall and the bottom surface of the inductance structure 8 are surrounded by the upper electrode film 6. N is an integer greater than or equal to 2.
In this embodiment, the substrate layer 1 having a partial thickness has a trench structure 2 therein, the lower electrode film 4, the capacitor dielectric film 5 and the upper electrode film 6 are located in the trench structure 2, and the lower electrode film 4, the capacitor dielectric film 5 and the upper electrode film 6 constitute a capacitor structure. Because the capacitor structure is a trench capacitor, the lower electrode film 4 covers the inner walls of the first to nth circles of trenches, the upper electrode film 6 is positioned on the surface of one side of the capacitor dielectric film 5 departing from the lower electrode film 4, and the area of the lower electrode film 4 opposite to the upper electrode film 6 is larger, so that the capacitor density of the capacitor structure is improved. Secondly, inductance structure 8 also is located in the groove structure, inductance structure 8's the direction of encircleing is unanimous with the direction of encircleing of first round slot to nth circle slot, and inductance structure 8 is abundant has utilized the longitudinal space of groove structure to can reduce the plane area that inductance structure 8 occupies, improve inductance structure 8's integrated level. Secondly, the side wall and the bottom surface of the inductance structure 8 are surrounded by the upper electrode film 6, a lower electrode film 4 and an upper electrode film 6 are arranged between the inductance structure 8 and the substrate layer 1, and the lower electrode film 4 and the upper electrode film 6 are utilized to improve the isolation between the inductance structure 8 and the substrate layer 1, so that the dielectric loss of the capacitor dielectric film 5 is reduced. In conclusion, the integration level of the adapter plate structure is improved and the dielectric loss is reduced. Thirdly, the longitudinal space of the trench structure 2 is fully utilized by the inductance structure 8, so that the size of the inductance structure 8 in the longitudinal direction is larger, and the quality factor of the inductance structure 8 is improved.
In one embodiment, the substrate layer 1 comprises a semiconductor substrate layer, such as a silicon substrate layer.
In one embodiment, the number of the trench structures in the substrate layer 1 is one, and in another embodiment, the number of the trench structures in the substrate layer is several.
Each groove structure comprises a first circle of continuous grooves to an Nth circle of continuous grooves, the first circle of grooves are grooves at the innermost circle of the groove structure, and the Nth circle of grooves are grooves at the outermost circle of the groove structure. Referring to fig. 2, the groove structure includes a continuous first turn of grooves to a second turn of grooves, N being equal to 2. It should be noted that in other embodiments, N may be selected from other values.
For the lower electrode film 4 in any one of the trench structures, the lower electrode film 4 in the first to nth trenches is connected; for the upper electrode film 6 in any one of the trench structures, the upper electrode film 6 in the first to nth turn trenches is connected. Referring to fig. 2, for any one of the trench structures, the lower electrode film 4 in the first-turn trench to the second-turn trench is connected, and the upper electrode film 6 in the first-turn trench to the second-turn trench is connected.
In one embodiment, the thickness of the lower electrode film 4 is 0.2um to 2um, such as 0.2um, 1.0um, 1.5um, or 2um; the thickness of the upper electrode film 6 is 0.2um to 2um, such as 0.2um, 1.0um, 1.5um or 2um; the thickness of the capacitor dielectric film 5 is 30nm to 300nm, for example, 30nm, 100nm, 200nm or 300nm.
The material of the lower electrode film 4 includes copper, titanium nitride, or polysilicon.
The material of the upper electrode film 6 includes copper, titanium nitride, or polysilicon.
The material of the capacitor dielectric film 5 comprises silicon oxide, silicon nitride, aluminum oxide or hafnium oxide.
The adapter plate structure further comprises: a first conductive member 7A and a second conductive member 7B, both extending through the substrate layer 1, the first conductive member 7A and the second conductive member 7B being located at a side portion of the trench structure and spaced apart from the trench structure; a first redistribution layer 10A and a second redistribution layer 10B on a side of the substrate layer 1 having a trench structure, the first redistribution layer 10A being electrically connected to the lower electrode film 4 and the first conductive member 7A, the second redistribution layer 10B being electrically connected to the upper electrode film 6 and the second conductive member 7B.
In this embodiment, the first redistribution layer 10A is electrically connected to the inductance structure 8 in the nth turn of trench, and the second redistribution layer 10B is electrically connected to the inductance structure 8 in the first turn of trench.
In other embodiments, the first redistribution layer is electrically connected to the inductive structure in the first turn of trench, and the second redistribution layer is electrically connected to the inductive structure in the nth turn of trench.
The first and second redistribution layers 10A and 10B may be in different layers, or the first and second redistribution layers 10A and 10B may be in the same layer and disposed at an interval. The inductance structure 8 and the lower electrode film 4 are electrically connected to the first conductive member 7A through the first rewiring layer 10A. The upper electrode film 6 is electrically connected to the second conductive member 7B through the second rewiring layer 10B. The voltage applied to the first conductive member 7A is different from the voltage applied to the second conductive member 7B.
The adapter plate structure further comprises: and a third redistribution structure 11 located on a side of the substrate layer 1, the first conductive member 7A, and the second conductive member 7B facing away from the first redistribution layer 10A. The adapter plate structure further comprises: and the first solder balls 9A and the second solder balls 9B are positioned on the side, away from the substrate layer 1, of the third heavy wiring structure 11.
The first solder ball 9A and the second solder ball 9B are electrically connected to the third heavy wiring structure 11.
The third redistribution structure 11 includes a third dielectric layer and a third redistribution layer located in the third dielectric layer, where the number of layers of the third dielectric layer may be one or several, and correspondingly, the number of layers of the third redistribution layer may be one or several. In this embodiment, the number of layers of the third dielectric layer is one, and the number of layers of the third redistribution layer is one. It should be noted that, in other embodiments, the number of layers of the third dielectric layer may be several, and the number of layers of the third redistribution layer may be several.
The first solder ball 9A is electrically connected to the first conductive member 7A through a part of the third re-wiring, and the second solder ball 9B is electrically connected to the second conductive member 7B through a part of the third re-wiring. The third re-wiring electrically connected to the first conductive member 7A and the third re-wiring electrically connected to the second conductive member 7B may be provided in different layers, or the third re-wiring electrically connected to the first conductive member 7A and the third re-wiring electrically connected to the second conductive member 7B may be provided in the same layer and spaced apart.
The substrate layer 1 is provided with a first through hole and a second through hole; the first conductive member 7A is located in the first through hole, and the second conductive member 7B is located in the second through hole.
The first through hole and the second through hole both penetrate through the substrate layer 1, and the first through hole and the second through hole are located on the side portion of the groove structure and spaced apart from the groove structure.
In one embodiment, the depth of the first through hole is 50um to 300um, such as 50um, 100um, 200um or 300um; the depth of the second through hole is 50 um-300 um, for example 50um, 100um, 200um or 300um.
The adapter plate structure further comprises: a first insulating layer 31 located between the lower electrode film 4 and an inner wall surface of the trench structure; and a second insulating layer 32 between the inductance structure 8 and the upper electrode film 6, between an inner wall of the first via hole and the first conductive member 7A, and between an inner wall of the second via hole and the second conductive member 7B.
In one embodiment, the thickness of the first insulating layer 31 is 0.1um to 0.5um, such as 0.1um, 0.2um, or 0.5um; the thickness of the second insulating layer 32 is 0.1um to 0.5um, for example, 0.1um, 0.2um or 0.5um.
The material of the first insulating layer 31 includes silicon oxide and silicon nitride; the material of the second insulating layer 32 includes silicon oxide and silicon nitride.
The first insulating layer 31 also covers the top surface of the substrate layer 1 between the first to nth turn grooves, the top surface of the substrate layer 1 between the nth turn groove and the first through hole, and the top surface of the substrate layer 1 between the nth turn groove and the second through hole; the first insulating layer 31 of the lower electrode film 4 extending to the top surface of the substrate layer 1 faces away from the upper surface of the substrate layer 1; the capacitor dielectric film 5 also extends to the upper surface of the lower electrode film 4 facing away from the top surface of the substrate layer 1; the upper electrode film 6 also extends to the upper surface of the capacitor dielectric film 5 facing away from the top surface of the substrate layer 1; the second insulating layer 32 also extends to the upper surface of the upper electrode film 6 facing away from the top surface of the substrate layer 1.
The adapter plate structure further comprises: first connecting members and second connecting members, the first connecting members being located between the first rewiring layer 10A and the inductance structure 8, between the first rewiring layer 10A and the lower electrode film 4, and between the first rewiring layer 10A and the first conductive member 7A, the second connecting members being located between the second rewiring layer 10B and the upper electrode film 6, between the second rewiring layer 10B and the inductance structure 8, and between the second rewiring layer 10B and the second conductive member 7B.
In one embodiment, the material of the first connector includes copper; the material of the second connecting member includes copper or aluminum.
In one embodiment, the longitudinal dimension of the inductive structure 8 is 100um to 1000um, such as 100um, 260um, 680um or 1000um.
Note that, in the plan view in fig. 2, for better illustration, the portions of the capacitor dielectric film 5, the upper electrode film 6, the lower electrode film 4, the first insulating layer 31, and the second insulating layer 32 above the tops of the substrate layers are not drawn, but film layers in the trench structure are shown with emphasis.
Example 2
Referring to fig. 3, the present embodiment provides a method for manufacturing an adapter plate structure, including the following steps:
step S1: providing a substrate layer;
step S2: forming a trench structure in the substrate layer of a partial thickness; the groove structure comprises a first circle of continuous grooves to an Nth circle of continuous grooves which are distributed from the center of the groove structure to the edge of the side part of the groove structure, and N is an integer which is greater than or equal to 2;
and step S3: forming a lower electrode film on the inner walls of the first circle of grooves to the Nth circle of grooves;
and step S4: forming a capacitor dielectric film on the surface of one side, away from the inner wall of the groove structure, of the lower electrode film;
step S5: forming an upper electrode film on the surface of one side of the capacitor dielectric film, which is far away from the lower electrode film;
step S6: and forming an inductance structure in the first-Nth circles of grooves, wherein the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film.
The process of the method for manufacturing the adapter plate structure will be described in detail with reference to fig. 4 to 14.
With combined reference to fig. 4 and 5, fig. 5 is a top view corresponding to fig. 4, providing a substrate layer 1; a groove structure 2 is formed in the substrate layer 1 with partial thickness, and the groove structure 2 comprises a first circle of continuous grooves to an Nth circle of continuous grooves which are arranged from the center of the groove structure 2 to the side edge of the groove structure 2.
The forming method of the trench structure 2 includes an etching process.
Referring to fig. 6 in combination, a first insulating layer 31 is formed on the inner wall surface of the trench structure 2.
The material of the first insulating layer 31 includes silicon oxide or silicon nitride.
The forming method of the first insulating layer 31 includes a deposition process.
The first insulating layer 31 is also located on the top surface of the substrate layer between the first to nth grooves, the top surface of the substrate layer between the nth groove and the first through hole, and the top surface of the substrate layer between the nth groove and the second through hole.
In one embodiment, the thickness of the first insulating layer 31 is 0.1um to 0.5um, such as 0.1um, 0.2um, or 0.5um. If the thickness of the first insulating layer 31 is too small, the degree of improvement in the insulation between the substrate layer 1 and the lower electrode film 4 by the first insulating layer 31 is small; if the thickness of the first insulating layer 31 is too large and the space for forming the inductor structure 8 is too small, the effect of improving the integration level of the interposer structure is reduced.
Referring to fig. 7, a lower electrode film 4 is formed on the inner walls of the first to nth turn trenches.
After the first insulating layer 31 is formed, the lower electrode film 4 is formed. The lower electrode film 4 also extends to the top surface of the substrate layer 1, and the first insulating layer 31 faces away from the upper surface of the substrate layer 1.
In one embodiment, the thickness of the lower electrode film 4 is 0.2um to 2um, such as 0.2um, 1.0um, 1.5um, or 2um.
The material of the lower electrode film 4 includes copper, titanium nitride, or polysilicon.
Referring to fig. 8, a capacitor dielectric film 5 is formed on a surface of the lower electrode film 4 on a side away from the inner wall of the trench structure 2.
After the lower electrode film 4 is formed, the capacitor dielectric film 5 is formed. The capacitor dielectric film 5 also extends to the upper surface of the lower electrode film 4 facing away from the top surface of the substrate layer 1.
In one embodiment, the thickness of the capacitor dielectric film 5 is 30nm to 300nm, such as 35nm, 100nm, 200nm or 300nm.
The material of the capacitor dielectric film 5 comprises silicon oxide, silicon nitride, aluminum oxide or hafnium oxide.
In one embodiment, the dielectric constant of the capacitor dielectric film 5 is 4 to 30, such as 4.1, 7, or 20.
Referring to fig. 9, an upper electrode film 6 is formed on a surface of the capacitor dielectric film 5 on a side away from the lower electrode film 4.
After the capacitor dielectric film 5 is formed, the upper electrode film 6 is formed. The upper electrode film 6 also extends to the upper surface of the capacitor dielectric film 5 facing away from the top surface of the substrate layer 1.
In one embodiment, the upper electrode film 6 has a thickness of 0.2um to 2um, such as 0.2um, 1.0um, 1.5um, or 2um.
The material of the upper electrode film 6 includes copper, titanium nitride, or polysilicon.
Referring to fig. 10, a first via hole 71 and a second via hole 72 are formed in the substrate layer 1.
After the upper electrode film 6 is formed, a first via hole 71 and a second via hole 72 are formed in the substrate layer 1. The first via 71 and the second via 72 are both located at the side of the trench structure and spaced from the trench structure.
The first and second through holes 71 and 72 penetrate through the substrate layer 1.
Referring to fig. 11, a second insulating layer 32 is formed on a surface of the upper electrode film 6 on a side away from the capacitor dielectric film 5 and inner wall surfaces of the first through hole 71 and the second through hole 72.
After the first via hole 71 and the second via hole 72 are formed, the second insulating layer 32 is formed. The second insulating layer 32 also extends to the upper surface of the upper electrode film 6 facing away from the top surface of the substrate layer 1.
The material of the second insulating layer 32 includes silicon oxide or silicon nitride. .
The method of forming the second insulating layer 32 includes a deposition process.
In one embodiment, the thickness of the second insulating layer 32 is 0.1um to 0.5um, such as 0.1um, 0.2um, or 0.5um. If the thickness of the second insulating layer 32 is too small, the second insulating layer 32 increases the insulation degree between the substrate layer 1 and the first conductive member 7A, between the substrate layer 1 and the second conductive member 7B, and between the upper electrode film 6 and the inductance structure 8 to be small; if the thickness of the second insulating layer 32 is too large and the space for forming the inductance structure 8 is too small, the effect of improving the integration level of the interposer structure is weakened.
Referring to fig. 12, an inductance structure 8 is formed in the first to nth turn trenches; a first conductive member is formed in the first via hole, and a second conductive member is formed in the second via hole.
After forming the second insulating layer 32, the inductance structure 8, the first conductive member 7A, and the second conductive member 7B are formed. The side walls and the bottom surface of the inductance structure 8 are surrounded by the upper electrode film.
Forming the first conductive member 7A and the second conductive member 7B simultaneously with forming the inductance structure 8; alternatively, after forming the inductance structure 8, forming the first conductive member 7A and the second conductive member 7B; alternatively, after the first conductive member 7A and the second conductive member 7B are formed, the inductance structure 8 is formed.
The material of the inductance structure 8, the first conductive member 7A and the second conductive member 7B is metal, such as copper.
The processes of forming the inductance structure 8, the first conductive member 7A, and the second conductive member 7B each include a plating process.
In one embodiment, the longitudinal dimension of the inductive structure 8 is 100um to 1000um, such as 100um, 260um, 680um or 1000um.
Referring to fig. 13, a first rewiring layer 10A and a second rewiring layer 10B are formed on the side of the substrate layer 1 having the trench structure.
After the inductor structure 8, the first conductive member 7A, and the second conductive member 7B are formed, a first connection member is formed on the first conductive member 7A, the lower electrode film 4, and a side of the inductor structure 8 facing away from the substrate layer 1. After the first connectors are formed, a first redistribution layer 10A is formed on a side of the first connectors away from the substrate layer 1. The first redistribution layer 10A is electrically connected to the lower electrode film 4 and the first conductor 7A.
In this embodiment, the first redistribution layer 10A is electrically connected to the inductance structure 8 in the nth trench; in other embodiments, the first redistribution layer is electrically connected to the inductive structure in the first ring of trenches.
A second connecting element is formed on the second conductor 7B, on the side of the inductance structure 8 and on the side of the upper electrode film 6 facing away from the substrate layer 1. After the second connection member is formed, a second redistribution layer 10B is formed on a side of the second connection member facing away from the substrate layer 1. The second rewiring layer 10B is electrically connected to the upper electrode film 6 and the second conductive member 7B.
In this embodiment, the second redistribution layer 10B is electrically connected to the inductance structure 8 in the first ring trench; in other embodiments, the second redistribution layer is electrically connected to the inductive structure in the nth turn trench.
The first rewiring layer 10A and the second rewiring layer 10B may be formed in different layers, the first rewiring layer 10A and the second rewiring layer 10B being formed successively; the first rewiring layer 10A and the second rewiring layer 10B may be formed at the same time and spaced apart in the same layer.
Referring to fig. 14, a third redistribution structure is formed on a side of the substrate layer 1, the first conductive member 7A, and the second conductive member 7B facing away from the first redistribution layer 10A.
After the second rewiring layer 10B is formed, a third rewiring structure 11 is formed. The third redistribution structure 11 is electrically connected to the first conductive member 7A and the second conductive member 7B.
Thinning the substrate layer 1 on the side away from the first redistribution layer 10A, wherein the substrate layer 1 is thinned to expose the first conductive piece 7A and the second conductive piece 7B; after the first conductive member 7A and the second conductive member 7B are exposed, a third redistribution structure 11 is formed.
With continued reference to fig. 14, a first solder ball 9A and a second solder ball 9B are formed on a side of the third heavy wiring structure 11 away from the substrate layer 1, and both the first solder ball 9A and the second solder ball 9B are electrically connected to the third heavy wiring structure 11.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (12)
1. An interposer structure, comprising:
a substrate layer;
a trench structure in the substrate layer of partial thickness; the groove structure comprises a first circle of continuous grooves to an Nth circle of continuous grooves which are distributed from the center of the groove structure to the side edge of the groove structure, and N is an integer greater than or equal to 2;
the lower electrode film covers the inner walls of the first circle of grooves to the Nth circle of grooves;
the capacitor dielectric film is positioned on the surface of one side, away from the inner wall of the groove structure, of the lower electrode film;
the upper electrode film is positioned on the surface of one side, away from the lower electrode film, of the capacitor dielectric film;
and the inductance structure is positioned in the first-turn groove to the Nth-turn groove, and the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film.
2. The interposer structure of claim 1, further comprising: a first conductive member and a second conductive member both penetrating through the substrate layer, the first conductive member and the second conductive member being located at a side portion of the trench structure and spaced apart from the trench structure; a first rewiring layer and a second rewiring layer on a side of the substrate layer having a trench structure, the first rewiring layer being electrically connected to the lower electrode film and the first conductive member, the second rewiring layer being electrically connected to the upper electrode film and the second conductive member;
the first rewiring layer is electrically connected with the inductance structure in the first ring of grooves, and the second rewiring layer is electrically connected with the inductance structure in the Nth ring of grooves; or, the first redistribution layer is electrically connected with the inductance structure in the nth groove, and the second redistribution layer is electrically connected with the inductance structure in the first groove.
3. The interposer structure of claim 2, further comprising: and the third redistribution structure is positioned on one side of the substrate layer, the first conductive piece and the second conductive piece, which is far away from the first redistribution layer.
4. The interposer structure of claim 2 wherein the substrate layer has a first via and a second via; the first conductive member is located in the first through hole, and the second conductive member is located in the second through hole.
5. The adapter plate structure of claim 4, further comprising: a first insulating layer located between the lower electrode film and an inner wall surface of the trench structure; and the second insulating layers are positioned between the inductance structure and the upper electrode film, between the inner wall of the first through hole and the first conductive piece and between the inner wall of the second through hole and the second conductive piece.
6. The adapter plate structure of claim 5, wherein the first insulating layer further covers a top surface of the substrate layer between the first through nth turn grooves, a top surface of the substrate layer between the nth turn groove and the first through hole, and a top surface of the substrate layer between the nth turn groove and the second through hole; the lower electrode film further extends to an upper surface of the substrate layer away from the first insulating layer; the capacitor dielectric film also extends to an upper surface of the lower electrode film facing away from a top surface of the substrate layer; the upper electrode film also extends to an upper surface of the capacitor dielectric film facing away from a top surface of the substrate layer; the second insulating layer also extends to an upper surface of the upper electrode film facing away from the top surface of the substrate layer.
7. The interposer structure of claim 2, further comprising: the first connecting pieces are located between the first redistribution layer and the inductor structure, between the first redistribution layer and the lower electrode film, and between the first redistribution layer and the first conductive piece, and the second connecting pieces are located between the second redistribution layer and the upper electrode film, between the second redistribution layer and the inductor structure, and between the second redistribution layer and the second conductive piece.
8. A method for manufacturing an adapter plate structure is characterized by comprising the following steps:
providing a substrate layer;
forming a trench structure in the substrate layer of a partial thickness; the groove structure comprises a first circle of continuous grooves to an Nth circle of continuous grooves which are distributed from the center of the groove structure to the edge of the side part of the groove structure, and N is an integer which is greater than or equal to 2;
forming a lower electrode film on the inner walls of the first circle of grooves to the Nth circle of grooves;
forming a capacitor dielectric film on the surface of one side, away from the inner wall of the groove structure, of the lower electrode film;
forming an upper electrode film on the surface of one side of the capacitor dielectric film, which is far away from the lower electrode film;
and forming an inductance structure in the first-Nth circles of grooves, wherein the side wall and the bottom surface of the inductance structure are surrounded by the upper electrode film.
9. The method of making an adapter plate structure of claim 8, further comprising:
after forming the upper electrode film, forming a first through hole and a second through hole on a substrate layer, wherein the first through hole and the second through hole are positioned at the side part of the groove structure and are spaced from the groove structure;
forming a first conductive member in the first via hole and a second conductive member in the second via hole;
forming a first rewiring layer and a second rewiring layer on one side of the substrate layer having a trench structure, the first rewiring layer being electrically connected to the lower electrode film and the first conductive member, the second rewiring layer being electrically connected to the upper electrode film and the second conductive member;
the first rewiring layer is electrically connected with the inductance structure in the first ring of grooves, and the second rewiring layer is electrically connected with the inductance structure in the Nth ring of grooves; or the first redistribution layer is electrically connected with the inductance structure in the Nth circle of groove, and the second redistribution layer is electrically connected with the inductance structure in the first circle of groove;
preferably, the first conductive member and the second conductive member are formed at the same time when the inductance structure is formed.
10. The method of making an adapter plate structure of claim 9, further comprising: after forming the first and second redistribution layers, a third redistribution structure is formed on a side of the substrate layer, the first conductive member, and the second conductive member facing away from the first redistribution layer.
11. The method of making an adapter plate structure of claim 8, further comprising: and forming a first insulating layer on the inner wall surface of the groove structure before forming the lower electrode film on the inner walls of the first to Nth grooves.
12. The method of making an adapter plate structure of claim 9, further comprising: before forming the first conductive piece, the second conductive piece and the inductance structure, forming a second insulating layer on the surface of one side of the upper electrode film, which is far away from the capacitance dielectric film, and the inner wall surfaces of the first through hole and the second through hole.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211318454.4A CN115579348A (en) | 2022-10-26 | 2022-10-26 | Adapter plate structure and preparation method thereof |
| PCT/CN2023/088725 WO2024087535A1 (en) | 2022-10-26 | 2023-04-17 | Adapter board structure and preparation method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211318454.4A CN115579348A (en) | 2022-10-26 | 2022-10-26 | Adapter plate structure and preparation method thereof |
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| CN115579348A true CN115579348A (en) | 2023-01-06 |
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| CN202211318454.4A Pending CN115579348A (en) | 2022-10-26 | 2022-10-26 | Adapter plate structure and preparation method thereof |
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| WO (1) | WO2024087535A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024087535A1 (en) * | 2022-10-26 | 2024-05-02 | 华进半导体封装先导技术研发中心有限公司 | Adapter board structure and preparation method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6573148B1 (en) * | 2000-07-12 | 2003-06-03 | Koninklljke Philips Electronics N.V. | Methods for making semiconductor inductor |
| FR2830683A1 (en) * | 2001-10-10 | 2003-04-11 | St Microelectronics Sa | Integrated circuit with inductance comprises spiral channel in which metal deposit forms inductance winding |
| KR100475533B1 (en) * | 2002-12-27 | 2005-03-10 | 매그나칩 반도체 유한회사 | Inductor monitoring pattern and method for manufacturing the same |
| US8686522B2 (en) * | 2011-10-13 | 2014-04-01 | International Business Machines Corporation | Semiconductor trench inductors and transformers |
| EP3422417B1 (en) * | 2017-06-30 | 2021-08-04 | Murata Manufacturing Co., Ltd. | Distributed lc filter structure |
| CN115579348A (en) * | 2022-10-26 | 2023-01-06 | 华进半导体封装先导技术研发中心有限公司 | Adapter plate structure and preparation method thereof |
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2022
- 2022-10-26 CN CN202211318454.4A patent/CN115579348A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024087535A1 (en) * | 2022-10-26 | 2024-05-02 | 华进半导体封装先导技术研发中心有限公司 | Adapter board structure and preparation method therefor |
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