CN218831252U

CN218831252U - Capacitor structure

Info

Publication number: CN218831252U
Application number: CN202222105082.9U
Authority: CN
Inventors: 邹道华; 高谷信一郎; 刘昱玮; 黄仁耀
Original assignee: Changzhou Chengxin Semiconductor Co Ltd
Current assignee: Changzhou Chengxin Semiconductor Co Ltd
Priority date: 2022-08-10
Filing date: 2022-08-10
Publication date: 2023-04-07
Anticipated expiration: 2032-08-10

Abstract

A capacitive structure, comprising: a substrate; the first electrode layer is positioned on the substrate and provided with a first projection pattern on the substrate; a first insulating layer on the first electrode layer; and the second electrode layer is positioned on the first insulating layer and provided with a second projection pattern on the substrate, and each edge of the second projection pattern is retracted within the projection range of the first projection pattern. Because each edge of the second projection pattern of the second electrode layer is retracted into the projection range of the first projection pattern of the first electrode layer, the corresponding edges of the first electrode layer and the second electrode layer are staggered in the direction perpendicular to the surface of the substrate, the phenomenon that the edges of the first electrode layer and the second electrode layer are discharged in the direction perpendicular to the surface of the substrate is avoided, the problem that the first insulating layer is broken down due to the dead discharge is solved, and the breakdown voltage of the capacitor structure and the reliability of the capacitor structure are improved.

Description

Capacitor structure

Technical Field

The utility model relates to a semiconductor manufacturing technology field especially relates to an electric capacity structure.

Background

With the continuous progress of the manufacturing technology of semiconductor integrated circuits, the progress of miniaturization and miniaturization of devices has been accompanied. The capacitor structure is an important component unit of an integrated circuit, and the capacitor structure in an integrated circuit chip is various, such as: a MOS (metal-oxide-semiconductor) field effect transistor capacitor; a PIP (polysilicon-insulator-polysilicon) capacitor, a variable junction capacitor, and a MIM (metal-insulator-metal) capacitor and a MOM (metal-oxide-metal) capacitor in a back-end interconnection.

Currently, there are two most commonly used back-end interconnection capacitor structures: MIM capacitors and MOM capacitors. The MIM capacitor and the MOM capacitor exist in a back-end interconnection layer structure, the area of a device layer is not occupied, and the linear characteristic of the capacitor is far better than that of other types of capacitors. The MOM capacitor mainly utilizes the integral capacitor formed between the upper and lower layer metal wires and the same layer metal, and has the advantage that the capacitor can be realized by the existing interconnection manufacturing process, namely, the MOM capacitor and copper interconnection structure can be completed simultaneously.

MIM capacitors are simple in structure, can have minimal resistivity, and are substantially free of parasitic capacitance due to internal depletion and relatively large capacitance. Therefore, MIM capacitors are often used in semiconductor devices, especially in high frequency devices. While more masks and more complex processes are required to form a MIM capacitor, a MIM capacitor can provide a more stable capacitance and can provide a larger capacitance. Therefore, MIM capacitors are still widely used.

However, the MIM capacitor in the related art still has many problems.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem provide an electric capacity structure to promote electric capacity structure's breakdown voltage and electric capacity structure's reliability.

In order to solve the above problem, the utility model provides an electric capacity structure, include: a substrate; the first electrode layer is positioned on the substrate and provided with a first projection pattern on the substrate; a first insulating layer on the first electrode layer; and the second electrode layer is positioned on the first insulating layer and provided with a second projection pattern on the substrate, and each edge of the second projection pattern is retracted in the projection range of the first projection pattern.

Optionally, each side of the second projection pattern is retracted within the projection range of the first projection pattern by a fixed size.

Optionally, the fixed size range: 0.1 to 0.3 micron.

Optionally, the method further includes: a third electrode layer located over the second electrode layer; and the second insulating layer is positioned between the third electrode layer and the second electrode layer.

Optionally, the third electrode layer has a third projection pattern on the substrate, and each edge of the third projection pattern is retracted within a projection range of the second projection pattern.

Optionally, each side of the third projection pattern is retracted within the projection range of the second projection pattern by a fixed size.

Optionally, the fixed size range: 0.1 to 0.3 micron.

Optionally, the method further includes: a first lead layer connected to the first electrode layer; the first lead layer and the second lead layer are respectively positioned on two opposite sides of the first electrode layer, and the first insulating layer is positioned between the first electrode layer and the second lead layer; a first lead connected to the first lead layer; a second lead connected to the second lead layer.

Optionally, the first projection pattern includes: rectangular.

Optionally, the second projection pattern includes: rectangular.

Compared with the prior art, the technical scheme of the utility model have following advantage:

the utility model discloses in technical scheme's the capacitor structure, because each limit of the second projection figure of second electrode layer draw back in the projection scope of the first projection figure of first electrode layer, consequently first electrode layer with each corresponding border of second electrode layer is at the perpendicular to stagger each other in the direction of the substrate surface, avoid first electrode layer with the border discharge of second electrode layer is at the perpendicular to form just right in the direction of the substrate surface, and then reduce and puncture owing to just right discharge the problem on first insulation layer promotes with this capacitor structure's breakdown voltage and capacitor structure's reliability.

Further, the third electrode layer has a third projection pattern on the substrate, and each side of the third projection pattern is retracted within a projection range of the second projection pattern. By staggering the corresponding edges between the second electrode layer and the third electrode layer in the direction perpendicular to the surface of the substrate, edge discharge between the second electrode layer and the third electrode layer is prevented from forming right alignment in the direction perpendicular to the surface of the substrate, and the problem that the second insulating layer is broken down due to the right alignment discharge is further reduced, so that the breakdown voltage of the capacitor structure and the reliability of the capacitor structure are improved.

Drawings

FIGS. 1 and 2 are schematic structural diagrams of a capacitor structure;

fig. 3 to 5 are schematic structural diagrams of a capacitor structure according to an embodiment of the present invention;

fig. 6 and 7 are schematic structural diagrams of a capacitor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, there are still many problems with the prior art capacitor structures. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 1 and 2 are schematic structural diagrams of a capacitor structure.

Referring to fig. 1 and fig. 2, fig. 2 isbase:Sub>A schematic cross-sectional view taken along linebase:Sub>A-base:Sub>A of fig. 1,base:Sub>A capacitor structure, comprising: a substrate (not shown); a first electrode layer 101 located on the substrate, the first electrode layer 101 having a first projected pattern on the substrate; a first insulating layer 102 on the first electrode layer 101; a second electrode layer 103 on the first insulating layer 102, the second electrode layer 103 having a second projected pattern on the substrate, the first projected pattern and the second projected pattern being coincident.

In this embodiment, since the first projection pattern of the first electrode layer 101 and the second projection pattern of the second electrode layer 103 are overlapped, the corresponding edges of the first electrode layer 101 and the second electrode layer 103 are completely opposite to each other in a direction perpendicular to the substrate surface. When the capacitor structure operates, the edges of the first electrode layer 101 and the second electrode layer 102 are easy to generate discharge, and when the corresponding edges of the first electrode layer 101 and the second electrode layer 102 are completely opposite in the direction perpendicular to the substrate surface, the first insulating layer 102 is easy to be broken down by the two completely opposite discharges (as shown in a part a and a part B in fig. 2), so that the breakdown voltage of the capacitor structure is low.

On this basis, the utility model provides a capacitor structure, because each limit of the second projection figure of second electrode layer draw back in the projection scope of the first projection figure of first electrode layer, consequently first electrode layer with each corresponding border of second electrode layer is at the perpendicular to stagger each other in the direction of the substrate surface, avoid first electrode layer with the border discharge of second electrode layer is at the perpendicular to form just right in the direction of the substrate surface, and then reduce and puncture owing to just right discharge the problem on first insulation layer promotes with this capacitor structure's breakdown voltage and capacitor structure's reliability.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 5 are schematic structural diagrams of a capacitor structure according to an embodiment of the present invention.

Referring to fig. 3 to 5, fig. 3 is a top view of a capacitor structure without a first insulating layer, fig. 4 is a cross-sectional view taken along line B-B of fig. 3, and fig. 5 is a cross-sectional view taken along line C-C of fig. 3, a capacitor structure comprising: a substrate (not shown); a first electrode layer 201 located on the substrate, the first electrode layer 201 having a first projected pattern on the substrate; a first insulating layer 202 over the first electrode layer 201; and the second electrode layer 203 is positioned on the first insulating layer 202, the second electrode layer 203 has a second projection pattern on the substrate, and each edge of the second projection pattern is retracted within the projection range of the first projection pattern.

In this embodiment, since each edge of the second projection pattern of the second electrode layer 203 is retracted within the projection range of the first projection pattern of the first electrode layer 201, corresponding edges of the first electrode layer 201 and the second electrode layer 203 are staggered from each other in a direction perpendicular to the substrate surface, so that edge discharge of the first electrode layer 201 and the second electrode layer 203 is prevented from forming an opposite alignment in the direction perpendicular to the substrate surface, and further, the problem that the first insulating layer 202 is broken down due to the opposite discharge is reduced, thereby improving the breakdown voltage of the capacitor structure and the reliability of the capacitor structure.

In this embodiment, each side of the second projection pattern is retracted within the projection range of the first projection pattern by a fixed dimension d.

In this embodiment, the fixed dimension d ranges from: 0.1 to 0.3 micron. The specific choice of the fixed dimension d needs to be determined according to the operating voltage.

In this embodiment, the first projection pattern is a rectangle; the second projection pattern is rectangular.

The first electrode layer 201 is made of one or more of gold, tantalum nitride, titanium nitride, aluminum, copper and titanium, and the second electrode layer 203 is made of one or more of gold, tantalum nitride, titanium nitride, aluminum, copper and titanium.

In this embodiment, the materials of the first electrode layer 201 and the second electrode layer 203 are copper, respectively.

With continued reference to fig. 3 to 5, the capacitor structure further includes: a first lead layer 204 connected to the first electrode layer 201; a second lead layer 205 connected to the second electrode layer 203, wherein the first lead layer 204 and the second lead layer 205 are respectively located at two opposite sides of the first electrode layer 201, and the first insulating layer 202 is located between the first electrode layer 201 and the second lead layer 205; a first lead 206 connected to the first lead layer 204; and a second lead 207 connected to the second lead layer 205.

In this embodiment, a capacitor structure is described on the basis of the capacitor structure in the above embodiment (fig. 4), and the difference between this embodiment and the above embodiment is that: further comprising: a third electrode layer and a second insulating layer on the second electrode layer. The following detailed description will be made in conjunction with the accompanying drawings.

Referring to fig. 6 and 7, fig. 6 is a top view of a capacitor structure with a first insulating layer and a second insulating layer omitted, fig. 7 is a schematic cross-sectional view taken along line D-D in fig. 6, and the capacitor structure further includes: a third electrode layer 301 over the second electrode layer 203; a second insulating layer 302 between the third electrode layer 301 and the second electrode layer 203.

In this embodiment, the third electrode layer 301 has a third projection pattern on the substrate, and each side of the third projection pattern is retracted within the projection range of the second projection pattern.

In this embodiment, by staggering the corresponding edges between the second electrode layer 203 and the third electrode layer 301 in the direction perpendicular to the substrate surface, edge discharge between the second electrode layer 203 and the third electrode layer 301 is prevented from forming a direct alignment in the direction perpendicular to the substrate surface, and thus the problem of breakdown of the second insulating layer 302 due to the direct alignment is reduced, so as to improve the breakdown voltage of the capacitor structure and the reliability of the capacitor structure.

In this embodiment, each side of the third projection pattern is retracted within the projection range of the second projection pattern by a fixed dimension d.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A capacitive structure, comprising:

a substrate;

the first electrode layer is positioned on the substrate and provided with a first projection pattern on the substrate;

a first insulating layer on the first electrode layer;

and the second electrode layer is positioned on the first insulating layer and provided with a second projection pattern on the substrate, and each edge of the second projection pattern is retracted in the projection range of the first projection pattern.

2. The capacitor structure of claim 1, wherein each side of the second projected pattern is recessed within the projected range of the first projected pattern by a fixed dimension.

3. The capacitive structure of claim 2 wherein the fixed size range is: 0.1 to 0.3 micron.

4. The capacitive structure of claim 1, further comprising: a third electrode layer located over the second electrode layer; and the second insulating layer is positioned between the third electrode layer and the second electrode layer.

5. The capacitor structure of claim 4, wherein the third electrode layer has a third projected pattern on the substrate, and each side of the third projected pattern is recessed within a projected range of the second projected pattern.

6. The capacitive structure of claim 5, wherein each side of the third projected pattern is recessed within the projected range of the second projected pattern by a fixed dimension.

7. The capacitive structure of claim 6 wherein the fixed size range is: 0.1 to 0.3 micron.

8. The capacitive structure of claim 1, further comprising: a first lead layer connected to the first electrode layer; the first lead layer and the second lead layer are respectively positioned on two opposite sides of the first electrode layer, and the first insulating layer is positioned between the first electrode layer and the second lead layer; a first lead connected to the first lead layer; a second lead connected to the second lead layer.

9. The capacitive structure of claim 1 wherein said first projected pattern comprises: rectangular.

10. The capacitive structure of claim 1 wherein said second projected pattern comprises: rectangular.