CN115562620A - Millimeter wave TDM-MIMO radar real-time super-resolution method based on FPGA - Google Patents

Abstract

The invention discloses a millimeter wave TDM-MIMO radar real-time super-resolution method based on FPGA, which is applied to the technical field of radar imaging and aims at solving the problems that the prior art has high computational complexity and the traditional hardware signal processing platform cannot meet the requirement of rapid operation processing; the FPGA board card analyzes and caches radar data, preprocesses and sends effective radar data; processing radar data by adopting hardware optimization design to realize recursive estimation of intermediate variables; computing, iterating and updating the auxiliary variable by the intermediate variable, and quickly caching the data variable; the invention achieves iteratively updating a fast angle estimate with a loop minimization. The invention overcomes the defects of high algorithm complexity and difficult real-time signal processing in the existing super-resolution DOA technology, and greatly improves the calculation efficiency of the algorithm.

Description

Millimeter wave TDM-MIMO radar real-time super-resolution method based on FPGA

Technical Field

The invention belongs to the technical field of radar imaging, and particularly relates to a millimeter wave radar high-flux super-resolution processing technology.

Background

Time division multiplexing multiple input multiple output (TDM-MIMO) radar direction of arrival (DOA) estimation plays an important role in application fields such as battlefield target positioning and tracking and automobile auxiliary driving. The angular resolution of the direct digital beamforming DOA estimation method is limited by the number of physical array elements. Considering space and cost, the method of increasing the number of array elements to improve the angular resolution has a great limitation in practical engineering applications. Documents "T.yardibi, J.Li, P.Stoica, M.Xue and A.B.Baggeroor, source Localization and Sensing: A Nonparametric Iterative Adaptive applied raw Based on Weighted Least Squares, in IEEE Transactions on Aerospace and Electronic systems.2010,46 (1): 425-443" propose an Iterative Adaptive Algorithm (IAA), and the method reduces the requirement of the traditional spectrum estimation method on fast beat number through Iterative Adaptive updating of an autocorrelation matrix, and effectively improves the azimuth resolution of the millimeter wave radar. However, the improvement of the resolution of the IAA algorithm is at the cost of sacrificing the operation efficiency, and the real-time requirement of the IAA in practical application is severely restricted. To further improve the resolution, the documents "P.Stoica, P.Babu and J.Li, new Method of Sparse Parameter Estimation in Separable Models and Its uses for Spectral Analysis of Irregularly Sampled Data, in IEEE Transactions on Signal Processing,2011,59 (1): 35-47" propose a Sparse iterative Estimation algorithm (SPICE) based on covariance, derived from a covariance fitting criterion, which can be used for accurate reconstruction of objects and information in the case of multiple fast beats, with a simple, stable statistical basis, without the need to select any parameters, and with the property of global convergence. However, the computational complexity of SPICE algorithm is still high, and the traditional hardware signal processing platform cannot meet the requirement of fast arithmetic processing due to the existing large matrix operation.

Disclosure of Invention

In order to solve the technical problem, the invention provides a millimeter wave TDM-MIMO radar real-time super-resolution method based on an FPGA. The field programmable logic array (FPGA) can be developed in a targeted manner according to project requirements and a signal processing algorithm, repeated programming and reconfiguration can be realized, a radar hardware system does not need to be changed, and the updating and maintenance cost of a later algorithm optimization system is reduced. Aiming at the problem of high computational complexity of the SPICE algorithm, the design and implementation of a hardware algorithm for high-speed processing can be researched by utilizing a parallel framework of an FPGA.

The technical scheme adopted by the invention is as follows: a millimeter wave TDM-MIMO radar real-time super-resolution method based on FPGA comprises the following steps:

s1, acquiring a sparse scene target sample to obtain radar data;

s2, sending radar data to the FPGA board card by using a high-speed interface;

s3, analyzing and caching radar data by the FPGA board card, preprocessing and sending effective radar data;

s4, processing radar data by adopting hardware optimization design to realize recursive estimation of intermediate variables;

s5, computing, iterating and updating the auxiliary variables by the intermediate variables, and caching the data variables quickly;

and S6, iteratively updating the fast angle estimation by loop minimization.

The invention has the beneficial effects that: the method overcomes the defects of high algorithm complexity, difficult realization of a signal processing platform or overlong processing time in the prior art. The present invention is simply implemented with loop minimization, and can realize efficient calculation with constant calculation and storage costs even in the case of processing a large amount of data. Meanwhile, the original batch processing data mode is replaced by the recursive estimation mode, and floating point number evolution operation is solved by using a parallel matrix computing structure and a table look-up method, so that the computing time is greatly shortened, and the system can process data in real time.

Drawings

FIG. 1 is a flow chart of the present invention;

fig. 2 is a block diagram of the radio frequency board card according to the present embodiment;

FIG. 3 is a high-speed interface block diagram according to the present embodiment;

fig. 4 is a block diagram of a radar data reception module according to the present embodiment;

FIG. 5 is a schematic diagram of a Topritz matrix expressed by column vectors according to the present embodiment;

FIG. 6 is a block diagram of a Topritz matrix Γ data output module according to the present embodiment;

FIG. 7 is a block diagram of calculation of the vector ρ in the present embodiment;

FIG. 8 is a top block diagram of auxiliary variable computation in the present embodiment;

FIG. 9 is a block diagram of the operator vector dot product (dot) module of the present embodiment;

FIG. 10 is a block diagram of the serial-to-parallel conversion according to the present embodiment;

FIG. 11 is a top block diagram of angle estimation according to the present embodiment;

FIG. 12 is a diagram of a single-precision floating-point number lookup and squaring module according to the present embodiment;

fig. 13 is a multiple-input multiple-output (MIMO) point target echo diagram of the present embodiment;

wherein, FIG. 13 (a) is an echo diagram of two point targets before the system is not processing; FIG. 13 (b) is an echo diagram of two point targets after system processing.

Detailed Description

In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.

The invention provides a millimeter wave TDM-MIMO radar real-time super-resolution method based on an FPGA, which overcomes the defects of high algorithm complexity, difficult realization of a signal processing platform or overlong processing time in the prior art. The combined hardware signal processing platform improves the resolution of the millimeter wave MIMO radar by realizing a super-resolution algorithm, realizes real-time imaging of a target, and can realize high-efficiency calculation with constant calculation and storage cost even under the condition of processing a large amount of data.

The specific implementation steps of the invention are described as follows with reference to the attached drawing 1:

s1, acquiring a sparse scene target sample and acquiring radar data. As shown in fig. 2, the number K of angle sampling points used in this embodiment is 256, and the angle sampling value is θ = (θ =) ₁ ,θ ₂ ,…,θ ₂₅₆ ) The number M of the millimeter wave TDM-MIMO radar transmitting antennas is 12, and the number N of the receiving antennas is 16. The radar transmits at a particular pulse repetition frequency (i.e., TX [3:1 ] in FIG. 2]) 12-channel chirp signals, received by radar (i.e. RX 4:1 in FIG. 2) during adjacent transmit pulse interval periods]) And after digital-to-analog conversion, the 16-channel echo signals are sent out from the digital-to-analog conversion buffer and send radar data to the FPGA end through the CSI2 interface.

And S2, sending radar data to the FPGA board card by using the high-speed interface. As shown in fig. 3, the CSI2 interface is configured with 1 Clock Lane (Clock Lane) and 4 Data lanes (Data Lane), and an additional Frame synchronization signal (Frame Syn) configured by the general input/output interface, for a total of 6 pairs of differential signals. Wherein, 4 Data Lanes are controlled by Clock Lane and Frame Syn to perform radar Data synchronous transmission. The control interface is a Serial Peripheral Interface (SPI), a radar board is used as a host to send Valid, the FPGA is used as a slave to send Ready, and the two signals control the sending and receiving of radar data based on a handshake protocol.

And S3, the FPGA board card analyzes and caches the radar data, and effective radar data are preprocessed and sent. Specifically, as shown in fig. 4, the radar data of the 4 channels is controlled by a finite state machine module (FSM) to be transmitted into the FPGA board MIPI CSI2Rx module, and the transmitted radar data packets are parsed into data streams. Specifically, a differential-to-single-ended (IBUFDS) module converts a transmitted differential signal pair (LVDS) into a single-ended signal, a serial-to-parallel module (Seri to Para) converts serially input single-ended data into 16-bit data for output, and a Packet parsing module (Packet parsing) identifies a header flag, a frame count, waveform information, a chip number, channel information, and a tail flag of a frame to complete data framing. And then, radar data caching is carried out, and because two clock sources of a data synchronous clock and a self-configured clock of the FPGA exist, asynchronous FIFO is adopted to carry out clock domain crossing data caching.

In particular, to improve the operation precision of the whole processing system, all data are operated by adopting the format of single-precision floating point number. Therefore, after ADC data transmitted by the radar board card is cached, the ADC data needs to be converted into single-precision floating point numbers through integer shaping in a data conversion module (float convert), and then the ADC data can be used for calculation of each subsequent module. Specifically, the sign bit of the data is not changed, the highest is not 0 bit plus offset 127 to form an 8-bit floating point exponent, and the tail ends of all data after the highest bit are filled with zeros to form a 23-bit mantissa, and finally the mantissa is converted into a 32-bit single-precision floating point.

And S4, processing the radar data by adopting hardware optimization design, and realizing recursive estimation of intermediate variables. The intermediate variables of the recursive computation are three as follows:

κ(m)＝κ(m-1)+y(m) ^H *y(m) (1)

ρ(m)＝ρ(m-1)+h(m) ^H *y(m) (2)

Γ(m)＝Γ(m-1)+h(m) ^H *h(m) (3)

wherein, κ (0), ρ (0), and Γ (0) are initial 0 values, y (M) is N receiving antenna data corresponding to M (M =1, …, M) th transmitting antenna of the TDM-MIMO radar, that is, radar data buffered in S3; y (m) ^H Is the conjugate transpose of y (m). H (m) is the steering matrix H (m) determined by the array

Is a complex matrix of 192 x 256,

representing a complex field), wherein the steering matrix H is stored in a memory cell of the FPGA, and the matrix data is read to complete the operation when calculating formula (2).

The gamma (m) is a special Toeplitz (toeplitz) matrix, and in order to accelerate the running speed and save the operation expense, the gamma (m) matrix is changed into prestored data. As shown in fig. 5, based on the characteristics of the toeplitz matrix, the column vector can be obtained by circularly shifting the previous column vector downwards, and the characteristics conform to the characteristics of a circular queue, so that the data of the Γ (m) matrix can be used for realizing that a single column element expresses the whole toeplitz matrix by the circular queue formed by an internal memory Block RAM (BRAM) of the FPGA, and 256 times of storage resources can be saved.

Specifically, as shown in fig. 6, the design adopts 32-parallelism calculation for the 256 × 256 matrix, and as can be seen from the above, the 256 × 256 matrix can express the entire matrix by only selecting the first row of elements. In the design, through 8 BRAMs storing 2048 bit data, namely, each BRAM outputs 32 64-bit complex single-precision floating point numbers, 32 data of the RAM1 are output according to a first clock, data of the RAM2 are output according to a second clock, and the data are sequentially executed for 8 times through an 8-to-1 data selector, so that 256 data output of a first column is completed. And (3) when the 8 th clock data is output, performing data transfer through the RAM read-write controller to form a second column element of the toeplitz matrix, and then continuing to output the data until the whole matrix operation is completed.

As shown in fig. 7, when calculating ρ (m), it is necessary to store the current vector value for the next recursive calculation, the initial value in ρ RAM1 is 0, and the value in ρ RAM1 and the calculation h (m) are read in the first calculation ^H * The addition of the values of y (m) completes the recursive operation, and the result is stored in ρ RAM 2. And when the whole calculation process is finished, controlling the data reading and writing process between the rho RAM1 and the rho RAM2 by the rho control, and writing the data in the rho RAM2 into the rho RAM1 to finish the seamless data transmission. κ (m) is similar to this structure, but differs in that the calculation result of κ (m) is a single value, so that it can be realized by only requiring two registers reg to replace the RAM1 and RAM2 in ρ calculation, respectively.

And S5, calculating, iterating and updating the auxiliary variables, and quickly caching the data variables. The calculation steps are as follows:

η＝κ(m)+θ ^H Γ(m)θ-2real{θ ^H ρ(m)} (4)

ζ＝ρ(m)-Γ(m)θ (5)

real is the real part of the complex number. Fig. 8 shows a top-level block diagram of the whole S4 recursive estimation of the intermediate variables and S5 computation of the auxiliary variables. χ = Γ (m) θ, epsilon = θ ^H ρ(m)、δ＝θ ^H χ is applied by an operator vector point product (dot) module. Specifically, as shown in fig. 9, the operator dot module is designed such that data sequentially passes through 32-degree-of-parallelism complex multiplication, 32 numbers of data are added by a low-time-lag adder, and finally the sum of 256 times of complex multiplication data, that is, the final value of vector dot multiplication, is obtained by passing the adder through a data stream for 8 times.

Because the subsequent calculation process is still 32 parallel calculation, the vectors χ and ε obtained by calculation need to pass through a serial-to-parallel module to convert the serially output vectors into 32 parallel output forms. Specifically, as shown in fig. 10, the serial-to-parallel module uses a counter to buffer data via the BRAM. After the data is cached, 32 data are sent out together through a pull-up control instruction. Meanwhile, in order to reduce fan-out, 32 data are combined into one data from high order to low order, and then the data are sent out, so that serial data are converted into 32 parallel data to be output. And finally, sending the calculated auxiliary variables eta and zeta to an S6 module for angle estimation.

And S6, realizing iterative updating of the fast angle estimation by cyclic minimization. The calculation steps of the whole algorithm are as follows:

for m＝1,…,M

κ(m)＝κ(m-1)+y(m) ^H *y(m) (6)

ρ(m)＝ρ(m-1)+h(m) ^H *y(m) (7)

Γ(m)＝Γ(m-1)+h(m) ^H *h(m) (8)

η＝κ(m)+θ ^H Γ(m)θ-2real{θ ^H ρ(m)} (9)

ζ＝ρ(m)-Γ(m)θ (10)

for k＝1,…,K

n＝(m-1)*16+1 (11)

α _k ＝η+Γ _kk |θ _k | ² +2real{θ _k ζ _k } (12)

β _k ＝Γ _kk (13)

γ _k ＝|ζ _k +Γ _kk θ _k | (14)

end for

end for

wherein, the formulas (6) - (10) are the calculation processes of S4 and S5, and the formulas (11) - (20) are the calculation processes of iteratively updating the fast angle estimation for the minimization of the S6 loop. M takes 12 as the number of millimeter wave TDM-MIMO radar transmitting antennas, K takes 256 as the number of angle sampling points, zeta _k And theta _k The kth elements, Γ, of vectors ζ and θ, respectively _kk And Γ _k Respectively the kth diagonal element and the kth column element of the Γ matrix. Obtaining three variables theta through formulas (17) to (19) respectively _k Estimated values of eta, zeta

And reassigned to θ in equation (20) _k And eta and zeta, completing data updating once, and completing updating all elements in the theta vector after K cycles. The operation of the whole algorithm is completed by circulating M times.

Particularly, the number of iterative operations in the estimation process is high, so that the operation time of the iterative operations almost occupies the total operation time of the whole system, and the total operation time of the system can be greatly reduced by optimizing the speed of one iterative operation. As shown in fig. 11, the module design mainly includes data caching and updating of the auxiliary variables η and ζ in S6, and estimation operation of θ. In particular, the data update (equations (18) - (20)) uses a low skew design, i.e., reduces pipeline registers, to reduce the skew of the entire update process below a single cycle. In the operation process, the estimation operation process of theta occupies main operation time, the operation speed of the whole operation process eliminates basic calculation processes such as complex multiplication and addition, the division operation and the evolution operation related in the formula (15) and the formula (16) are long in time consumption, and speed optimization is performed aiming at the process.

Specifically, the single-precision floating-point number expression is f = s · 2 ^E+127 1+F where s is the sign bit, E +127 is the 8-bit exponent plus offset 127, f is the 23-bit mantissa after the decimal point. In the invention, all the open square positive numbers are defaulted, so the sign bit is 0. The square of the single-precision floating point number is as follows:

parity according to E can be converted into:

since divide-by-2 for 2 can be converted to shift right to discard the least significant bits, the above equation can be simplified as:

as shown in fig. 12, after the data is obtained, the exponent and the mantissa of the data are respectively taken, the exponent E is determined to be an odd-even number, and the exponent value after the evolution is obtained through simple calculation. And meanwhile, the mantissa part takes the mantissa as a table address, and the mantissa part of the evolution data is obtained according to a parity table look-up of the exponent. And finally splicing the data together again to obtain the evolution data. Particularly, under the condition of not influencing the data precision, the 23-bit mantissa part omits the lower 4-bit data, and only takes the upper 19 bits for carrying out the evolution calculation, thereby saving part of storage resources.

Specifically, the division operation can be converted into a reciprocal of a dividend multiplied by a divisor, and in order to ensure that the divisor f' ≠ 0, a minimum quantity Δ is added to enable the division operation to be smoothly executed, and f = s · 2 is taken ^E+127 - (1+F), where the actual exponent value of the floating point number is e ₁ = E +127, so the reciprocal index E is taken ₂ ＝-E+127＝254-e ₁ . Also, because 1+F is a decimal between 1 and 2, there is a relationship:

the result is a number less than 1, but the mantissa must be a number between 1 and 2 in the floating-point representation, and the most significant bit of the mantissa must be 1 as known from the above relationship, so the mantissa only needs to be shifted left by one bit, while dividing by 2 keeps the value unchanged, i.e., it is

The correct mantissa value may be obtained as follows:

in the embodiment, on the same platform, the comparison of the operation speed between the traditional computing mode and the design is compared:

TABLE 1 operation speed comparison table

It can be seen from the above experimental results that the method provided by this embodiment is far ahead in processing time. The method provided by the embodiment overcomes the defects that the algorithm in the prior art is high in complexity, a signal processing platform is difficult to realize or the processing time is too long.

FIG. 13 (a) shows an echo plot of two point targets before the system has not processed; FIG. 13 (b) shows the echo plots of two point targets after system processing. It can be seen that there is significant main lobe overlap between the two MIMO point target echoes before the system is left unprocessed. After system processing, there is almost no overlap of the main lobes. The results show that the resolution of the MIMO echo signal is obviously improved after the MIMO echo signal is processed by the system designed by the invention. The abscissa Angle in fig. 13 represents the Angle, and the ordinate Normalized amplitude represents the Normalized amplitude.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (9)

1. A millimeter wave TDM-MIMO radar real-time super-resolution method based on FPGA is characterized by comprising the following steps:

s1, acquiring a sparse scene target sample to obtain radar data;

s2, sending radar data to the FPGA board card by using the high-speed interface;

s3, analyzing and caching radar data by the FPGA board card, preprocessing and sending effective radar data;

s4, processing radar data by adopting hardware optimization design to realize recursive estimation of intermediate variables;

s5, computing, iterating and updating the auxiliary variables by the intermediate variables, and caching the data variables quickly;

and S6, realizing iterative updating of the fast angle estimation by cyclic minimization.

2. The FPGA-based millimeter wave TDM-MIMO radar real-time super resolution method as claimed in claim 1, wherein the high speed interface in step S2 is a CSI2 interface.

3. The real-time super-resolution method for the millimeter wave TDM-MIMO radar based on the FPGA according to claim 2, wherein the step S3 specifically comprises: the method comprises the steps that radar data are controlled by a finite-state machine module to be transmitted into an FPGA board card MIPI CSI2Rx module, transmitted radar data packets are analyzed into data streams, and then asynchronous FIFO is adopted to conduct clock domain crossing data caching; and then the integer conversion to single-precision floating point number processing is carried out in the data conversion module.

4. The real-time super-resolution method for the millimeter wave TDM-MIMO radar based on the FPGA according to claim 3, wherein the intermediate variables in the step S4 are as follows:

κ(m)＝κ(m-1)+y(m) ^H *y(m) (1)

ρ(m)＝ρ(m-1)+h ^H (m)*y(m) (2)

Γ(m)＝Γ(m-1)+h(m) ^H *h(m) (3)

wherein, k (M), ρ (M) and Γ (M) are three intermediate variables, y (M) is data of N receiving antennas corresponding to the mth transmitting antenna of the radar, and M =1, …, M; h (m) is the m-th row vector of the steering matrix H determined by the array,

the control matrix H is stored in a storage unit of the FPGA;

the gamma (m) is a special Topritz matrix, and the data of the gamma (m) matrix is used for realizing that a single column element expresses the whole Topritz matrix by a circular queue formed by RAM;

when rho (m) is calculated, the method comprises a first control unit and two RAMs, wherein the first control unit is marked as rho control, and the two RAMs are respectively marked as rho RAM1 and rho RAM2; the initial value in the rho RAM1 is 0, the value in the rho RAM1 is read during the first operation and added with the value for calculating h (m) × y (m) to complete the recursive operation, and the result is stored in the rho RAM2; when the whole calculation process is finished, controlling a data reading and writing process between the rho RAM1 and the rho RAM2 by the rho control, and writing the data in the rho RAM2 into the rho RAM1 to finish the transmission of seamless data;

when calculating kappa (m), a second control unit is required to be provided with two registers reg, the second control unit is required to be provided with kappa control, and the two registers reg are respectively provided with kappa reg1 and kappa reg 2; the initial value in the kappa reg1 is 0, the value in the kappa reg1 is read during the first operation, the value of h (m) × y (m) is calculated, the recursive operation is completed, and the result is stored in the kappa reg 2; when the whole calculation process is finished, the data read-write process between the kappa reg1 and the kappa reg 2 is controlled by the kappa control, and the data in the kappa reg 2 is written into the kappa reg1, so that the seamless data transmission is completed.

5. The real-time super-resolution method for the millimeter wave TDM-MIMO radar based on the FPGA as claimed in claim 4, wherein the data of the Γ (m) matrix is a circular queue formed by the RAM to realize that a single column element expresses the whole Toeplitz matrix, specifically: calculating by Q parallelism, and expressing the whole Topritz matrix by single column elements by the aid of a circular queue formed by internal memories BRAM of S FPGAs (field programmable gate arrays); each BRAM stores the number of data bits in a matrix of = Γ (m) divided by Q;

outputting Q data per BRAM according to a clock sequence, and executing S times through an S-to-1 data selector to complete a row of data output; carrying out data transmission through a BRAM read-write controller to form subsequent column data output of a gamma (m) matrix; q × S = Γ (m) number of data bits of one column of the matrix.

6. The millimeter wave TDM-MIMO radar real-time super-resolution method based on the FPGA according to claim 4, wherein the auxiliary variable update expression in the step S5 is as follows:

η＝κ(m)+θ ^H Γ(m)θ-2real{θ ^H ρ(m)} (4)

ζ＝ρ(m)-Γ(m)θ (5)

eta and zeta are auxiliary variables, and the auxiliary variable updating structure comprises: chi-operator vector point multiplication module, epsilon-operator vector point multiplication module and delta-operator vector point multiplication module, wherein chi = gamma (m) theta, and epsilon = theta ^H ρ(m)，δ＝θ ^H χ。

7. The FPGA-based millimeter wave TDM-MIMO radar real-time super resolution method according to claim 6, wherein three operator vector point multiplication modules, namely a χ operator vector point multiplication module, an ε operator vector point multiplication module and a δ operator vector point multiplication module, have the same structure, and the calculation process is as follows: the input data sequentially passes through complex multiplication of Q parallelism, the Q number is added through a low-time-lag adder, and finally, the sum of Q multiplied by S complex multiplication data, namely the final value of vector dot multiplication, is obtained through an adder by data flow for S times; the input data of the chi-operator vector point multiplication module are gamma (m) and theta, and the input data of the epsilon-operator vector point multiplication module are chi and theta ^H The input data of the delta operator vector point multiplication module are rho (m) and theta ^H (ii) a Where a denotes multiplication and the superscript H denotes transposition.

8. The FPGA-based millimeter wave TDM-MIMO radar real-time super resolution method as claimed in claim 7, wherein vectors calculated by the χ operator vector dot product module and the ε operator vector dot product module are converted into Q parallel output form by the serial to parallel conversion module.

9. The real-time super-resolution method for the millimeter wave TDM-MIMO radar based on the FPGA according to claim 8, wherein the calculation formula of the step S6 is as follows:

for k＝1,…,K

n＝(m-1)*16+1 (1)

α _k ＝η+Γ _kk |θ _k | ² +2real{θ _k ζ _k } (2)

β _k ＝Γ _kk (3)

γ _k ＝|ζ _k +Γ _kk θ _k | (4)

wherein K represents the number of cycles, ζ _k Is the kth element of ζ, θ _k Is the kth element of theta, Γ _kk And Γ _k Respectively the kth diagonal element and the kth column element of the Γ matrix. Obtaining three variables theta through formulas (17) to (19) respectively _k Estimated values of eta, zeta

A low-time-lag design is adopted for the data updating process in the formula;

for the squaring operation involved in the formula, the single precision floating point number is expressed in the form of f = s · 2 ^E+127 - (1+F) wherein s is sign, E is exponent, and M is 23 mantissa after decimal point; for the evolution data, the exponential value after evolution is obtained through calculation according to the odd-even of the exponent; meanwhile, the mantissa part takes mantissa as a table address, and the mantissa part of the evolution data is obtained according to the parity table look-up of the exponent; finally, splicing the exponent value and the mantissa part together again to obtain evolution data;

for the division operation involved in the formula, the division operation is converted into an operation structure in which the dividend is multiplied by the reciprocal of the divisor.

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