CN115562419A - Quick-response low dropout linear voltage stabilizing circuit - Google Patents
Quick-response low dropout linear voltage stabilizing circuit Download PDFInfo
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- CN115562419A CN115562419A CN202211250855.0A CN202211250855A CN115562419A CN 115562419 A CN115562419 A CN 115562419A CN 202211250855 A CN202211250855 A CN 202211250855A CN 115562419 A CN115562419 A CN 115562419A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention discloses a quick-response low-dropout linear voltage stabilizing circuit which comprises an error amplifier, a push-pull circuit, a PMOS (P-channel metal oxide semiconductor) adjusting transistor and an output circuit, wherein one end of the error amplifier is connected with a power supply voltage, the other end of the error amplifier is grounded, one end of the push-pull circuit is connected with the power supply voltage, the other end of the push-pull circuit is grounded, a first input end of the error amplifier is connected with a drain electrode of the PMOS adjusting transistor, a second input end of the error amplifier is connected with a reference voltage, a first output end of the error amplifier is connected with a first input end of the push-pull circuit, a second output end of the error amplifier is connected with a second input end of the push-pull circuit, an output end of the push-pull circuit is connected with a grid electrode of the PMOS adjusting transistor and inputs output voltage, a source electrode of the PMOS adjusting transistor is connected with the power supply voltage, a drain electrode of the PMOS adjusting transistor is connected with an input end of the output circuit, and an output end of the output circuit is grounded. The scheme can improve the output current of the low dropout linear voltage stabilizing circuit and reduce the overshoot and dive voltage and the recovery time during transient response.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a low dropout linear voltage regulator circuit with quick response.
Background
A Low Dropout Regulator (LDO) circuit is a buck dc linear Regulator. With the development of System On Chip (Soc) technology, low dropout linear voltage regulator circuits are widely used in computer, communication, instrumentation, consumer electronics, camera monitoring, and other industries.
The conventional LDO circuit has large overshoot and depression voltage, long recovery time and poor transient response capability. Referring to FIG. 1, a basic structure diagram of a conventional low dropout linear voltage regulator circuit is shown. In fig. 1, the LDO circuit is a single-loop negative feedback system including an error amplifier EA, a buffer stage buffer, a PMOS regulator transistor MP, a voltage division feedback network, an output circuit, and a miller compensation circuit. The voltage division feedback network comprises a first resistor R 1 A second resistor R 2 First resistance R 1 And a second resistor R 2 Form a voltage dividing unit, dividing voltage V fb Is fed back to the positive input terminal of the error amplifier EA, the negative input terminal of which receives the reference voltage V ref . The output circuit is composed of an output resistor R load And an output capacitor C L And (4) forming. The Miller compensation circuit comprises a compensation resistor R c And a compensation capacitor C c The compensation circuit is used for compensating the pole of the output end of the error amplifier EA and the pole of the drain electrode of the PMOS adjusting transistor MP, so that the feedback loop can be stable under various load conditions. When the load of the LDO without the off-chip capacitor changes, no additional energy storage element provides instantaneous current compensation for the load, and the output voltage is completely adjusted by the PMOS adjusting transistor, so that the overshoot and the undershoot voltage of the output voltage can be greatly influenced by the response speed of the PMOS adjusting transistor. In addition, in order to make the LDO circuit have sufficient driving capability so as to be able to output a large current of 500mA, the size of the PMOS adjustment transistor is generally large, and the larger PMOS adjustment transistor has a larger gate parasitic capacitance, which requires a larger current to charge and discharge the gate capacitance of the PMOS adjustment transistor, so as to achieve better transient response characteristics. In summary, the conventional LDO circuit shown in fig. 1 has the disadvantages of large overshoot voltage, large depression voltage, and large recovery time under the condition of no off-chip capacitor and large output current, and thus cannot be used in computers, communications, instruments and meters, and consumer electronicsThe system is used in industries such as son, camera monitoring and the like.
Disclosure of Invention
The invention aims to solve the technical problem that the low dropout linear voltage stabilizing circuit with quick response is provided aiming at the defects of the prior art, the scheme can improve the output current of the low dropout linear voltage stabilizing circuit and reduce the overshoot, the dive voltage and the recovery time in transient response.
The technical scheme adopted by the invention for solving the technical problems is as follows: a low dropout linear voltage stabilizing circuit with fast response comprises an error amplifier, a push-pull circuit, a PMOS adjusting transistor and an output circuit, wherein one end of the error amplifier is connected with a power supply voltage, the other end of the error amplifier is grounded, one end of the push-pull circuit is connected with the power supply voltage, the other end of the push-pull circuit is grounded, a first input end of the error amplifier is connected with a drain electrode of the PMOS adjusting transistor, a second input end of the error amplifier is connected with a reference voltage, a first output end of the error amplifier is connected with a first input end of the push-pull circuit, a second output end of the error amplifier is connected with a second input end of the push-pull circuit, an output end of the push-pull circuit is connected with a grid electrode of the PMOS adjusting transistor and inputs and outputs voltage, a source electrode of the PMOS adjusting transistor is connected with the power supply voltage, a drain electrode of the PMOS adjusting transistor is connected with an input end of the output circuit, and an output end of the output circuit is grounded.
Preferably, the error amplifier comprises a PMOS cross-coupled pair, a common source PMOS amplifier tube, an input differential pair circuit, a tail current source and an NMOS current mirror, the PMOS cross-coupled pair comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, the common source PMOS amplifier tube comprises a fifth PMOS transistor and a sixth PMOS transistor, the input differential pair circuit comprises a seventh NMOS transistor and an eighth NMOS transistor, the tail current source comprises a ninth NMOS transistor and a tenth NMOS transistor, the NMOS current mirror comprises an eleventh NMOS transistor and a twelfth NMOS transistor, sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth NMOS transistor are respectively connected with a power voltage, sources of the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are respectively grounded, a gate and a drain of the first PMOS transistor are respectively connected with a gate of the second PMOS transistor, the drain of the first PMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the seventh NMOS transistor, and the drain of the third PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the sixth PMOS transistor, and the drain of the eighth NMOS transistor, the gate of the third PMOS transistor is connected to the gate and the drain of the fourth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the eleventh NMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the twelfth NMOS transistor and the gate, the gate of the twelfth NMOS transistor is the first output terminal of the error amplifier, the gate of the seventh NMOS transistor is the second input terminal of the error amplifier, the gate of the seventh NMOS transistor is input with a reference voltage, and the source of the seventh NMOS transistor is connected to the drain of the tenth NMOS transistor, the drain of the seventh NMOS transistor, the drain of the eighth NMOS transistor, and the drain of the seventh NMOS transistor, the source electrode of the eighth NMOS tube is connected, the grid electrode of the eighth NMOS tube is the first input end of the error amplifier, the grid electrode and the drain electrode of the ninth NMOS tube are respectively externally connected with a current source, the grid electrode of the tenth NMOS tube is connected, the grid electrode of the eleventh NMOS tube is the second output end of the error amplifier, and the grid electrode of the eleventh NMOS tube is respectively connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixteenth NMOS tube and the second input end of the push-pull circuit. The low dropout linear voltage stabilizing circuit adopts a PMOS cross coupling pair as a load of an error amplifier, the cross coupling pair consisting of a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube forms a positive feedback structure, and an alternating negative resistance is formed due to positive feedback, so that the first PMOS tube and the fourth PMOS tube are in positive transconductance, the second PMOS tube and the third PMOS tube are in negative transconductance, and in addition, the absolute value of the transconductance of the first PMOS tube and the fourth PMOS tube is required to be larger than the absolute value of the transconductance of the second PMOS tube and the third PMOS tube, so as to ensure that the error amplifier can normally work in an amplification state. The PMOS cross coupling pair can perform impedance conversion of a load well, and pushes a secondary point at the grid end of the sixth PMOS tube to a high frequency position, so that the integral stability of the low dropout linear voltage regulator circuit is realized well.
Preferably, the push-pull circuit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth NMOS transistor and a sixteenth NMOS transistor, where the source electrodes of the thirteenth PMOS transistor and the fourteenth PMOS transistor are respectively connected to a power supply voltage, the source electrodes of the fifteenth NMOS transistor and the sixteenth NMOS transistor are respectively grounded, the gate and the drain electrode of the thirteenth PMOS transistor are respectively connected to the gate of the fourteenth PMOS transistor, the drain electrode of the thirteenth PMOS transistor is connected to the drain electrode of the fifteenth NMOS transistor, the drain electrode of the fourteenth PMOS transistor is connected to the drain electrode of the sixteenth NMOS transistor, the gate of the fifteenth NMOS transistor is the first input end of the push-pull circuit, the gate of the fifteenth NMOS transistor is connected to the drain electrode of the twelfth NMOS transistor, the gate of the sixteenth NMOS transistor is connected to the gate of the eleventh NMOS transistor, and the drain electrode of the sixteenth NMOS transistor is the output end of the push-pull circuit.
Preferably, the output circuit includes a load resistor and a load capacitor connected in parallel, one end of the load resistor is connected to the drain of the PMOS adjustment transistor, and the other end is grounded, and one end of the load capacitor is connected to the drain of the PMOS adjustment transistor, and the other end is grounded.
Compared with the prior art, the invention has the following advantages: the low dropout linear voltage stabilizing circuit adopts the push-pull circuit, the push-pull circuit has the characteristics of current filling and current pulling, and can amplify two paths of current output by the error amplifier in the same proportion, so that the grid end parasitic capacitor of the PMOS adjusting transistor is rapidly charged and discharged, better transient response is realized, the output current is improved, and overshoot, depression voltage and recovery time during transient response are reduced.
Drawings
FIG. 1 is a basic structure diagram of a conventional low dropout linear voltage regulator circuit;
FIG. 2 is a schematic diagram of a fast-response low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 3 illustrates transient response performance of a conventional low dropout linear voltage regulator circuit;
FIG. 4 illustrates transient response performance of the low dropout linear voltage regulator circuit of FIG. 2;
fig. 5 is a combined view of fig. 3 and fig. 4.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The low dropout linear voltage regulator circuit with fast response of the embodiment has a schematic structure shown in fig. 2, and comprises an error amplifier, a push-pull circuit, a PMOS regulator transistor M17 and an output circuit, wherein one end of the error amplifier is connected with a power supply voltage V DD The other end is grounded, and one end of the push-pull circuit is connected with a power supply voltage V DD The other end is grounded, the first input end of the error amplifier is connected with the drain electrode of a PMOS adjusting transistor M17, and the second input end of the error amplifier is connected with a reference voltage V ref The first output end of the error amplifier is connected with the first input end of the push-pull circuit, the second output end of the error amplifier is connected with the second input end (grid of M16) of the push-pull circuit, the output end of the push-pull circuit is connected with the grid of the PMOS adjusting transistor M17, and the output voltage V is input and output OUT The source of the PMOS regulation transistor M17 is connected to the supply voltage V DD The drain of the PMOS regulator transistor M17 is connected to the input of the output circuit, and the output of the output circuit is grounded.
In this embodiment, the error amplifier includes a PMOS cross-coupled pair, a common-source PMOS amplifier transistor, an input differential pair circuit, a tail current source and an NMOS current mirror, the PMOS cross-coupled pair includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3 and a fourth PMOS transistor M4, the common-source PMOS amplifier transistor includes a fifth PMOS transistor M5 and a sixth PMOS transistor M6, the input differential pair circuit includes a seventh NMOS transistor M7 and an eighth NMOS transistor M8, the tail current source includes a ninth NMOS transistor M9 and a tenth NMOS transistor M10, the NMOS current mirror includes an eleventh NMOS transistor M11 and a twelfth NMOS transistor M12, and the source electrodes of the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the fourth PMOS transistor M4, the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are respectively connected to the PMOS transistor M6Connected to the supply voltage V DD The sources of the ninth NMOS transistor M9, the tenth NMOS transistor M10, the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are grounded, the gate and the drain of the first PMOS transistor M1 are connected to the gate of the second PMOS transistor M2, the drain of the first PMOS transistor M1 is connected to the gate of the fifth PMOS transistor M5, the drain of the seventh NMOS transistor M7 and the drain of the third PMOS transistor M3, the drain of the second PMOS transistor M2 is connected to the drain of the fourth PMOS transistor M4, the gate of the sixth PMOS transistor M6 and the drain of the eighth NMOS transistor M8, the gate of the third PMOS transistor M3 is connected to the gate and the drain of the fourth PMOS transistor M4, the drain of the fifth PMOS transistor M5 is connected to the drain of the eleventh NMOS transistor M11, the drain of the sixth PMOS transistor M6 is connected to the drain of the twelfth NMOS transistor M12 and the gate, the gate of the twelfth PMOS transistor M12 is the first output terminal of the error amplifier, the gate of the seventh NMOS transistor M7 is the second gate of the error amplifier, and the input terminal of the seventh NMOS transistor M7 is the error amplifier ref The source of the seventh NMOS transistor M7 is connected to the drain of the tenth NMOS transistor M10 and the source of the eighth NMOS transistor M8, the gate of the eighth NMOS transistor M8 is the first input terminal of the error amplifier, the gate and the drain of the ninth NMOS transistor M9 are externally connected to a current source, the gate of the tenth NMOS transistor M10 is connected to the gate of the eleventh NMOS transistor M11 is the second output terminal of the error amplifier, and the gate of the eleventh NMOS transistor M11 is connected to the drain of the fifth PMOS transistor M5, the gate of the sixteenth NMOS transistor M16 and the second input terminal of the push-pull circuit.
In this embodiment, the push-pull circuit includes a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, and a sixteenth NMOS transistor M16, and sources of the thirteenth PMOS transistor M13 and the fourteenth PMOS transistor M14 are respectively connected to the power supply voltage V DD The source electrodes of the fifteenth and sixteenth NMOS transistors M15 and M16 are grounded, the gate electrode and the drain electrode of the thirteenth PMOS transistor M13 are connected to the gate electrode of the fourteenth PMOS transistor M14, the drain electrode of the thirteenth PMOS transistor M13 is connected to the drain electrode of the fifteenth NMOS transistor M15, the drain electrode of the fourteenth PMOS transistor M14 is connected to the drain electrode of the sixteenth NMOS transistor M16, the gate electrode of the fifteenth NMOS transistor M15 is the first input terminal of the push-pull circuit, the gate electrode of the fifteenth NMOS transistor M15 is connected to the drain electrode of the twelfth NMOS transistor M12, and the gate electrode of the sixteenth NMOS transistor M16 is connected to the gate electrode of the eleventh NMOS transistor M11And the drain electrode of the sixteenth NMOS transistor M16 is the output end of the push-pull circuit.
In this embodiment, the output circuit includes a load resistor R connected in parallel L And a load capacitor C L Load resistance R L Has one end connected to the drain of the PMOS regulating transistor M17 and the other end grounded, and a load capacitor C L One end of the PMOS transistor M17 is connected to the drain of the PMOS regulator transistor M17, and the other end is grounded.
In this embodiment, the error amplifier is used to output the voltage V OUT And a reference voltage V ref And comparing, amplifying the comparison result, and outputting the amplified result by using double-end current. The push-pull circuit is used as an intermediate stage of the low dropout linear voltage stabilizing circuit and is used for amplifying two paths of current output by the error amplifier in the same proportion and charging and discharging the gate capacitance of the PMOS adjusting transistor M17 so as to drive the PMOS adjusting transistor M17, so that the PMOS adjusting transistor M17 can quickly respond to the change of the load. When the current flowing through the twelfth NMOS transistor M12 is greater than the current flowing through the eleventh NMOS transistor M11, that is, the current flowing through the fourteenth PMOS transistor M14 is greater than the current flowing through the sixteenth NMOS transistor M16, the gate capacitance of the PMOS adjusting transistor M17 is charged. When the current flowing through the twelfth NMOS transistor M12 is smaller than the current flowing through the eleventh NMOS transistor M11, that is, the current flowing through the fourteenth PMOS transistor M14 is smaller than the current flowing through the sixteenth NMOS transistor M16, the gate capacitance of the PMO S adjusting transistor M17 is discharged. The large push-pull circuit current is more favorable for charging and discharging the gate capacitance of the PMOS regulator transistor M17.
In practical applications, it is known that the driving capability of the low dropout linear voltage regulator circuit is proportional to the width-to-length ratio of the PMOS regulator transistor M17. The PMOS regulator transistor M17 in the present invention employs the prior art. The length of the PMOS adjusting transistor M17 adopts the minimum process size, and the larger the width, the larger the area, and the stronger the on-load capability. However, the gate parasitic capacitance of the PMOS regulator transistor M17 is proportional to the area of the MOS transistor constituting the PMOS regulator transistor M17, which means that when the current of the push-pull circuit is not changed, i.e., the charging and discharging current to and from the gate capacitance of the PMOS regulator transistor M17 is not changed, the size of the PMOS regulator transistor M17 is not large, since the charging and discharging time is increased, i.e., the transient response is deteriorated, when the size of the PMOS regulator transistor M17 is increased.
FIG. 3 is a diagram of transient response performance of a conventional linear regulator circuit With low dropout (FIG. 3 is a diagram drawn by software according to the index of the paper, and the paper and the present are ACapacititor-less LDo With Fast-transient Error Amplifier and Push-pull Difference Xin Ming; jia-ha Zhang; chun-qi Zhang; li Hu; yao Qin; shao-wei Zhen; bo Zhang;2018IEEE International Symposium on Circuits and Systems (ISCAS); yeast: 2018 conference paper publication IEEE). In fig. 3 to 5, "ISCAS" corresponds to the transient response performance of the low dropout linear voltage regulator circuit based on the above-mentioned thesis, and "the present design" corresponds to the transient response performance of the low dropout linear voltage regulator circuit with fast response according to the embodiment of the present invention. The low dropout linear voltage stabilizing circuit is superior to the existing low dropout linear voltage stabilizing circuit in the aspects of overshoot voltage, depression voltage, recovery time and the like, and has better transient response performance.
Claims (4)
1. A low dropout linear voltage stabilizing circuit with quick response is characterized by comprising an error amplifier, a push-pull circuit, a PMOS adjusting transistor and an output circuit, wherein one end of the error amplifier is connected with a power supply voltage, the other end of the error amplifier is grounded, one end of the push-pull circuit is connected with the power supply voltage, the other end of the push-pull circuit is grounded, a first input end of the error amplifier is connected with a drain electrode of the PMOS adjusting transistor, a second input end of the error amplifier is connected with a reference voltage, a first output end of the error amplifier is connected with a first input end of the push-pull circuit, a second output end of the error amplifier is connected with a second input end of the push-pull circuit, an output end of the push-pull circuit is connected with a grid electrode of the PMOS adjusting transistor and inputs and outputs voltage, a source electrode of the PMOS adjusting transistor is connected with the power supply voltage, a drain electrode of the PMOS adjusting transistor is connected with an input end of the output circuit, and an output end of the output circuit is grounded.
2. The fast response low dropout linear voltage regulator according to claim 1, wherein the error amplifier comprises a PMOS cross-coupled pair, a common source PMOS amplifier transistor, an input differential pair circuit, a tail current source and an NMOS current mirror, wherein the PMOS cross-coupled pair comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, the common source PMOS amplifier transistor comprises a fifth PMOS transistor and a sixth PMOS transistor, the input differential pair circuit comprises a seventh NMOS transistor and an eighth NMOS transistor, the tail current source comprises a ninth NMOS transistor and a tenth NMOS transistor, the NMOS current mirror comprises an eleventh NMOS transistor and a twelfth NMOS transistor, the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth NMOS transistor are connected to a power supply voltage, the sources of the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are grounded, the drains of the PMOS transistors are connected to the ground, the first drain and the second drain of the PMOS transistor are connected to the sixth drain of the sixth PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor, the sixth NMOS and the drain of the sixth NMOS are connected to the drain of the sixth NMOS, the error amplifier is connected to the drain of the sixth PMOS cross-coupled to the sixth PMOS transistor, the drain of the sixth PMOS transistor, the error amplifier, the drain of the error amplifier is connected to the sixth NMOS, the drain of the sixth PMOS transistor, the sixth NMOS transistor, the drain of the sixth NMOS, the drain and the drain of the sixth NMOS transistor is connected to the drain of the fifth NMOS, the drain of the fifth NMOS transistor, the fifth NMOS transistor is connected to the sixth NMOS, the drain of the error amplifier, the grid electrode of the seventh NMOS tube is used for inputting reference voltage, the source electrode of the seventh NMOS tube is respectively connected with the drain electrode of the tenth NMOS tube and the source electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is the first input end of the error amplifier, the grid electrode and the drain electrode of the ninth NMOS tube are respectively externally connected with a current source, the grid electrode of the tenth NMOS tube is connected, the grid electrode of the eleventh NMOS tube is the second output end of the error amplifier, and the grid electrode of the eleventh NMOS tube is respectively connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixteenth NMOS tube and the second input end of the push-pull circuit.
3. The fast response low dropout linear voltage regulator circuit according to claim 2, wherein the push-pull circuit comprises a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth NMOS transistor and a sixteenth NMOS transistor, wherein the sources of the thirteenth PMOS transistor and the fourteenth PMOS transistor are respectively connected to a power supply voltage, the sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor are respectively grounded, the gate and the drain of the thirteenth PMOS transistor are respectively connected to the gate of the fourteenth PMOS transistor, the drain of the thirteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor, the drain of the fourteenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor, the gate of the fifteenth NMOS transistor is the first input terminal of the push-pull circuit, the gate of the fifteenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, the gate of the sixteenth NMOS transistor is connected to the gate of the eleventh NMOS transistor, and the drain of the sixteenth NMOS transistor is the output terminal of the push-pull circuit.
4. The fast response low dropout linear voltage regulator circuit of claim 3, wherein said output circuit comprises a load resistor and a load capacitor connected in parallel, one end of said load resistor is connected to the drain of said PMOS regulator transistor, the other end is grounded, one end of said load capacitor is connected to the drain of said PMOS regulator transistor, the other end is grounded.
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| CN202211250855.0A CN115562419A (en) | 2022-10-13 | 2022-10-13 | Quick-response low dropout linear voltage stabilizing circuit |
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| CN202211250855.0A CN115562419A (en) | 2022-10-13 | 2022-10-13 | Quick-response low dropout linear voltage stabilizing circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117742435A (en) * | 2024-02-06 | 2024-03-22 | 深圳市顾邦半导体科技有限公司 | Linear voltage stabilizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117742435A (en) * | 2024-02-06 | 2024-03-22 | 深圳市顾邦半导体科技有限公司 | Linear voltage stabilizer |
| CN117742435B (en) * | 2024-02-06 | 2024-05-17 | 深圳市顾邦半导体科技有限公司 | Linear voltage stabilizer |
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