CN115549661A - Circuit and method for outputting PWM signal - Google Patents
Circuit and method for outputting PWM signal Download PDFInfo
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Abstract
The application relates to a circuit and a method for outputting PWM signals, which belong to the technical field of power electronics, and the circuit comprises: the processor is used for receiving and responding to the starting signal, clearing and starting the counter; the integrating circuit is used for receiving and responding to the starting signal, acquiring a direct-current voltage signal to be converted, and performing integration operation on the direct-current voltage signal to obtain and output a response voltage signal; the comparison circuit is used for receiving the response voltage signal and the preset voltage threshold value and outputting a stop signal according to the comparison result of the voltage value of the response voltage signal and the preset voltage threshold value; the processor also receives and responds to the stop signal, stops the counter and outputs the PWM signal with the corresponding duty ratio according to the count value when the counter stops. The method and the device only need two I/O ports of the processor and are respectively used for receiving the starting signal and the stopping signal, occupation of the I/O ports of the processor is reduced to a greater extent, and I/O port resources of the processor are saved.
Description
Technical Field
The present disclosure relates to power electronics technologies, and in particular, to a circuit and a method for outputting a PWM signal.
Background
The radio frequency plasma operation system is a new generation low temperature plasma operation system, can be used for soft tissue dissection, excision, ablation, hemostasis and drying of surgical operations, and can be matched with an endoscope system to carry out intracavity operations or be matched with an imaging system to carry out interventional therapy.
At present, when a radio frequency plasma surgery system works, direct current voltage needs to be converted into alternating current pulses, because the radio frequency plasma surgery system usually has a plurality of gears, each gear corresponds to a direct current voltage value, in order to control the power of the alternating current pulses, the direct current voltage value needs to be collected, the direct current voltage value is input into a processor after being subjected to A/D conversion, the processor simulates and outputs PWM signals according to the collected direct current voltage value, the duty ratio of the alternating current pulses is controlled by the PWM signals, and therefore the control of the power of the alternating current pulses is achieved.
In view of the above-mentioned related technologies, the inventor found that, as the digital output pins of the ADC chip increase with the increase of the conversion precision of the ADC chip, for example, 8 output pins of D0-D7 are provided for 8-bit a/D converter ADC0809, and 12 output pins of DB0-DB11 are provided for 12-bit a/D converter AD574A, the a/D conversion needs to occupy more I/O ports of the processor, which results in waste of I/O port resources of the processor.
Disclosure of Invention
In order to save I/O port resources of a processor, the application provides a circuit and a method for outputting a PWM signal.
In a first aspect, the present application provides a circuit for outputting a PWM signal, which adopts the following technical solution.
A circuit for outputting a PWM signal, comprising:
the processor is used for receiving and responding to the starting signal, clearing and starting the counter;
the integration circuit is used for receiving and responding to the starting signal, acquiring a direct-current voltage signal to be converted, and performing integration operation on the direct-current voltage signal to obtain and output a response voltage signal;
the comparison circuit is used for receiving the response voltage signal and a preset voltage threshold value and outputting a stop signal according to a comparison result of the voltage value of the response voltage signal and the preset voltage threshold value;
the processor also receives and responds to the stop signal, stops counting of the counter and outputs PWM signals with corresponding duty ratios according to the count value when the counter stops.
By adopting the technical scheme, after the starting signal is received, the processor starts the function of the counter, clears the counter and starts counting from zero; meanwhile, after acquiring a direct-current voltage signal to be converted, the integrating circuit outputs a ramp waveform which linearly changes along with time, wherein the ramp waveform is a response voltage signal of the direct-current voltage signal under the integrating circuit; because the voltage value of the response voltage signal increases along with time, when the response voltage signal is greater than the preset voltage threshold, the level of the output end of the comparison circuit is turned over, a stop signal is output, and the processor stops counting of the counter after receiving the stop signal; the larger the voltage value of the direct current voltage signal is, the larger the slope of the ramp waveform is, and the response voltage signal can be larger than a preset voltage threshold value in a smaller counting time, so that the voltage value of the direct current voltage signal is determined through the counting value of the counter, the processor simulates to output a PWM signal corresponding to the voltage value, the duty ratio of the alternating current pulse is controlled, and the power of the alternating current pulse is controlled. The processor responds to the starting signal to start the function of the counter, responds to the stopping signal to stop the counting of the counter, and simulates and outputs the corresponding PWM signal according to the counting value of the counter, so that only two I/O ports of the processor are needed to receive the starting signal and the stopping signal respectively.
Optionally, the integration circuit further includes a post-stage protection circuit, and the post-stage protection circuit is configured to reduce a voltage amplitude of the response voltage signal.
By adopting the technical scheme, the amplitude of the response voltage signal output by the integrating circuit can be increased to be equal to that of the direct-current voltage signal along with time, and due to the fact that the plurality of gears are arranged, the voltage span of the direct-current voltage signal is large, and when the amplitude of the response voltage signal is increased to a certain degree, a rear-stage circuit is easy to damage, so that the voltage amplitude of the response voltage signal is reduced by the rear-stage protection circuit, and system faults caused by damage of the rear-stage circuit are reduced.
Optionally, the integrating circuit includes a first resistor R1 and a capacitor C, one end of the first resistor R1 is configured to receive the dc voltage signal, the other end of the first resistor R1 is connected to one end of the capacitor C, and the other end of the capacitor C is grounded;
one end of the first resistor R1 connected to the capacitor C is used for outputting the response voltage signal.
By adopting the technical scheme, the first resistor R1 and the capacitor C form the RC integrating circuit, the voltage at two ends of the capacitor C can not change suddenly, the voltage at two ends of the capacitor C is gradually increased along with the charging of the capacitor C, the larger the voltage value of the direct-current voltage signal is, the larger the charging current for charging the capacitor C is, the faster the speed of the accumulation of the charges on the capacitor C is, and the faster the voltage increase rate at two ends of the capacitor C is.
Optionally, the post-stage protection circuit includes a second resistor R2, and the second resistor R2 is connected in parallel to two ends of the capacitor C.
By adopting the technical scheme, the first resistor R1 and the second resistor R2 form the series voltage division circuit, so that voltage drop is generated on the first resistor R1, the voltage amplitude of the response voltage signal can be reduced according to the proportion of a voltage division formula, and the situation that the voltage amplitude of the response voltage signal is too large to damage a rear-stage circuit is prevented.
Optionally, the integration circuit includes a third resistor R3 and an inductor L, one end of the inductor L is configured to receive the dc voltage signal, the other end of the inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded;
one end of the inductor L connected to the third resistor R3 is used for outputting the response voltage signal.
By adopting the above technical scheme, the inductor L and the third resistor R3 form an RL integrating circuit, because the current on the inductor L cannot change suddenly, the current on the inductor L increases gradually with the charging of the inductor L, the larger the voltage value of the dc voltage signal is, the larger the charging voltage for charging the inductor L is, the faster the current on the inductor L increases, and the faster the current passes through the third resistor R3, so that the voltage increase rate at the two ends of the third resistor R3 is.
Optionally, the post-stage protection circuit includes a fourth resistor R4, one end of the fourth resistor R4 is connected to the inductor L, and the other end of the fourth resistor R4 is configured to receive the dc voltage signal.
By adopting the technical scheme, the third resistor R3 and the fourth resistor R4 form a series voltage division circuit, so that voltage drop is generated on the fourth resistor R4, the voltage amplitude of the response voltage signal can be reduced according to the proportion of a voltage division formula, and the situation that the voltage amplitude of the response voltage signal is too large and damages a rear-stage circuit is prevented.
Optionally, the comparison circuit includes an operational amplifier a, a first input end of the operational amplifier a is configured to receive the response voltage signal, a second input end of the operational amplifier a is configured to receive a preset reference voltage Vref, and an output end of the operational amplifier a is configured to output the stop signal.
By adopting the technical scheme, the level output by the output end of the operational amplifier depends on the magnitude of the voltage received by the same-direction input end and the reverse-direction input end of the operational amplifier, and when the reference voltage Vref is greater than the response voltage signal, the operational amplifier A outputs a high level or a low level; as the response voltage signal gradually increases, when the reference voltage Vref is less than the response voltage signal, the operational amplifier a outputs a low level or a high level, and the output of the operational amplifier a will flip over time, and in combination with the characteristics of the integrating circuit, the larger the voltage value of the dc voltage signal, the shorter the output of the operational amplifier a will flip over, and the earlier the operational amplifier a can output the stop signal.
Optionally, the processor includes a master CPU.
By adopting the technical scheme, the counter function of the main control CPU is used, only one interrupt input port of the main control CPU is occupied to receive the stop signal, the voltage value of the direct current voltage signal is determined according to the counting of the counter, and therefore the corresponding PWM signal is output.
In a second aspect, the present application provides a method for outputting a PWM signal, which adopts the following technical solution.
A method for outputting a PWM signal, applied to the circuit according to the first aspect, comprising:
receiving and responding to a starting signal, acquiring a direct current voltage signal to be converted, resetting and starting a counter;
acquiring a response voltage signal obtained and output by performing integral operation on the direct current voltage signal under a preset integral model based on the preset integral model;
judging whether the voltage value of the response voltage signal is greater than a preset voltage threshold value, if so, outputting a stop signal;
based on the stop signal, the counter stops counting and outputs the count value of the counter;
and outputting PWM signals with corresponding duty ratios according to the counting values when the counter stops based on a preset output model.
By adopting the technical scheme, after receiving a starting signal, the processor starts the function of the counter, the counter is cleared and starts counting from zero, meanwhile, the preset integration model acquires a direct current voltage signal to be converted, and the output of the preset integration model and the voltage value of the direct current voltage signal have a ramp waveform which linearly changes along with time, wherein the ramp waveform is a response voltage signal of the direct current voltage signal under the integration circuit; the voltage value of the response voltage signal is increased along with time, when the response voltage signal is larger than the preset voltage threshold, the stop signal is output, the processor stops counting of the counter after receiving the stop signal, the larger the voltage value of the direct current voltage signal is, the larger the slope of the slope waveform is, the response voltage signal can be larger than the preset voltage threshold in the smaller counting of the counter, so that the voltage value of the direct current voltage signal is determined through the counting value of the counter, the preset output model outputs the PWM signal corresponding to the voltage value according to the counting value, the duty ratio of the alternating current pulse is controlled, and the power of the alternating current pulse is controlled. The processor only needs to receive the starting signal and the stopping signal, and compared with the method that the ADC chip processor needs to receive 8-bit or 12-bit digital signals, the occupation of the I/O port of the processor is reduced to a greater extent, so that the I/O port resource of the processor is saved.
In a third aspect, the present application provides a radio frequency plasma surgical system, which adopts the following technical solution.
A radio frequency plasma surgical system comprising the circuit of the first aspect described above.
In summary, the present application at least includes the following beneficial effects:
after receiving the starting signal, the processor starts the function of the counter, clears the counter and starts counting from zero; meanwhile, after the integrating circuit acquires the direct-current voltage signal to be converted, a ramp waveform which is linearly changed along with the time with the voltage value of the direct-current voltage signal is output, and the ramp waveform is a response voltage signal of the direct-current voltage signal under the integrating circuit; as the voltage value of the response voltage signal increases along with time, when the response voltage signal is greater than the preset voltage threshold, the level of the output end of the comparison circuit is inverted, a stop signal is output, and the processor stops counting after receiving the stop signal; the larger the voltage value of the direct current voltage signal is, the larger the slope of the ramp waveform is, and the response voltage signal can be larger than a preset voltage threshold value in a smaller counting time, so that the voltage value of the direct current voltage signal is determined through the counting value of the counter, the processor simulates to output a PWM signal corresponding to the voltage value, the duty ratio of the alternating current pulse is controlled, and the power of the alternating current pulse is controlled. The processor responds to the starting signal to start the function of the counter, responds to the stopping signal to stop the counting of the counter, and outputs the corresponding PWM signal according to the counting value of the counter in an analog mode.
Drawings
FIG. 1 is a block diagram of a circuit configuration of an embodiment of the circuit of the present application;
fig. 2 is a schematic diagram illustrating a corresponding relationship among a response voltage signal, a stop signal and a count value under different dc voltage signals according to the present application.
FIG. 3 is a schematic diagram of the overall circuit structure of an embodiment of the circuit of the present application;
FIG. 4 is a schematic diagram of the overall circuit configuration of another embodiment of the circuit of the present application;
FIG. 5 is a flow chart of an embodiment of the method of the present application.
Description of reference numerals: 100. a processor; 200. an integrating circuit; 210. a rear stage protection circuit; 300. a comparison circuit; 400. and a key circuit.
Detailed Description
The present application will be described in further detail with reference to fig. 1-5.
Since the digital output pins of the ADC chip increase with the increase of the conversion accuracy of the ADC chip, the commonly used 8-bit a/D converter outputs 8-bit binary numbers through 8 pins to represent the conversion result, and needs to occupy 8I/O ports of the processor 100. Meanwhile, the input end of the A/D converter is analog quantity, the output end of the A/D converter is digital quantity, and the edge of a digital signal is steep, so that higher harmonics are generated and are easily coupled into an analog circuit, interference is caused on the analog signal, and the control difficulty is increased.
The embodiment of the application provides a circuit for outputting a PWM signal.
A circuit for outputting a PWM signal as shown in fig. 1, comprising: a processor 100 for receiving and responding to the start signal, clearing and starting the counter; the integrating circuit 200 is configured to receive and respond to the start signal, obtain a dc voltage signal to be converted, perform an integrating operation on the dc voltage signal, and obtain and output a response voltage signal; a comparison circuit 300 for receiving the response voltage signal and the preset voltage threshold, and outputting a stop signal according to a comparison result between the voltage value of the response voltage signal and the preset voltage threshold; the processor 100 also receives and responds to the stop signal, stops the counter, and outputs a PWM signal of a corresponding duty ratio according to a count value when the counter is stopped.
It should be noted that the counter is integrated in the processor 100, and meanwhile, the processor 100 further includes an output unit, where a count value-PWM signal duty ratio mapping table is stored in the output unit, and the mapping table includes mapping relationships between different count values and different duty ratios of PWM signals, for example, the duty ratio of the PWM signal mapped when the count value is 60 is 50%, and the duty ratio of the PWM signal mapped when the count value is 80 is 60%.
In this embodiment, after receiving the start signal, the processor 100 starts the counter function, clears the counter, and starts counting from zero; meanwhile, after the integrating circuit 200 acquires the dc voltage signal to be converted, a ramp waveform having a linear change with time with the voltage value of the dc voltage signal is output, and the ramp waveform is a response voltage signal of the dc voltage signal under the integrating circuit 200; as the voltage value of the response voltage signal increases with time, when the response voltage signal reaches the preset voltage threshold, the level of the output end of the comparison circuit 300 is inverted, a stop signal is output, and the processor 100 stops counting after receiving the stop signal; the larger the voltage value of the direct-current voltage signal is, the larger the slope of the ramp waveform is, the response voltage signal can be larger than a preset voltage threshold value within a shorter counting time, so that the smaller the count value of the counter is, the voltage value of the direct-current voltage signal is determined by the count value of the counter, and the processor simulates and outputs a PWM signal corresponding to the voltage value.
As shown in fig. 2, due to the output signal of the integrating circuit 200
And an input signal
There is a functional relationship between:
k is a coefficient determined by parameters of the integrating circuit 200, k is constant for the same integrating circuit 200, and the input direct current voltage signals with different voltages are subjected to direct current voltage signal processing
And, and
the output slopes are different through the same integration circuit 200
、
And
，
，
、
and
and then the voltage is compared with a fixed voltage Vref through a comparison circuit 300, so that stop signals are output at different moments, and the counter stops counting when receiving the stop signals. As can be seen from fig. 2, the larger the amplitude of the dc voltage signal is, the smaller the count value of the counter is, and the voltage value of the dc voltage signal can be determined according to the count value of the counter, thereby outputting a PWM signal corresponding to the duty ratio.
As shown in FIG. 3, processor 100 includes a master CPU, an interrupt input port of which is coupled to an output of compare circuit 300, as an embodiment of processor 100.
In this embodiment, the main control CPU is connected to the key circuit 400, the operator outputs a start signal by pressing a key, the main control CPU receives the start signal, clears and starts the counter of the main control CPU, and receives a stop signal from an interrupt input port of the main control CPU to stop the counter of the main control CPU, and the main control CPU outputs a corresponding PWM signal in an analog manner according to a count value of the counter.
In order to reduce system failure caused by damage to the subsequent stage, the integration circuit 200 further includes a subsequent stage protection circuit 210, and the subsequent stage protection circuit 210 is used to reduce the voltage amplitude of the response voltage signal.
In this embodiment, the amplitude of the response voltage signal output by the integrating circuit 200 may increase with time to be equal to the amplitude of the dc voltage signal, and since there are multiple stages, the voltage span of the dc voltage signal is large, and when the voltage span of the response voltage signal increases to a certain extent, the subsequent circuit is easily damaged, so that the subsequent protection circuit 210 is configured to reduce the voltage amplitude of the response voltage signal, and reduce the system failure caused by the damage of the subsequent circuit.
In one embodiment as the integration circuit 200, the integration circuit 200 includes a first resistor R1 and a capacitor C, one end of the first resistor R1 is used for receiving a direct-current voltage signal, the other end of the first resistor R1 is connected with one end of the capacitor C, and the other end of the capacitor C is grounded; one end of the first resistor R1 connected to the capacitor C is used to output a response voltage signal.
In the above embodiment, the first resistor R1 and the capacitor C form the RC integration circuit 200, since the voltage across the capacitor cannot change abruptly, the voltage across the capacitor C gradually increases as the capacitor C is charged, and according to the RC integration circuit formula:
it is understood that the larger the voltage value of the dc voltage signal is, the larger the charging current for charging the capacitor C becomes, the faster the speed at which the charges are accumulated on the capacitor C becomes, and the faster the rate of increase in the voltage across the capacitor C becomes.
As an embodiment of the rear stage protection circuit 210, the rear stage protection circuit 210 includes a second resistor R2, and the second resistor R2 is connected in parallel to two ends of the capacitor C.
In the above embodiment, the first resistor R1 and the second resistor R2 form a series voltage dividing circuit, so that a voltage drop is generated across the first resistor R1, and thus the voltage amplitude of the response voltage signal can be reduced according to the proportion of the voltage dividing formula, and the voltage amplitude of the response voltage signal is prevented from being too large and damaging the subsequent circuit.
As shown in fig. 4, as another embodiment of the integration circuit 200, the integration circuit 200 includes a third resistor R3 and an inductor L, one end of the inductor L is used for receiving a dc voltage signal, the other end of the inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded; one end of the inductor L connected to the third resistor R3 is used to output a response voltage signal.
By adopting the above technical solution, the inductor L and the third resistor R3 form the RL integrating circuit 200, and since the current in the inductor L cannot change suddenly, the current in the inductor L gradually increases with the charging of the inductor L. And, according to the RL integrating circuit formula:
it can be seen that the larger the voltage value of the dc voltage signal is, the larger the charging voltage for charging the inductor L is, the faster the current increases in the inductor L, and the faster the current passes through the third resistor R3, so that the voltage increase rate at both ends of the third resistor R3 is increased.
As another implementation of the rear stage protection circuit 210, the rear stage protection circuit 210 includes a fourth resistor R4, one end of the fourth resistor R4 is connected to the inductor L, and the other end of the fourth resistor R4 is used for receiving a direct current voltage signal.
In the above embodiment, the third resistor R3 and the fourth resistor R4 form a series voltage dividing circuit, so that a voltage drop is generated across the fourth resistor R4, thereby enabling the voltage amplitude of the response voltage signal to be reduced according to the proportion of the voltage dividing formula, and preventing the voltage amplitude of the response voltage signal from being too large and damaging the subsequent circuit.
As an embodiment of the comparison circuit 300, the comparison circuit 300 includes an operational amplifier a, an inverting input of which is configured to receive the response voltage signal, a non-inverting input of which is configured to receive the preset reference voltage Vref, and an output of which is configured to output the stop signal.
In the above embodiment, since the level of the output of the operational amplifier is determined by the voltages received by the inverting input terminal and the non-inverting input terminal, the operational amplifier a outputs a high level when the reference voltage Vref is greater than the response voltage signal; as the response voltage signal gradually increases, when the reference voltage Vref is less than the response voltage signal, the operational amplifier a outputs a low level, and it can be seen that the output of the operational amplifier a will flip over time, and in combination with the characteristics of the integrating circuit 200, the larger the voltage value of the dc voltage signal is, the shorter the output of the operational amplifier a will flip over, the earlier the operational amplifier a can output the stop signal, and the smaller the count value of the counter.
The embodiment of the application provides a method for outputting a PWM signal.
As shown in fig. 5, a method for outputting a PWM signal, applied to the above circuit, includes:
s100, receiving and responding to a starting signal, acquiring a direct current voltage signal to be converted, resetting and starting a counter;
specifically, the starting signal may be a common input key, or a handle trigger key, a pedal trigger key, or an interactive key of a touchable screen, which is set in accordance with actual requirements, and the like, without limitation, the counter may count the number of received pulses according to the frequency of the preset pulse when receiving the starting signal, and the frequency of the preset pulse may be a clock frequency of the CPU, or may be set manually in accordance with historical experience, for example, 1kHZ, that is, a time interval between rising edges/falling edges of two adjacent pulses is 1ms.
S200, acquiring a response voltage signal which is obtained and output by integrating the direct-current voltage signal under the integral model based on a preset integral model;
specifically, the direct-current voltage signal is converted into a response voltage signal which linearly increases along with time through a preset integral model, the direct-current voltage signal is a fixed voltage value at each gear, and the larger the voltage value is, the larger the rate of increase of the response voltage signal is.
S300, judging whether the voltage value of the response voltage signal is larger than a preset voltage threshold value or not, and if so, outputting a stop signal;
specifically, as the voltage value is larger, the rate of the increase of the response voltage signal along with time is larger, and the time that the voltage value of the response voltage signal is larger than the preset voltage threshold is shorter, that is, the number of pulse counts of the counter is smaller, wherein the preset voltage threshold is manually set in combination with historical experience.
S400, based on the stop signal, stopping counting by the counter and outputting the count value of the counter;
specifically, the count value of the counter can reflect the time when the response voltage signal increases to be greater than the preset voltage threshold value, and then reflect the voltage value of the direct current voltage signal.
And S500, outputting the PWM signal with the corresponding duty ratio according to the counting value when the counter stops based on a preset output model.
Specifically, according to the count value of the counter, a preset output model outputs a PWM signal, the count value determines the duty ratio of the output PWM signal, and the output model comprises a corresponding relation between the count value and the duty ratio of the PWM signal, wherein the corresponding relation is set by artificially combining historical experience.
In the above embodiment, after receiving the start signal, the processor 100 starts the counter function, the counter is cleared and starts counting from zero, and meanwhile, the preset integration model obtains the dc voltage signal to be converted, and outputs a ramp waveform having a linear change with time according to the integration model, where the ramp waveform is a response voltage signal of the dc voltage signal under the integration circuit 200; the voltage value of the response voltage signal is increased along with time, when the response voltage signal is greater than the preset voltage threshold, the stop signal is output, the counter stops counting, and the processor 100 stops counting after receiving the stop signal. The processor 100 only needs to receive the starting signal and the stopping signal, and compared with the method that the ADC chip processor 100 needs to receive 8-bit or 12-bit digital signals, the occupation of the I/O port of the processor is reduced to a greater extent, and therefore the I/O port resource of the processor is saved.
The embodiment of the application provides a radio frequency plasma surgery system.
A radio frequency plasma surgical system comprises the circuit.
In the embodiment, the circuit outputs PWM signals with different duty ratios according to direct current voltage signals with different amplitudes, the PWM signals convert the direct current voltage into alternating current pulses, the power of the alternating current pulses is controlled according to different duty ratios of the PWM signals, the conversion from the direct current voltage to the alternating current pulses is completed, the conversion precision (the smaller the counting time, the higher the precision) and the conversion speed are controllable, and the circuit can be successfully applied to a radio frequency plasma surgery control system.
It should be noted that, in the foregoing embodiments, descriptions of the respective embodiments have respective emphasis, and reference may be made to relevant descriptions of other embodiments for parts that are not described in detail in a certain embodiment.
The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.
Claims (10)
1. A circuit for outputting a PWM signal, characterized by: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
a processor (100) for receiving and responding to a start signal, clearing and starting a counter;
the integrating circuit (200) is used for receiving and responding to the starting signal, acquiring a direct current voltage signal to be converted, and carrying out integration operation on the direct current voltage signal to obtain and output a response voltage signal;
the comparison circuit (300) is used for receiving the response voltage signal and a preset voltage threshold value and outputting a stop signal according to the comparison result of the voltage value of the response voltage signal and the preset voltage threshold value;
the processor (100) also receives and responds to the stop signal, stops counting of the counter, and outputs a PWM signal with a corresponding duty ratio according to a count value when the counter stops.
2. A circuit for outputting a PWM signal according to claim 1, wherein: the integration circuit (200) further comprises a post-protection circuit (210), wherein the post-protection circuit (210) is used for reducing the voltage amplitude of the response voltage signal.
3. A circuit for outputting a PWM signal according to claim 2, wherein: the integration circuit (200) comprises a first resistor R1 and a capacitor C, one end of the first resistor R1 is used for receiving the direct-current voltage signal, the other end of the first resistor R1 is connected with one end of the capacitor C, and the other end of the capacitor C is grounded;
one end of the first resistor R1 connected with the capacitor C is used for outputting the response voltage signal.
4. A circuit for outputting a PWM signal according to claim 3, wherein: the post-stage protection circuit (210) includes a second resistor R2, and the second resistor R2 is connected in parallel to both ends of the capacitor C.
5. A circuit for outputting a PWM signal according to claim 2, wherein: the integrating circuit (200) comprises a third resistor R3 and an inductor L, wherein one end of the inductor L is used for receiving the direct-current voltage signal, the other end of the inductor L is connected with one end of the third resistor R3, and the other end of the third resistor R3 is grounded;
one end of the inductor L connected to the third resistor R3 is used for outputting the response voltage signal.
6. The circuit according to claim 5, wherein: the rear stage protection circuit (210) includes a fourth resistor R4, one end of the fourth resistor R4 is connected to the inductor L, and the other end of the fourth resistor R4 is configured to receive the dc voltage signal.
7. A circuit for outputting a PWM signal according to any one of claims 1 to 6, wherein: the comparison circuit (300) comprises an operational amplifier A, wherein a first input end of the operational amplifier A is used for receiving the response voltage signal, a second input end of the operational amplifier A is used for receiving a preset reference voltage Vref, and an output end of the operational amplifier A is used for outputting the stop signal.
8. A circuit for outputting a PWM signal according to claim 7, wherein: the processor (100) includes a master CPU.
9. A method for outputting a PWM signal, applied to the circuit of any one of claims 1-8, wherein: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
receiving and responding to a starting signal, acquiring a direct current voltage signal to be converted, resetting and starting a counter;
acquiring a response voltage signal obtained and output by performing integral operation on the direct current voltage signal under a preset integral model based on the preset integral model;
judging whether the voltage value of the response voltage signal is greater than a preset voltage threshold value, if so, outputting a stop signal;
based on the stop signal, the counter stops counting and outputs the count value of the counter;
and outputting PWM signals with corresponding duty ratios according to the counting values when the counter stops based on a preset output model.
10. A radio frequency plasma surgical system, characterized by: comprising a circuit as claimed in any one of claims 1-8.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1292944A (en) * | 1998-02-11 | 2001-04-25 | 鲍尔德西内有限公司 | PWM controller for use with open loop DC to AC converter |
| CN1822506A (en) * | 2006-02-10 | 2006-08-23 | 中控科技集团有限公司 | Integrating A/D convertion method and its A/D converter |
| JP2006228685A (en) * | 2005-02-21 | 2006-08-31 | Matsushita Electric Works Ltd | Discharge lamp lighting device and lighting device |
| CN113228828A (en) * | 2018-11-26 | 2021-08-06 | 上海晶丰明源半导体股份有限公司 | Control circuit, driving system, chip, control method and driving method |
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2022
- 2022-11-29 CN CN202211502908.3A patent/CN115549661B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1292944A (en) * | 1998-02-11 | 2001-04-25 | 鲍尔德西内有限公司 | PWM controller for use with open loop DC to AC converter |
| JP2006228685A (en) * | 2005-02-21 | 2006-08-31 | Matsushita Electric Works Ltd | Discharge lamp lighting device and lighting device |
| CN1822506A (en) * | 2006-02-10 | 2006-08-23 | 中控科技集团有限公司 | Integrating A/D convertion method and its A/D converter |
| CN113228828A (en) * | 2018-11-26 | 2021-08-06 | 上海晶丰明源半导体股份有限公司 | Control circuit, driving system, chip, control method and driving method |
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