CN115549463A - Single-phase power factor correction control method for regulating input impedance based on multiplier voltage - Google Patents

Single-phase power factor correction control method for regulating input impedance based on multiplier voltage Download PDF

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CN115549463A
CN115549463A CN202211299759.5A CN202211299759A CN115549463A CN 115549463 A CN115549463 A CN 115549463A CN 202211299759 A CN202211299759 A CN 202211299759A CN 115549463 A CN115549463 A CN 115549463A
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voltage
control
multiplier
loop
power factor
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陈健斌
杨程喻
邹建俊
陈凯
徐宇峰
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Guangdong Titan Intelligent Power Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/24—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to undervoltage or no-voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The invention discloses and provides a single-phase power factor correction control method based on multiplier voltage regulation input impedance, which has the advantages of low manufacturing cost, simple and convenient implementation, reduction of power factor deterioration, capability of enabling the input impedance in the whole operation process to be a constant and capability of improving the safety and the reliability of a circuit system. The invention is suitable for the technical field of power electronics.

Description

Single-phase power factor correction control method for regulating input impedance based on multiplier voltage
Technical Field
The invention relates to a single-phase power factor correction control method for regulating input impedance based on multiplier voltage.
Background
The PFC (Power Factor Correction) is a Power electronic technology that corrects a distorted current into a sinusoidal current and makes the current in phase with a voltage, thereby making a Power Factor close to 1. There are a variety of circuit topologies and methods for implementing PFC, which need to be selected according to the specific application. Among them, single-phase power factor correction (boots PFC) is a common topology, and is commonly used in Uninterruptible Power Supplies (UPS) and large-scale household appliances.
Typical boots PFC implementations require five different sampling points (some schemes may be simplified to three, i.e. the voltage and current at the same node are sampled simultaneously), not only the AC voltage V before rectification AC And current I AC The inductor current I is also sampled L And rectified input voltage V in Finally, the output voltage V needs to be sampled out 。
The control loop adopted by a typical boots PFC is a typical double-loop structure (consisting of a voltage outer loop and a current inner loop), and the voltage single-loop control is easy to design and analyze, but has slow response speed and infinite current function. The current loop can enhance the stability of the circuit, has high response speed, can eliminate low-frequency waves generated in a single voltage mode, and has the capacity of limiting overcurrent. However, such dual-loop control has relatively complex circuit implementation (or software implementation), is inconvenient to debug, has a power factor basically depending on the sampling precision before rectification and the performance of the multiplier, and the performance of the control loop, and is difficult to adjust to optimal parameters, and in large-scale production, the production process adjustment for stable production requires a long time; in addition, functions such as soft start, under (over) power protection, over-temperature protection, etc. require additional circuitry and programming to implement.
In summary, conventional boots PFCs have several disadvantages: 1. the traditional boots PFC solution requires more devices, is difficult to reduce the manufacturing cost, and is difficult to implement the PFC; 2. the traditional boots PFC solution needs better sampling precision and loop performance to reduce the degradation of the power factor, which leads to the rise of cost and the difficulty of loop debugging; 3. conventional boots PFC solutions require an additional detection mechanism to prevent under (over) power from occurring in the circuit.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a single-phase power factor correction control method for regulating input impedance based on multiplier voltage, which has the advantages of low manufacturing cost, simple and convenient implementation, reduction of power factor deterioration, constant input impedance in the whole operation process and capability of improving the safety and the reliability of a circuit system.
The invention comprises the following steps:
A. collecting inductive current I by sampling circuit L An output voltage V out And an input voltage V in Three parameters;
B. respectively passing the inductive currents I through control loops L The output voltage V out And said input voltage V in Calculating to obtain the control value I of the inductive current ramp And multiplier voltage V m ；
C. The control value of the inductor current I ramp And the multiplier voltage V m And adding the signals in the control loop and outputting the signals to a PWM generating terminal, and generating corresponding driving signals in the PWM generating terminal.
The control loop is a parallel double loop and comprises a voltage loop and a multiplier voltage algorithm loop.
The voltage loop passes through the output voltage V out Calculating the difference value of the target output voltage and adjusting the output quantity, simultaneously judging the position of the zero crossing point of the input alternating voltage by phase discrimination, and finally outputting the inductive current control value I related to inductive current control after being combined with the inductive current IL for calculation ramp 。
The multiplier voltage algorithm loop is used for the calculation of the overvoltage protection voltage once the input voltage V is applied in When the current is not in the range of the limit value, the current can be automatically shut down; the multiplier voltage algorithm loop can also be based on the compensated inductor current I L And a control voltage V control Calculating the multiplier voltage V m 。
The PWM generating end sequentially comprises a ramp period trigger signal, an integrator,Comparator and SR flip-flop, the inductive current control value I ramp And said multiplier voltage V m And after the addition calculation is carried out at the last end of the control loop, the control loop enters the integrator after zero division, and finally a driving signal is sent out through the Q end of the SR trigger.
In step B, the inductor current I L After the calculation of the two types of compensators, the two types of compensators are respectively input into the voltage ring and the multiplier voltage algorithm ring, and the transfer function of the two types of compensators is as follows:
Figure BDA0003904076060000031
in step B, the input voltage V in Obtaining an over-current protection voltage V after passing through a first-order filter bo Said overvoltage protection voltage V bo The calculation formula of (2) is as follows:
Figure BDA0003904076060000032
in step B, the overvoltage protection voltage V bo The control voltage V is within the multiplier voltage algorithm loop control The multiplier voltage V is obtained after the combination calculation m Wherein the control voltage V control And an output voltage V out The relation of (A) is as follows:
Figure BDA0003904076060000033
the multiplier voltage V m The calculation formula of (1) is as follows:
Figure BDA0003904076060000034
has the advantages that: the invention reduces the number of external components to the utmost extent, and the number of sampling points is less than that of the common single-phase power factor correction technology (boots PFC)The cost is reduced, and the implementation process of PFC is greatly simplified; the invention adopts a parallel double-loop control loop structure, can control the inductive current and the alternating voltage V without sampling the rectification front end AC The same frequency and the same phase; the invention reduces the deterioration of the rectified sine wave input voltage to the power factor through the calculation of the multiplier loop, so that the input impedance in the whole operation process is a constant; the control loop integrates an under (over) power protection mechanism, so that the safety and the reliability of a circuit system are improved; according to the invention, the effective compensator is designed to inhibit the influence of the ripple of the output voltage on the control loop, so that the performance of the circuit is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional typical boots PFC system;
FIG. 2 is a control block diagram of a conventional typical boots PFC system;
FIG. 3 is a circuit schematic of the power correction circuit of the present invention;
FIG. 4 is a control block diagram of the present invention;
fig. 5 is a waveform diagram of the PFC modulation principle of the present invention;
FIG. 6 is a multiplier voltage timing diagram of the present invention;
FIG. 7 is a schematic overall waveform diagram of an embodiment of the present invention;
FIG. 8 is an enlarged schematic diagram of a waveform diagram of an embodiment of the present invention.
Detailed Description
As shown in fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, the present invention includes the steps of:
A. collecting inductive current I by sampling circuit L An output voltage V out And an input voltage V in Three parameters, in this particular embodiment, the sampling circuit is a power correction circuit;
B. respectively passing the inductive currents I through control loops L The output voltage V out And the input voltage V in Calculating to obtain an inductive current control value I ramp And a multiplier voltage V m ；
C. The control value of the inductor current I ramp And the multiplier voltage V m And adding the signals in the control loop and outputting the signals to a PWM generating terminal, and generating corresponding driving signals in the PWM generating terminal.
The control loop is a parallel double loop and comprises a voltage loop and a multiplier voltage algorithm loop.
The voltage loop passes through the output voltage V out Calculating the difference value of the target output voltage, adjusting the output quantity, simultaneously judging the position of the zero crossing point of the input alternating voltage by phase discrimination, and finally comparing the position with the inductive current I L Outputting the inductance current control value I related to the inductance current control after combining calculation ramp 。
The multiplier voltage algorithm loop is used for the calculation of the overvoltage protection voltage once the input voltage V is applied in When the current is not in the range of the limit value, the current can be automatically shut down; the multiplier voltage algorithm loop can also be based on the compensated inductor current I L And a control voltage V control Calculating the multiplier voltage V m 。
The PWM generating end sequentially comprises a ramp wave periodic trigger signal, an integrator, a comparator and an SR trigger, and the inductive current control value I ramp And said multiplier voltage V m And after the addition calculation is carried out at the last end of the control loop, the control loop enters the integrator after zero division, and finally a driving signal is sent out through the Q end of the SR trigger.
As shown in fig. 3, the circuit topology used in the present invention is a boost PFC, which is a single-phase boost PFC topology. The invention is basically the same as the typical boots PFC system. In practical applications, some additional driving/bootstrap circuits are added without changing the basic principle, as shown in fig. 1 and fig. 3, compared with a typical boots PFC circuit, the power correction circuit of the present invention has one more diode D above the inductor Lm in order to reduce the impact of the surge voltage on the capacitor.
As shown in fig. 4, in the hardware scheme of the control block diagram of the present invention, it is not necessary to sample the parameters before rectification, and the ac current I before rectification can be also sampled AC Control is performed to correct the distorted current to a sinusoidal current and to match it with the AC voltage V AC In phase. The number of samples is two less than the typical method (one in some scenarios).
The parameter to be sampled of the invention is I L An output voltage V out And an input voltage V in Three parameters, the concrete implementation method of the sampling circuit does not influence the implementation process of the invention (some low-cost schemes can reduce the inductive current I L And an input voltage V in Read out by a sampling conditioning circuit on the same node and then respectively calculate by a software method).
The control process of the present invention is described below. The beginning of the control loop of the invention is the inductor current I L Entering a two-type compensator, the compensator has three control parameters, and the transfer function is as follows:
Figure BDA0003904076060000061
this is a typical type two compensator with a low frequency zero and a pole, which is used to reduce the ripple of the output voltage into the control loop (the ripple frequency is 100Hz for a 50Hz application), and the values of the three parameters of this type two compensator can be determined by simply determining the values of the frequency of the zero and pole to be compensated.
The control loop of the invention is a parallel double-loop design, and the algorithm loops on both sides are in an additive relationship. One side is a voltage ring, the functions of which are two, one is used for calculating the difference value of target output voltage and adjusting output quantity, and the other side is a common PI link; and secondly, judging the position of the zero crossing point of the input alternating voltage by phase discrimination, and realizing the position by a division process.
The voltage loop finally outputs a value I related to the control of the inductive current ramp And added to the output of the multiplier voltage algorithm loop on the other side.
The other side is a multiplier voltage algorithm loop, and the functions of the multiplier voltage algorithm loop are two, namely, the multiplier voltage algorithm loop is used for overvoltage protectionCalculation of guard voltage, once input voltage V in And automatically shut down when the limit value is exceeded (or fallen below). Second, based on the compensated inductive current IL and the control voltage V control Calculating multiplier voltage V by using the calculated values m The specific calculation relationship of (1) is as follows:
Figure BDA0003904076060000071
wherein, I CS The value of the inductor current IL after being calculated by the two-type compensator. V bo Is an overvoltage protection voltage. K c Is to control the voltage conversion ratio, V control Is a control voltage, V control (min) is the minimum value of the control voltage, K C Is to control the voltage conversion ratio.
Over-current protection voltage V bo Is an input voltage V in Removing high frequency component by first-order filtering, and converting ratio K B The specific calculation relationship is obtained as follows:
Figure BDA0003904076060000072
wherein the ratio K B The conversion ratio of the overvoltage protection voltage, the specific size of which depends on the sampling relation, is as follows:
Figure BDA0003904076060000073
specific proportional sampling value K B The selection is not so important and will not be described in detail.
V control And V control (min) is the minimum value of the control voltage and the control voltage, respectively, for adjusting the range and the size of the output power of the present invention, and needs to be determined according to the rated output power and the adjustment range. The relationship with the output voltage is as follows:
Figure BDA0003904076060000074
wherein G is e (s) is the open loop gain of the system, K c Is to control the voltage conversion ratio, V out Is the rated output voltage, and the latter function is the transfer function of the two-type compensator.
Minimum value of control voltage V control (min) is the control voltage V under the output power condition control Can be controlled by applying a control voltage V control The equation of (a) finds a value under a specific condition, generally 0.3-0.75, after the Monte Carlo analysis is performed on the number of deviations, and a fixed value is obtained under the same output condition.
And an overvoltage protection voltage V bo After the upper limit of the limit value is exceeded, the voltage algorithm loop of the multiplier automatically enters a current limiting state to limit further improvement of the current. And after the lower limit of the limit value is lower, the voltage algorithm ring of the multiplier automatically enters an undervoltage state, and the output control value is 0 at the moment, so that the undervoltage protection action is automatically entered.
The multiplier voltage algorithm loop will finally output a numeric multiplier voltage V related to the input voltage phase m And with the output I of the voltage ring on the other side ramp And (4) adding.
The part of the control loop after the adder is PWM generated and functions to generate the corresponding drive signal by the previous control parameters. The device is composed of the following main parts:
the ramp periodic trigger signal is a square wave signal source, the frequency is high frequency, the frequency used in the common scheme is 65kHz-150kHz, the duty ratio is 0.1 percent, and the ramp periodic trigger signal is specifically a narrow pulse signal and is used for triggering an integrator and an SR trigger.
The integrator, i.e. the ramp generation in fig. 4, is used to generate a ramp value, which is different in different implementations, and the analog circuit method is implemented by an integrating circuit, and the digitizing scheme may be implemented by a counter. The circuit has an edge triggering function, and can be cleared immediately after receiving a ramp cycle triggering signal for controlling the cycle number.
And the comparator compares the value Vref with the value of the ramp wave and outputs a corresponding logic level. The determination of the comparison value Vref, in relation to the design of parameters such as the rated power and the input impedance, affects the range of the Power Factor (PF) and the output power. The specific relationship is derived later on in the input impedance.
The SR flip-flop is a normal SR flip-flop. When R =1, s =0, the output Q is set to 1, when R =0, when s =1, the output Q is set to 0, when R =1, and when s =1, the output Q state is unchanged. (avoid R =0, S =0, with an indefinite Q-state output)
The invention is suitable for the technical field of power electronics, and is used for designing controllers and related circuits in single-phase power factor correction circuits (boots PFC) and realizing PFC processes of Continuous Current Modes (CCM).

Claims (9)

1. A single-phase power factor correction control method based on multiplier voltage to adjust input impedance is characterized in that: the method comprises the following steps:
A. collecting inductive current I by sampling circuit L An output voltage V out And an input voltage V in Three parameters;
B. respectively passing the inductive currents I through control loops L The output voltage V out And said input voltage V in Calculating to obtain the control value I of the inductive current ramp And multiplier voltage V m ；
C. The control value of the inductor current I ramp And the multiplier voltage V m And adding the signals in the control loop and outputting the signals to a PWM generating terminal, and generating corresponding driving signals in the PWM generating terminal.
2. The single-phase power factor correction control method for adjusting input impedance based on multiplier voltage according to claim 1, wherein: the control loop is a parallel double loop and comprises a voltage loop and a multiplier voltage algorithm loop.
3. According to the claimThe method for controlling the single-phase power factor correction based on the multiplier voltage to adjust the input impedance is characterized in that: the voltage loop passes through the output voltage V out Calculating the difference value of the target output voltage, adjusting the output quantity, simultaneously judging the position of the zero crossing point of the input alternating voltage by phase discrimination, and finally comparing the position with the inductive current I L Outputting the inductance current control value I related to the inductance current control after combining calculation ramp 。
4. The single-phase power factor correction control method of claim 3 for adjusting input impedance based on multiplier voltage, wherein: the multiplier voltage algorithm loop is used for the calculation of the overvoltage protection voltage once the input voltage V is applied in When the temperature is not within the range of the limit value, the automatic shutdown can be realized; the multiplier voltage algorithm loop can also be based on the compensated inductor current I L And a control voltage V control Calculating the multiplier voltage V m 。
5. The single-phase power factor correction control method of claim 4 for adjusting input impedance based on multiplier voltage, wherein: the PWM generating end sequentially comprises a ramp periodic trigger signal, an integrator, a comparator and an SR trigger, and the inductive current control value I ramp And said multiplier voltage V m And after the addition calculation is carried out at the last end of the control loop, the control loop enters the integrator after zero division, and finally a driving signal is sent out through the Q end of the SR trigger.
6. The single-phase power factor correction control method for adjusting input impedance based on multiplier voltage of claim 5, wherein: in step B, the inductor current I L After the calculation of the two types of compensators, the two types of compensators are respectively input into the voltage ring and the multiplier voltage algorithm ring, and the transfer function of the two types of compensators is as follows:
Figure FDA0003904076050000021
7. the single-phase power factor correction control method for adjusting input impedance based on multiplier voltage of claim 6, wherein: in step B, the input voltage V in Obtaining an over-current protection voltage V after passing through a first-order filter bo Said overvoltage protection voltage V bo The calculation formula of (2) is as follows:
Figure FDA0003904076050000022
8. the single-phase power factor correction control method for adjusting input impedance based on multiplier voltage of claim 7, wherein: in step B, the overvoltage protection voltage V bo The control voltage V within the multiplier voltage algorithm loop control The multiplier voltage V is obtained after the combination calculation m Wherein the control voltage V control And an output voltage V out The relation of (A) is as follows:
Figure FDA0003904076050000023
9. the single-phase power factor correction control method for adjusting input impedance based on multiplier voltage of claim 8, wherein: the multiplier voltage V m The calculation formula of (1) is as follows:
Figure FDA0003904076050000024
CN202211299759.5A 2022-10-24 2022-10-24 Single-phase power factor correction control method for regulating input impedance based on multiplier voltage Pending CN115549463A (en)

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