CN111934527B - Carrier synchronization method and device without interconnection line of converter - Google Patents
Carrier synchronization method and device without interconnection line of converter Download PDFInfo
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- CN111934527B CN111934527B CN202010616515.XA CN202010616515A CN111934527B CN 111934527 B CN111934527 B CN 111934527B CN 202010616515 A CN202010616515 A CN 202010616515A CN 111934527 B CN111934527 B CN 111934527B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
Abstract
The application discloses a carrier synchronization method and a carrier synchronization device without interconnection lines of a converter, which comprise the steps of counting the number of counting cycles of a clock of a PWM module; judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated; if the rising edge of the synchronous pulse is captured, judging whether the number of the counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range; if so, adjusting the counting peak value of the clock of the PWM module in the next carrier synchronization period according to the counting value of the clock of the eCAP module when the synchronization pulse is captured, the current counting peak value and the preset phase of the clock of the PWM module. According to the method, interconnection lines do not need to be arranged between each converter and the synchronous controller or between the converters, the input cost can be reduced, the flexibility of system layout is improved, and sudden change of control pulses of the power module can be avoided.
Description
Technical Field
The application relates to the technical field of converters, in particular to a carrier synchronization method without interconnection lines of a converter; still relate to the carrier synchronization device that does not have interconnect line of a converter.
Background
When a plurality of converters are not provided with input isolation transformers and are directly connected to a power grid at the same point, large circulating currents are generated among the power modules due to the fact that instantaneous voltages output by the power modules are inconsistent, and the output filter inductors of the converters are saturated due to the large circulating currents, so that the converters cannot normally work. Meanwhile, the large circulating current can also cause the output current/voltage resonance of the converter, so that the fault of the converter is disconnected. And the main factor causing the circulation current between the direct parallel converters is that the carriers of the power modules of the converters are not synchronous. As shown in fig. 1, the current solution for carrier synchronization is to provide a synchronization controller outside each converter, transmit the synchronization signal sent uniformly to each converter through the interconnection line, and synchronize the carrier to a preset specified phase when each converter receives the synchronization signal. In order to ensure the consistency of the synchronization signals to the converters, the lengths of the interconnection lines between the converters and the synchronization controller cannot differ too much, and the converters need to be gathered in a fixed range. However, the current transformer is often distributed widely, thereby increasing the wiring difficulty and cost. In addition, as shown in fig. 2, the conventional carrier synchronization method is hard synchronization, that is, the converter synchronizes the carrier to a specified phase, for example, to 0 phase, immediately after receiving the synchronization signal. Such hard synchronization may cause a sudden change of the control pulse of the power module, which may cause a large low-order harmonic, and even cause over-current and over-voltage faults.
In view of the above, how to solve the above technical defects has become a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The purpose of the application is to provide a carrier synchronization method and device without interconnection lines of a converter, interconnection lines between converters or between a synchronous controller and the converter are not needed to be arranged, the input cost can be reduced, the flexibility of system layout is improved, sudden change of control pulses of a power module can be avoided, and the influence of carrier synchronization on the control performance is reduced.
In order to solve the technical problem, the application provides a carrier synchronization method without an interconnecting line for a converter, which includes:
counting the number of counting cycles of a clock of the PWM module;
judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated;
if the rising edge of the synchronous pulse is captured, judging whether the number of counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range;
if the current counting value is within the preset range, the counting peak value of the clock of the PWM module in the next carrier synchronization period is adjusted according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value and the preset phase of the clock of the PWM module.
Optionally, the counting the number of counting cycles of the clock of the PWM module includes:
judging whether a counting waveform corresponding to a counting value of a clock of the PWM module crosses a zero point;
and every time the counting waveform is zero-crossed, adding one to the number of counting cycles of the clock of the PWM module.
Optionally, the determining whether a count waveform corresponding to a count value of a clock of the PWM module crosses zero includes:
comparing the current count value with the previous count value of the clock of the eCAP module;
and if the current count value of the clock of the eCAP module is smaller than the previous count value, the counting waveform crosses zero.
Optionally, the determining whether the eCAP module captures a rising edge of the synchronization pulse includes:
judging whether the interrupt flag bit of the eCAP module is 1 or not;
and if so, capturing the rising edge of the synchronous pulse by the eCAP module.
Optionally, the manner of obtaining the synchronization pulse is:
collecting the power grid voltage of a power grid in which the converter is incorporated through a voltage collecting circuit;
filtering the power grid voltage through a filter circuit;
and converting the filtered power grid voltage into the synchronous pulse with the same frequency as the power grid voltage through a comparison circuit.
Optionally, the adjusting, according to the count value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current count peak value and the preset phase of the clock of the PWM module, the count peak value of the clock of the PWM module in the next carrier synchronization period includes:
when the clock of the PWM module adopts an increasing and decreasing counting mode, the reference
And
calculating to obtain the variation delta of the counting peak value;
rounding the variation delta of the counting peak value to zero, and taking the remainder u,
rounding the remainder u to zero according to
Obtaining the counting peak value of each counting period in the next carrier synchronization period;
the eCAP _ cnt is a count value of a clock of the eCAP module when the eCAP module captures the synchronous pulse, ref _ cnt is a count value corresponding to the preset phase, rT _ car is a current counting peak value of the clock of the PWM module, delta 'is a value obtained by rounding a variation delta of the counting peak value to zero, u' is a value obtained by rounding a remainder u to zero, rTcar is a new counting peak value, rT _ car is an original counting peak value, and N is the number of counting cycles of the clock of the PWM module in a power grid voltage period.
Optionally, the adjusting, according to the count value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current count peak value and the preset phase of the clock of the PWM module, the count peak value of the clock of the PWM module in the next carrier synchronization period includes:
when the PWM module adopts an increasing counting mode or a decreasing counting mode
rounding the variation delta of the counting peak value to zero, and rounding the remainder u to zero according to the value of the remainder u, u-delta cnt '-delta' × (N-1)
Obtaining the counting peak value of each counting period in the next carrier synchronization period;
the eCAP _ cnt is a count value of a clock of the eCAP module when the eCAP module captures the synchronous pulse, ref _ cnt is a count value corresponding to the preset phase, rT _ car is a current counting peak value of the clock of the PWM module, delta 'is a value obtained by rounding a variation delta of the counting peak value to zero, u' is a value obtained by rounding a remainder u to zero, rTcar is a new counting peak value, rT _ car is an original counting peak value, and N is the number of counting cycles of the clock of the PWM module in a power grid voltage period.
In order to solve the above technical problem, the present application further provides a carrier synchronization device without interconnection line for a converter, including:
a synchronization pulse generating circuit for generating a synchronization pulse; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated;
the control chip is used for counting the number of counting cycles of the clock of the PWM module; judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated; if the rising edge of the synchronous pulse is captured, judging whether the number of counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range; if the current counting value is within the preset range, the counting peak value of the clock of the PWM module in the next carrier synchronization period is adjusted according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value and the preset phase of the clock of the PWM module.
Optionally, the synchronization pulse generating circuit includes:
the voltage acquisition circuit is used for acquiring the grid voltage of a power grid in which the converter is incorporated;
the filter circuit is used for filtering the power grid voltage;
and the comparison circuit is used for converting the filtered power grid voltage into the synchronous pulse with the same frequency as the power grid voltage.
Optionally, the comparison circuit includes:
a voltage comparator for comparing the grid voltage with a zero voltage;
and the MOS tube is used for pulling up the output of the voltage comparator.
The application provides a carrier synchronization method without an interconnection line for a converter, which comprises the following steps: counting the number of counting cycles of a clock of the PWM module; judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated; if the rising edge of the synchronous pulse is captured, judging whether the number of counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range; if the current counting value is within the preset range, the counting peak value of the clock of the PWM module in the next carrier synchronization period is adjusted according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value and the preset phase of the clock of the PWM module.
Therefore, the interconnection-line-free carrier synchronization method for the converter takes the zero crossing point of the grid voltage of the power grid in which the converter is incorporated as the synchronization signal, and the interconnection lines among the converters or between the synchronization controller and the converter are not required to be arranged, so that the synchronization difference caused by the inconsistent lengths of the interconnection lines can be avoided, and the input cost is reduced. In addition, the carrier synchronization is carried out in a soft synchronization mode of adjusting the counting peak value of the clock of the PWM module, and the initial phase difference of the carrier is finally adjusted to be zero by adjusting the counting peak value repeatedly, namely the carrier synchronization is carried out. Compared with the traditional hard synchronization mode, the method and the device can avoid sudden change of the control pulse of the power module caused by sudden forced synchronization of the carrier, and reduce the influence of the carrier synchronization on the control performance.
The carrier synchronization device without the interconnection line also has the technical effects.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a conventional interconnected converter parallel system;
FIG. 2 is a schematic diagram of a burst during carrier hard synchronization;
fig. 3 is a schematic flowchart of a carrier synchronization method without an interconnection line for a converter according to an embodiment of the present disclosure;
FIG. 4 is a diagram of a synchronization pulse according to an embodiment of the present application;
FIG. 5 is a diagram illustrating an up-down counting mode according to an embodiment of the present application;
FIG. 6 is a diagram illustrating an incremental count mode according to an embodiment of the present application;
FIG. 7 is a diagram illustrating a countdown mode according to an embodiment of the present application;
FIG. 8 is a diagram of a hardware circuit provided in an embodiment of the present application;
FIG. 9 is a schematic diagram of a filter and a comparator circuit according to an embodiment of the present disclosure;
FIG. 10 is a bode plot of an embodiment of the present application;
fig. 11 is a schematic diagram of a comparator according to an embodiment of the present application;
fig. 12 is a forward zero-crossing voltage transfer characteristic diagram according to an embodiment of the present application.
Detailed Description
The core of the application is to provide the carrier synchronization method and the carrier synchronization device without the interconnection lines between the synchronous controller and the converters or between the converters, so that the input cost can be reduced, the flexibility of system layout is improved, the sudden change of control pulses of the power module can be avoided, and the influence of carrier synchronization on the control performance is reduced.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 3, fig. 3 is a schematic flowchart of a carrier synchronization method without interconnection lines for a converter according to an embodiment of the present application, referring to fig. 3, the method includes:
s101: counting the number of counting cycles of a clock of the PWM module;
specifically, the carrier synchronization method for the converters provided by the application is applied to control systems of the converters, and the control systems of the converters independently execute the following steps to achieve carrier synchronization among the converters. The control pulse of the power module of the converter is generated by a PWM module of a control chip of a control system of the converter, a clock of the PWM module continuously counts according to a specified counting mode, and when the counting value reaches a counting peak value, counting is started from zero or counting is started to be decreased from the counting peak value (specifically, the counting mode determines).
The counting period of the clock of the PWM module is a counting period in which the counting value of the clock of the PWM module is incremented from zero to a peak value and then decremented from the peak value to zero in an increment and decrement mode; or in the increment mode, the counting value of the clock of the PWM module is incremented from zero to a peak value to be a counting period; or in the down mode, one count period from peak to zero.
Under the condition that the system clock frequency of the control chip, the clock frequency of the PWM module and the switching frequency of the power module of the converter are all determined, the number of counting cycles of the clock of the PWM module in one power grid voltage cycle is correspondingly determined. For example, when the control chip is a DSP, when the system clock frequency of the DSP is 150MHz, the clock frequency of the PWM in the DSP is 2 frequency division of the system clock frequency of the DSP, and the switching frequency of the power module of the converter is 2.85kHz, the count peak value of the clock of the PWM module is 13157, and the number of count cycles of the clock of the PWM module in one grid voltage cycle is 57. Between two zero crossings of the mains voltage, the number of counting cycles of the clock of the PWM module should range between 56 and 58. If the voltage of the power grid is beyond the interval, the zero crossing point of the voltage of the power grid cannot be effectively detected, or the frequency fluctuation of the power grid is large, and at the moment, the operation of subsequently adjusting the counting peak value of the clock of the PWM module is not performed.
Step S101 is to count the number of counting cycles of the clock of the PWM module, and subsequently determine whether to adjust the counting peak value. In a specific embodiment, counting the number of counting cycles of the clock of the PWM module includes: judging whether a counting waveform corresponding to a counting value of a clock of the PWM module crosses a zero point; the number of count cycles of the clock of the PWM module is incremented by one each time the count waveform crosses zero.
Further, in a specific embodiment, determining whether a count waveform corresponding to a count value of a clock of the PWM module crosses a zero point includes: comparing the current count value with the previous count value of the clock of the eCAP module; and if the current count value of the clock of the eCAP module is smaller than the previous count value, counting the zero crossing point of the waveform.
Specifically, the clock of the eCAP module continuously counts up, and the count value may be reset to zero and the up-counting may be restarted after receiving the peripheral synchronization pulse of the control chip (which is issued by the PWM module). Based on this, in this embodiment, each time the count waveform corresponding to the count value of the clock of the PWM module crosses the zero point, the PWM module sends out the peripheral synchronization pulse, thereby triggering the count value of the clock of the eCAP module to return to zero. And then, whether the counting waveform corresponding to the counting value of the clock of the PWM module crosses zero or not can be judged by comparing the current counting value of the clock of the eCAP module with the previous counting value. And if the current count value of the clock of the eCAP module is smaller than the previous count value, representing the zero crossing point of the counting waveform. On the contrary, if the current count value of the clock of the eCAP module is not less than the previous count value, it indicates that the count waveform does not pass through the zero point. And adding one to the number of the counting cycles of the clock of the PWM module every time the counting waveform crosses zero to obtain the total number of the counting cycles of the clock of the PWM module in the current carrier synchronization cycle.
S102: judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated;
specifically, each converter is directly connected in parallel on public voltage, and the voltage waveforms of the power grid are consistent, so the zero crossing point of the power grid voltage of the power grid into which the converter is incorporated is used as a synchronous signal, and an upper computer and other external devices are not required to provide a uniform carrier synchronous signal. The step aims to detect whether the grid voltage of the power grid into which the converter is incorporated crosses zero. Specifically, a synchronization pulse having the same frequency as the grid voltage is generated based on the grid voltage (as shown in fig. 4), and a rising edge of the synchronization pulse is captured by the eCAP module, wherein the rising edge of the synchronization pulse corresponds to a zero crossing point of the grid voltage. If the eCAP module captures the rising edge of the synchronous pulse, the rising edge represents the zero crossing point of the power grid voltage.
The method for obtaining the synchronization pulse may be: collecting the power grid voltage of a power grid in which the converter is incorporated through a voltage collecting circuit; filtering the power grid voltage through a filter circuit; and converting the filtered power grid voltage into synchronous pulses with the same frequency as the power grid voltage through a comparison circuit.
Specifically, on the basis of collecting the power grid voltage through the voltage collecting circuit, high-frequency interference signals caused by power grid lines and the like are further filtered through the filter circuit, and finally the filtered power grid voltage is compared with a zero level through the comparison circuit, so that the power grid voltage is converted into synchronous pulses with the same frequency as the power grid voltage.
In addition, determining whether the eCAP module captures a rising edge of the synchronization pulse may include: judging whether an interrupt flag bit of the eCAP module is 1 or not; if yes, the eCAP module captures the rising edge of the synchronization pulse.
Specifically, after the eCAP module captures the rising edge of the synchronization pulse, the control chip of the converter control system stores the count value of the clock of the eCAP into the corresponding register, and sets the interrupt flag of the eCAP module to 1, so that if the interrupt flag of the eCAP module is set to 1, it is indicated that the eCAP module captures the rising edge of the synchronization pulse. Otherwise, the eCAP module does not capture the rising edge of the synchronization pulse.
S103: if the rising edge of the synchronous pulse is captured, judging whether the number of the counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range;
s104: and if the current counting value is within the preset range, adjusting the counting peak value of the clock of the PWM module in the next carrier synchronization period according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value of the clock of the PWM module and the preset phase.
Specifically, on the basis of counting the number of the counting cycles of the clock of the PWM module, when the eCAP module captures the rising edge of the synchronization pulse, that is, when the zero crossing point of the grid voltage is detected, it is first determined whether the number of the counting cycles of the clock of the PWM module in the current carrier synchronization cycle is within a preset range; if the number of the counting cycles of the clock of the PWM module in one grid voltage cycle is 57, judging whether the number of the counting cycles of the clock of the PWM module in the current carrier synchronization cycle is within the range of 56-58. If so, adjusting the counting peak value of the clock of the PWM module in the next carrier synchronization period further according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value and the preset phase of the clock of the PWM module.
In a specific embodiment, adjusting a count peak value of a clock of the PWM module in a next carrier synchronization period according to a count value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, a current count peak value of the clock of the PWM module, and a preset phase includes:
when the clock of the PWM module adopts an increasing and decreasing counting mode, the reference
the change delta of the counting peak value is rounded to zero, the remainder u is taken,
rounding the remainder u to zero according to
Obtaining the counting peak value of each counting period in the next carrier synchronization period;
the eCAP _ cnt is a count value of a clock of the eCAP module when the eCAP module captures a synchronous pulse, the ref _ cnt is a count value corresponding to a preset phase, the rT _ car is a current count peak value of the clock of the PWM module, delta 'is a value obtained by rounding a variation delta of the count peak value to zero, u' is a value obtained by rounding a remainder u to zero, the rTcar is a new count peak value, the rT _ car is an original count peak value, and N is the number of count cycles of the clock of the PWM module in a power grid voltage cycle.
Specifically, referring to fig. 5, in the case that the clock of the PWM module adopts the up-down counting mode (i.e., the counting waveform is triangular wave), since the new counting peak is loaded into the period register when the counting value of the clock of the PWM module is zero and becomes effective in the next counting period, when the clock of the PWM module adopts the up-down counting mode, the capture time needs to be discussed.
For example, the capture time occurs during the increment phase of the 57 th count cycle, i.e., capture time 1 shown in fig. 5, and the new count peak calculated at the second calculation time of the 57 th count cycle (as shown in calculation 1 in fig. 5) is loaded into the cycle register of the PWM module at the zero time of the 58 th count cycle, i.e., the 58 th count peak uses the latest count peak. Each count period within the next carrier synchronization period (20ms) uses a new count peak.
The capture time occurs at the decrement phase of the 57 th count cycle, i.e., capture time 2 shown in fig. 5, and the new count peak calculated at the first calculation time of the 58 th count cycle (as shown in calculation 2 in fig. 5) is loaded into the cycle register of the PWM module at the zero time of the 59 th count cycle, i.e., the 59 th count cycle uses the latest cycle count value. At this time, a new count peak is used for each of the following count periods, except that the original count peak is still used for the first count period in the following carrier synchronization period (20 ms).
If the remainder is added to the peak count value, the count periods within the entire carrier synchronization period will be inconsistent and differ by 1, so this embodiment rounds delta to zero, rounds remainder u, and rounds u to zero. The counting peak value of the first u 'counting periods in the next carrier synchronization period is plus or minus one, and the plus or minus one is determined by the sign of u'. The count peak value of the u' +1 th and subsequent count cycles remains unchanged.
In another specific embodiment, adjusting the count peak value of the clock of the PWM module in the next carrier synchronization period according to the count value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current count peak value of the clock of the PWM module, and the preset phase includes:
when the PWM module adopts an increasing counting mode or a decreasing counting mode, according to
And with
Calculating to obtain the change of the counting peak valueQuantity delta;
rounding the variation delta of the counting peak value to zero, and rounding the remainder u to zero according to the value of the remainder u, u-delta cnt '-delta' × (N-1)
Obtaining the counting peak value of each counting period in the next carrier synchronization period;
the eCAP _ cnt is a count value of a clock of the eCAP module when the eCAP module captures a synchronous pulse, ref _ cnt is a count value corresponding to a preset phase, rT _ car is a current count peak value of the clock of the PWM module, delta 'is a value obtained by rounding a variation delta of the count peak value to zero, u' is a value obtained by rounding a remainder u to zero, rTcar is a new count peak value, rT _ car is an original count peak value, and N is the number of count cycles of the clock of the PWM module in a power grid voltage period.
Specifically, referring to fig. 6 and 7, when the clock of the PWM module adopts the count-up mode or the count-down mode (i.e., the count waveform is sawtooth wave), the change amount of the count peak is calculated without dividing by 2 and without distinguishing the capturing time, compared to the embodiment that the clock of the PWM module adopts the count-up/count-down mode. The counting peak value of the first u 'counting periods in the next carrier synchronization period is plus or minus one, and the plus or minus one is determined by the sign of u'. The count peak value of the u' +1 th and subsequent count cycles remains unchanged.
The final goal of the carrier soft synchronization is that the number of the counting cycles of the clock of the PWM module in each carrier synchronization cycle is equal to the number of the counting cycles of the clock of the PWM module in one grid voltage cycle, for example, 57 cycles. And when the eCAP module catches the rising edge of the synchronous pulse, the count value of the clock of the eCAP module is just consistent with the count value of the clock represented by the preset phase. Since each carrier synchronization period is fixed, and the clock frequencies of the PWM module and the eCAP module are kept constant, the total clock count values of the PWM module and the eCAP module are constant within one carrier synchronization period, such as (13157 × 2-1) × 57 ═ 1499841. And when the number of the counting cycles of the clock of the PWM module in one grid voltage cycle is 57, under a normal condition, the time (i.e., the synchronization time) when each eCAP module captures the rising edge of the synchronization pulse is before or after the zero point of the 57 th counting cycle, and the counting cycle is not exceeded. Therefore, if the count peak value per count cycle is decreased, the carrier phase at the next synchronization timing is increased, and conversely, is decreased. The phase of the synchronous time is close to the preset phase by controlling the counting peak value of the counting period, and finally the carrier phase is synchronized.
Assuming that the synchronization phase is 0, the carrier overshoots when the capture timing occurs at the increment stage of the 57 th count cycle, and ideally, the capture timing is degraded to the zero point at which the 56 th carrier ends, and at this time, the count peak of the count cycle in the next carrier synchronization cycle should be increased to move the next capture timing backward. If the capture time occurs in the descending stage of the 57 th counting period, it indicates that the carrier has undershoot, and ideally, the capture time should advance to the zero point of the 57 th carrier, and at this time, the counting peak value of the counting period in the carrier synchronization period should be reduced, so that the position of the next capture time is moved forward. I.e. the absolute value of the deviation of the preset phase of the carrier from the actual phase does not exceed half of the total count value of the counting period, i.e. < 13157.
In summary, according to the carrier synchronization method for the converter provided by the application, the zero-crossing point of the grid voltage of the power grid into which the converter is incorporated is used as the synchronization signal, and the interconnection lines between the converters or between the synchronization controller and the converter do not need to be arranged, so that the synchronization difference caused by the length inconsistency of the interconnection lines can be avoided, and the investment cost is reduced. In addition, the carrier synchronization is carried out in a soft synchronization mode of adjusting the counting peak value of the clock of the PWM module, and the initial phase difference of the carrier is finally adjusted to be zero by adjusting the counting peak value repeatedly, namely the carrier synchronization is carried out. Compared with the traditional hard synchronization mode, the method and the device can avoid sudden change of the control pulse of the power module caused by sudden forced synchronization of the carrier, and reduce the influence of the carrier synchronization on the control performance.
The present application further provides a non-interconnection line carrier synchronization apparatus for a converter, which may be referred to in correspondence with the above-described method. The device comprises:
a synchronization pulse generating circuit for generating a synchronization pulse; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated;
the control chip is used for counting the number of counting cycles of the clock of the PWM module; judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated; if the rising edge of the synchronous pulse is captured, judging whether the number of counting cycles of the clock of the PWM module in the current carrier synchronization cycle is within a preset range or not; and if the current counting value is within the preset range, adjusting the counting peak value of the clock of the PWM module in the next carrier synchronization period according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value of the clock of the PWM module and the preset phase.
The description of the control chip is not repeated herein, and reference may be made to the embodiments of the foregoing method. The synchronization pulse generation circuit is further described as follows: the synchronous pulse generating circuit is used for generating a synchronous pulse; the rising edge of the synchronization pulse corresponds to a zero crossing of the grid voltage of the power grid into which the converter is incorporated. Also, as shown with reference to fig. 8, the synchronization pulse generating circuit may include: the voltage acquisition circuit is used for acquiring the grid voltage of a power grid in which the converter is incorporated; the filter circuit is used for filtering the voltage of the power grid; and the comparison circuit is used for converting the filtered power grid voltage into synchronous pulses with the same frequency as the power grid voltage.
The filter is an active filter, the network voltage waveform of the parallel connection point of the converter is filtered by the filter to remove the high-frequency interference of the line, and the comparison circuit converts the network voltage signal into a 5V square wave signal, namely a synchronous pulse.
In fig. 9, an input voltage source V20 represents the input voltage of the voltage sampling circuit, which has been converted into a low-voltage electrical signal, such as a cosine signal with an amplitude of 10V, and after high-frequency interference signals caused by the voltage conversion circuit, the power grid line, etc. are filtered out by the active filter, the high-frequency interference signals enter the comparison circuit to be compared with a zero level, so that cosine waveforms are converted into square waves with the same frequency, and the square waves are sent to a control chip in the converter control system to perform carrier synchronization processing.
The active filter can avoid the defects caused by the inherent non-linear characteristic of the inductance element, magnetic field shielding, loss, volume and heavy weight, and has the function of providing certain signal gain and buffering action. In order to reduce the filter delay time as much as possible, the delay time is selected to be 20 μ s, and C1, C2 is set to 1nF, and R1, R2 is set to 10k Ω. The cut-off frequency of the active filter at this time is:
the transfer function of the active filter is:
the bode diagram is shown in fig. 10, at this time, the damping ratio of the active filter is 1, the natural frequency is 105, the quality factor is 0.5, the phase angle margin is 90 °, the amplitude margin is 75dB, and the active filter has a large stability margin and does not substantially affect the stability of the back end.
In a direct parallel system of the converter, the low level of the zero-crossing synchronous pulse is 0, the voltage of the digital signal of the high-level matching control board is 5V, and therefore the threshold voltage of the zero-crossing synchronous pulse is 0 and a positive value respectively. However, in practice, the synchronous reference signal is based on the positive zero-crossing point of the parallel point voltage waveform, so that the other threshold voltage can only be negative. Therefore, it is necessary to improve the voltage comparator to make the voltage threshold value be 0 and negative. The circuit structure thereof is shown in fig. 11. At this time, according to the 'virtual short, virtual break' of the integrated operational amplifier, the following results are obtained:
when in use
While, U o0; on the contrary, the first step is to take the reverse,
the transmission characteristics are shown in fig. 12. Hysteresis width of
In the comparison circuit, the selected comparator LM211 has a low level error, which is not reliable 0V, but is related to the operating current of the internal ground transistor, usually around 80 mV. Therefore, the forward zero-crossing point is biased downwards, and the error difference caused by different carrier synchronization circuits is large, so that the synchronization deviation of each carrier is caused. To this end, referring to fig. 9, in a specific embodiment, the comparison circuit comprises: the voltage comparator and the MOS tube are connected, namely a pull-up output of the MOS tube is added after the output of the LM 211.
The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The apparatuses, devices, and computer-readable storage media disclosed in the embodiments correspond to the methods disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to in the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The method and the device for synchronizing the non-interconnection line carrier of the converter provided by the present application are described in detail above. The principles and embodiments of the present application are described herein using specific examples, which are only used to help understand the method and its core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A carrier synchronization method without interconnection lines of a converter is characterized by comprising the following steps:
counting the number of counting cycles of a clock of the PWM module; the PWM module generates a control pulse of a power module of the converter;
judging whether the eCAP module captures the rising edge of the synchronous pulse or not; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated;
if the rising edge of the synchronous pulse is captured, judging whether the number of counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range;
if the current counting value is within the preset range, the counting peak value of the clock of the PWM module in the next carrier synchronization period is adjusted according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value and the preset phase of the clock of the PWM module.
2. The interconnection-line-free carrier synchronization method for the converter according to claim 1, wherein the counting the number of counting cycles of the clock of the PWM module comprises:
judging whether a counting waveform corresponding to a counting value of a clock of the PWM module crosses a zero point;
and every time the counting waveform passes through a zero point, the number of counting periods of the clock of the PWM module is increased by one.
3. The interconnection-line-free carrier synchronization method of the converter according to claim 2, wherein the determining whether the counting waveform corresponding to the counting value of the clock of the PWM module crosses zero comprises:
comparing the current count value with the previous count value of the clock of the eCAP module;
and if the current count value of the clock of the eCAP module is smaller than the previous count value, the counting waveform passes through the zero point.
4. The interconnection-line-free carrier synchronization method for the converter according to claim 3, wherein the determining whether the eCAP module captures a rising edge of the synchronization pulse comprises:
judging whether the interrupt flag bit of the eCAP module is 1 or not;
and if so, capturing the rising edge of the synchronous pulse by the eCAP module.
5. The interconnection-line-free carrier synchronization method for the converter according to claim 4, wherein the synchronization pulses are obtained by:
acquiring the power grid voltage of a power grid in which the converter is incorporated through a voltage acquisition circuit;
filtering the power grid voltage through a filter circuit;
and converting the filtered power grid voltage into the synchronous pulse with the same frequency as the power grid voltage through a comparison circuit.
6. The interconnection-line-free carrier synchronization method of the converter according to claim 5, wherein the adjusting the count peak value of the clock of the eCAP module in the next carrier synchronization period according to the count value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current count peak value and the preset phase of the clock of the PWM module comprises:
when the clock of the PWM module adopts an increasing and decreasing counting mode, the reference
the change delta of the counting peak value is rounded to zero, the remainder u is taken,
rounding the remainder u to zero according to
Obtaining the counting peak value of each counting period in the next carrier synchronization period;
the eCAP module is used for capturing a synchronous pulse, the clock of the eCAP module is counted, the eCAP module is used for capturing the synchronous pulse, ref _ cnt is a counted value corresponding to the preset phase, rT _ car is a current counting peak value of the clock of the PWM module, delta 'is a value obtained by rounding a variable delta of the counting peak value to zero, u' is a value obtained by rounding a remainder u to zero, rTcar is a new counting peak value, rT _ car is an original counting peak value, and N is the number of counting cycles of the clock of the PWM module in a power grid voltage cycle.
7. The interconnection-line-free carrier synchronization method according to claim 5, wherein the adjusting the count peak value of the clock of the eCAP module in the next carrier synchronization period according to the count value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current count peak value and the preset phase of the clock of the PWM module comprises:
when the PWM module adopts an increasing counting mode or a decreasing counting mode
rounding the change delta of the count peak to zero and taking the remainder u, u ═ delta cnt '-delta' × (N-1)
Rounding the remainder u to zero according to
Obtaining the counting peak value of each counting period in the next carrier synchronization period;
the eCAP module is used for capturing a synchronous pulse, the clock of the eCAP module is counted, the eCAP module is used for capturing the synchronous pulse, ref _ cnt is a counted value corresponding to the preset phase, rT _ car is a current counting peak value of the clock of the PWM module, delta 'is a value obtained by rounding a variable delta of the counting peak value to zero, u' is a value obtained by rounding a remainder u to zero, rTcar is a new counting peak value, rT _ car is an original counting peak value, and N is the number of counting cycles of the clock of the PWM module in a power grid voltage cycle.
8. An interconnection-line-free carrier synchronization device of a converter is characterized by comprising:
a synchronization pulse generating circuit for generating a synchronization pulse; the rising edge of the synchronous pulse corresponds to the zero crossing point of the grid voltage of the power grid into which the converter is incorporated;
the control chip is used for counting the number of counting cycles of the clock of the PWM module; the PWM module generates a control pulse of a power module of the converter; judging whether the eCAP module captures the rising edge of the synchronous pulse or not; if the rising edge of the synchronous pulse is captured, judging whether the number of counting cycles of the clock of the PWM module in the current carrier synchronous cycle is in a preset range; and if the current counting value is within the preset range, adjusting the counting peak value of the clock of the PWM module in the next carrier synchronization period according to the counting value of the clock of the eCAP module when the eCAP module captures the synchronization pulse, the current counting peak value and the preset phase of the clock of the PWM module.
9. The interconnecting-line-free carrier synchronization device of claim 8, wherein the synchronization pulse generation circuit comprises:
the voltage acquisition circuit is used for acquiring the grid voltage of a power grid in which the converter is incorporated;
the filter circuit is used for filtering the power grid voltage;
and the comparison circuit is used for converting the filtered power grid voltage into the synchronous pulse with the same frequency as the power grid voltage.
10. The interconnection-line-less carrier synchronization device of a converter according to claim 9, wherein the comparison circuit comprises:
a voltage comparator for comparing the grid voltage with a zero voltage;
and the MOS tube is used for pulling up the output of the voltage comparator.
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