CN115548094A - Enhanced gallium nitride transistor, manufacturing method of device and device - Google Patents

Enhanced gallium nitride transistor, manufacturing method of device and device Download PDF

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CN115548094A
CN115548094A CN202211255239.4A CN202211255239A CN115548094A CN 115548094 A CN115548094 A CN 115548094A CN 202211255239 A CN202211255239 A CN 202211255239A CN 115548094 A CN115548094 A CN 115548094A
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layer
gan
metal
drain
gate
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张鹏浩
王路宇
徐敏
王强
潘茂林
樊蓉
杨妍楠
谢欣灵
徐赛生
王晨
张卫
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Fudan University
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The invention provides an enhancement mode gallium nitride transistor, which comprises: the semiconductor device comprises a substrate, and a nucleating layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer which are formed on the substrate along the direction far away from the substrate; wherein the p-GaN layer comprises a first p-GaN layer and a second p-GaN layer; the first p-GaN layer is formed on the grid region; the second p-GaN layer is formed on the non-grid region; the source electrode, the grid electrode and the drain electrode are respectively formed on a source region, a grid electrode region and a drain region on the p-GaN layer; the grid electrode comprises the first p-GaN layer and a grid metal layer formed at the top end of the first p-GaN layer; and a passivation layer, wherein the first p-GaN layer includes passivated Mg ions; so that the gate is non-conductive at zero gate voltage. The technical scheme solves the problem of how to avoid etching damage of the first p-GaN layer.

Description

Enhanced gallium nitride transistor, manufacturing method, preparation method of device and device
Technical Field
The invention relates to the field of semiconductor devices, in particular to an enhanced gallium nitride transistor, a manufacturing method of equipment and the equipment.
Background
Gallium nitride high electron mobility transistors (AlGaN/GaN HEMTs) have broad prospects in the high-frequency and high-power fields due to their excellent device performance. With the continuous maturation of the technology, a part of the market is occupied in consumer electronics and radio frequency communication applications. In addition, such lateral devices also have the feasibility of high-density monolithic integration. The drive, protection and control functions can be integrated with the power switch, and the performance can be further improved due to the avoidance of parasitic inductance. Unlike silicon-based chips that are implemented using complementary logic circuits comprising n-channel field effect transistors (NMOS) and p-channel field effect transistors (PMOS), current implementations of gallium nitride power devices and peripheral circuits are based on n-channels. In GaN monolithic integrated circuits, a direct-coupled field effect logic (DCFL) scheme is typically used, which consists of an enhancement n-channel transistor and a depletion n-channel transistor. The pull-up circuit is composed of a depletion mode device with a short-circuited grid source, and therefore the depletion mode device is always in a conducting state. When the pull-down circuit is turned on, a large amount of static power is consumed. Therefore, power consumption is a major drawback of such DCFL circuits. The complementary logic circuit does not have this problem. To form a GaN-based complementary logic circuit with an n-channel GaN transistor, a high performance enhanced p-channel GaN transistor with a certain current density and good on-off ratio is required.
In conventional studies, p-channel gallium nitride transistors have been constructed by filling a quantum well with a high-density two-dimensional hole gas (2 DHG) mainly by utilizing the strong polarization characteristics of nitrides, so as to improve hole mobility and carrier density. However, such a customized epitaxial structure generally has a parasitic n-channel that cannot be depleted or does not have an n-channel, and thus cannot meet the requirement of a GaN complementary logic circuit, i.e., n and p channels exist simultaneously and do not interfere with each other. The current commercial p-GaN/AlGaN/GaN epitaxial wafer can just meet the requirement, and p-GaN/AlGaN and AlGaN/GaN heterojunction interfaces can be used as a p channel and an n channel. The presence of p-GaN depletes electrons in the AlGaN barrier layer so that the p-channel is also not disturbed by the n-channel. And etching the p-GaN at the position of the gate region, and only keeping the extremely thin thickness (< 10 nm) in the gate region, so that the holes in the p-GaN channel layer under zero gate voltage can be depleted, and the normally-closed p-channel device is realized. However, p-GaN etching has no doubt to damage the crystal lattice and the hole mobility in the p-channel is also reduced. And the etched interface also forms a high-density trap state due to factors such as etching byproduct accumulation, nitrogen vacancy and the like, thereby seriously influencing the performance of the device. Therefore, developing a new process for manufacturing a p-GaN gate becomes a technical focus to be solved by those skilled in the art.
Disclosure of Invention
The invention provides an enhanced gallium nitride transistor, a manufacturing method thereof, a manufacturing method of the enhanced gallium nitride transistor, and equipment thereof, and aims to solve the problem of how to avoid etching damage of a first p-GaN layer.
According to a first aspect of the present invention, there is provided an enhancement mode gallium nitride transistor comprising:
the semiconductor device comprises a substrate, and a nucleating layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer which are formed on the substrate along the direction far away from the substrate; wherein the p-GaN layer comprises a first p-GaN layer and a second p-GaN layer; the first p-GaN layer is formed on the grid region; the second p-GaN layer is formed on the non-grid region;
the source electrode, the grid electrode and the drain electrode are respectively formed on a source region, a grid electrode region and a drain region on the p-GaN layer; the grid electrode comprises the first p-GaN layer and a grid metal layer formed at the top end of the first p-GaN layer; and
a passivation layer for protecting the substrate from light,
wherein the first p-GaN layer comprises a neutral complex formed by passivation of acceptor impurity Mg ions; so that the gate is non-conductive at zero gate voltage.
Optionally, the passivation layer comprises a first passivation layer and a second passivation layer; the first passivation layer is formed on the second p-GaN layer; the second passivation layer is formed on the first passivation layer and the gate metal layer.
Optionally, the enhancement mode gan transistor further comprises:
the source electrode metal interconnection layer, the drain electrode metal interconnection layer and the grid electrode metal interconnection layer; the source metal interconnection layer, the drain metal interconnection layer and the grid metal interconnection layer are respectively formed at the top ends of the source electrode, the drain electrode and the grid;
a source metal pad, a drain metal pad and a gate metal pad; the source metal pad, the drain metal pad and the gate metal pad are formed at the top ends of the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer, respectively.
Optionally, the material of the nucleation layer is AlN, the material of the channel layer is GaN, and the material of the barrier layer is AlGaN.
According to a second aspect of the present invention, there is provided a method for manufacturing an enhancement mode gan transistor, comprising:
providing a substrate;
sequentially forming a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate along the direction far away from the substrate;
forming a source electrode, a drain electrode and a third passivation layer; the source electrode, the drain electrode and the third passivation layer are formed on the p-GaN layer, and the third passivation layer covers the source electrode and the drain electrode;
etching the third passivation layer in the gate region to form a gate opening and a first passivation layer;
performing first treatment on the p-GaN layer of the grid region to form a first p-GaN layer;
depositing a gate metal layer at the top end of the first p-GaN layer to form a gate; the gate comprises
The first p-GaN layer and the gate metal layer on the top end of the first p-GaN layer; and
forming a source metal interconnection layer, a drain metal interconnection layer and a grid metal interconnection layer; a source metal pad, a drain metal pad and a gate metal pad;
wherein the first processing comprises: and passivating the acceptor impurity Mg ions in the p-GaN layer so that the grid is not conducted at zero grid voltage.
Optionally, the thickness of the first p-GaN layer is controllable.
Optionally, the thickness of the first p-GaN layer is controlled to be a first thickness; the first thickness characterizes a thickness in a stacking direction of the barrier layer and the p-GaN layer.
Optionally, the first thickness is adjusted so that the distance between the first p-GaN layer and the barrier layer is controlled to be 5-10 nm.
Optionally, the method for passivating Mg ions in the p-GaN layer includes: thermal oxidation, oxygen plasma, and hydrogen plasma.
Optionally, when the thermal oxidation method is adopted, the first thickness is realized by adjusting temperature, oxygen flow, pressure or time in the oxidation process;
when the oxygen plasma method or the hydrogen plasma method is employed, the first thickness is achieved by adjusting power, pressure, gas flow rate, or time.
Optionally, the forming of the source electrode, the drain electrode and the third passivation layer specifically includes:
respectively depositing metal layers in the source region and the drain region and annealing to form the source electrode and the drain electrode;
depositing a passivation layer material on the surface of the p-GaN layer to form the third passivation layer.
Optionally, before forming the source electrode, the drain electrode and the third passivation layer, the method further includes:
forming an isolation layer; the isolation layer is formed in the channel layer, the barrier layer, and the p-GaN layer; and the isolation layer is formed at one end of the source region and the drain region far away from the gate region.
Optionally, forming a source metal interconnection layer, a drain metal interconnection layer and a gate metal interconnection layer; the source metal pad, the drain metal pad and the gate metal pad specifically include:
forming a second passivation layer; the second passivation layer is formed on the top ends of the first passivation layer and the gate metal layer;
etching the first passivation layer and the second passivation layer on the top ends of the source electrode and the drain electrode; forming corresponding source interconnection holes and drain interconnection holes; etching the second passivation layer at the top end of the grid to form a grid interconnection hole;
filling metal layers in the source electrode interconnection hole, the drain electrode interconnection hole and the grid electrode interconnection hole to form a corresponding source electrode metal interconnection layer, a corresponding drain electrode metal interconnection layer and a corresponding grid electrode metal interconnection layer; and
and respectively depositing metal layers at the top ends of the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer to form a corresponding source metal pad, a corresponding drain metal pad and a corresponding gate metal pad.
According to a third aspect of the present invention, there is provided a method of manufacturing an electronic device, comprising: the invention relates to a method for manufacturing an enhancement mode gallium nitride transistor according to the second aspect.
According to a fourth aspect of the invention, there is provided an electronic device comprising an enhancement mode gallium nitride transistor according to any one of the first aspects of the invention.
The invention provides an enhancement mode gallium nitride transistor, the structure of which comprises: the device comprises a substrate, and a nucleation layer, a buffer layer, a channel layer and a barrier layer which are formed on the substrate along the direction far away from the substrate; forming a first p-GaN layer in the gate region of the barrier layer, wherein the first p-GaN layer is passivated by acceptor impurity Mg ions to form a neutral compound; forming a second p-GaN layer in the non-grid region; the first p-GaN layer and the gate metal layer deposited at the top end of the first p-GaN layer form a gate; a source electrode and a drain electrode of the device are formed on the source region and the drain region of the second p-GaN layer; a neutral compound is formed due to the fact that acceptor impurities Mg ions in the first p-GaN layer are passivated; therefore, the concentration of holes in the first p-GaN layer is reduced, and finally the grid is not conducted when the grid voltage is zero; the functional requirements of the enhanced gallium nitride transistor are met, and etching damage of the first p-GaN layer is avoided. And the first p-GaN layer in the gate region becomes a high-resistance p-GaN layer due to the great reduction of the hole concentration, which helps to reduce the gate leakage current. Therefore, the technical scheme provided by the invention solves the problem of how to avoid the etching damage of the first p-GaN layer, and improves the performance of the device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for fabricating an enhancement mode gan transistor according to an embodiment of the invention;
FIG. 2 is a first schematic diagram illustrating a device structure according to an embodiment of the present invention at a different processing stage of a method for fabricating an enhanced GaN transistor;
FIG. 3 is a second schematic diagram illustrating a device structure according to a second embodiment of the present invention at a different stage of fabrication of a method for fabricating an enhancement mode GaN transistor;
fig. 4 is a schematic diagram of a third device structure at a different processing stage according to a method for fabricating an enhancement mode gan transistor according to an embodiment of the invention;
description of the reference numerals:
101-a substrate;
102-a nucleation layer;
103-a buffer layer;
104-a channel layer;
105-a barrier layer;
106-a second p-GaN layer;
107-an isolation layer;
108-source;
109-drain electrode
110-a first passivation layer;
111-a first p-GaN layer;
112-a gate metal layer;
113-source metal interconnect;
114-gate metal interconnect layer;
115-drain metal interconnect layer;
116-a second passivation layer;
117-source metal pad;
118-a gate metal pad;
119-drain metal pad;
120-third passivation layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Gallium nitride high electron mobility transistors (AlGaN/GaN HEMTs) have a broad prospect in the high frequency and high power fields due to their superior device performance. With the continuous maturation of the technology, a part of the market is occupied in consumer electronics and radio frequency communication applications. Furthermore, such lateral devices also have the feasibility of high-density monolithic integration. The drive, protection and control functions can be integrated with the power switch, and the performance can be further improved due to the avoidance of parasitic inductance.
Unlike silicon-based chips that are implemented using complementary logic circuits comprising n-channel field effect transistors (NMOS) and p-channel field effect transistors (PMOS), current implementations of gallium nitride power devices and peripheral circuits are based on n-channels. In GaN monolithic integrated circuits, a direct-coupled field effect logic (DCFL) scheme is typically employed, consisting of an enhancement n-channel transistor and a depletion n-channel transistor. The pull-up circuit is composed of a depletion mode device with a short-circuited grid source, and therefore the depletion mode device is always in a conducting state. When the pull-down circuit is turned on, a large amount of static power is consumed. Therefore, power consumption is a major drawback of such DCFL circuits. The complementary logic circuit does not have this problem. To form a GaN-based complementary logic circuit with an n-channel GaN transistor requires a high performance enhancement mode p-channel GaN transistor with a certain current density and good on-off ratio. In conventional studies, p-channel gallium nitride transistors have been constructed by filling a quantum well with a high-density two-dimensional hole gas (2 DHG) mainly by utilizing the strong polarization characteristics of nitrides, so as to improve hole mobility and carrier density. However, such a customized epitaxial structure generally has a parasitic n-channel that cannot be depleted, or does not have an n-channel, and thus cannot meet the requirements of a GaN complementary logic circuit, i.e., n and p channels exist simultaneously and do not interfere with each other.
The current commercial p-GaN/AlGaN/GaN epitaxial wafer can just meet the requirement, and p-GaN/AlGaN and AlGaN/GaN heterojunction interfaces can be used as a p channel and an n channel. The presence of p-GaN depletes electrons in the AlGaN barrier layer so that the p-channel is also not disturbed by the n-channel. And etching the p-GaN at the position of the gate region, and only keeping the extremely thin thickness (< 10 nm) in the gate region, so that the holes in the p-GaN channel layer under zero gate voltage can be depleted, and the normally-closed p-channel device is realized. However, etching p-GaN will undoubtedly damage the crystal lattice and the hole mobility in the p-channel will also be reduced. And the etched interface also forms a high-density trap state due to factors such as etching byproduct accumulation, nitrogen vacancy and the like, thereby seriously influencing the performance of the device.
In view of the above, through repeated experiments, the inventors of the present application found that by passivating Mg ions, which are used as a doped shallow acceptor impurity, above a p-GaN channel layer in a gate region, the concentration of holes in the channel is greatly reduced, and an effect of being unable to conduct at zero gate voltage can be achieved, thereby satisfying the requirements for the functions of an enhancement-mode GaN transistor. Therefore, the invention provides a new technical scheme and a new technological process for realizing the p-channel enhanced gallium nitride transistor by etching-free p-GaN.
Therefore, according to the technical scheme provided by the invention, the grid electrode is formed in a mode of passivating acceptor impurity Mg ions in the p-GaN layer, so that the requirements on the functions of the enhanced gallium nitride transistor can be met, and the etching damage of the p-GaN can be avoided. The etching of p-GaN is avoided, the problems are solved, and the performance of the device is improved.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 1-4, according to an embodiment of the present invention, an enhancement mode gan transistor is provided, including:
a substrate 101, and a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, and a p-GaN layer formed on the substrate 101 in a direction away from the substrate 101; wherein the p-GaN layer comprises a first p-GaN layer 111 and a second p-GaN layer 106; the first p-GaN layer 111 is formed in the gate region; the second p-GaN layer 106 is formed in a non-gate region; in one embodiment, the material of the nucleation layer 102 is AlN, the material of the channel layer 104 is GaN, and the material of the barrier layer 105 is AlGaN; of course, the foregoing structural layers may be made of other materials, and the present invention is not limited thereto, and the material implementation form of any corresponding structural layer is within the protection scope of the present invention;
a source electrode 108, a drain electrode 109 and a gate electrode, wherein the source electrode 108, the gate electrode and the drain electrode 109 are respectively formed on the source region, the gate region and the drain region on the p-GaN layer; the gate comprises the first p-GaN layer 111 and a gate metal layer 112 formed at the top end of the first p-GaN layer 111; the source 108 comprises a first metal layer and a second metal layer; the first metal layer covers the second metal layer, the first metal layer is made of Au, and the second metal layer is made of Ni; the drain electrode 109 comprises a third metal layer and a fourth metal layer; the third metal layer covers the fourth metal layer, the third metal layer is made of Au, and the fourth metal layer is made of Ni; of course, the foregoing structural layers may be made of other materials, and the present invention is not limited thereto, and the material implementation form of any corresponding structural layer is within the protection scope of the present invention;
the gate metal layer 112 includes a fifth metal layer and a sixth metal layer; the fifth metal layer covers the sixth metal layer, the fifth metal layer is made of Au, and the sixth metal layer is made of Ni; the structural layer may be made of other materials, and the invention is not limited thereto, and any implementation form of the materials of the structural layer is within the scope of the invention; wherein, in one embodiment, the thickness of the gate metal layer 112 is 40 or 60nm; the invention is not limited to the above, and any thickness realization form of the corresponding structural layer is within the protection scope of the invention; and
the passivation layer is made of SiN; the structural layer may be made of other materials, and the invention is not limited thereto, and any implementation form of the materials of the structural layer is within the scope of the invention; in one embodiment, the passivation layers include a first passivation layer 110 and a second passivation layer 116; the first passivation layer 110 is formed on the second p-GaN layer 106; the second passivation layer 116 is formed on the first passivation layer 110 and the gate metal layer 112.
Wherein the first p-GaN layer 111 includes a neutral complex formed by passivation of acceptor impurity Mg ions; so that the gate is not conductive at zero gate voltage, and the device structure of the enhancement mode gan transistor is shown in fig. 4.
Wherein the non-gate region refers to: regions other than the gate region on the barrier layer 105;
in the enhanced gallium nitride transistor provided by the invention, a p-GaN layer is formed on a barrier layer 105, a first p-GaN layer 111 forming the p-GaN layer is formed in a grid region, and a second p-GaN layer 106 forming the p-GaN layer is formed in a non-grid region; the first p-GaN layer 111 and the gate metal layer 112 deposited on the top end thereof form a gate electrode; meanwhile, a source electrode 108 and a drain electrode 109 are formed on the source region and the drain region on the p-GaN layer; wherein, the concentration of holes in the first p-GaN layer 111 is reduced because of the formation of neutral compounds due to the passivation of acceptor impurity Mg ions in the first p-GaN layer 111, and finally the gate is not conducted at zero gate voltage. And the first p-GaN layer 111 of the gate region becomes a high-resistance p-GaN layer due to a great decrease in hole concentration, which contributes to a reduction in gate leakage current.
Therefore, according to the technical scheme provided by the invention, the first p-GaN layer 111 formed after the passivation of the acceptor impurity Mg ions is used as the structure for forming the grid, and the finally formed grid is not conducted at zero grid voltage due to the structure; the requirements on the functions of the device are met, and compared with the prior art, the problem of how to avoid etching damage of the first p-GaN layer 111 is solved, and the performance of the device is improved.
In one embodiment, the enhancement-mode gan transistor further comprises:
a source metal interconnect 113, a drain metal interconnect 115, and a gate metal interconnect 114; the source metal interconnection layer 113, the drain metal interconnection layer 115 and the gate metal interconnection layer 114 are respectively formed on the top ends of the source electrode 108, the drain electrode 109 and the gate electrode;
source metal pad 117, drain metal pad 119, and gate metal pad 118; the source metal pad 117, the drain metal pad 119, and the gate metal pad 118 are formed on top of the source metal interconnection layer 113, the drain metal interconnection layer 115, and the gate metal interconnection layer 114, respectively.
Secondly, according to an embodiment of the present invention, a method for manufacturing an enhancement mode gan transistor is further provided, a flow chart of the method for manufacturing the enhancement mode gan transistor is shown in fig. 1, and the method includes:
s11: providing a substrate 101;
s12: sequentially forming a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, and a p-GaN layer on the substrate 101 in a direction away from the substrate 101;
s13: forming a source electrode 108, a drain electrode 109, and a third passivation layer 120; the source electrode 108, the drain electrode 109 and the third passivation layer 120 are formed on the p-GaN layer, and the third passivation layer 120 covers the source electrode 108 and the drain electrode 109, and the device after the source electrode 108, the drain electrode 109 and the third passivation layer 120 are formed is shown in fig. 2;
in one embodiment, the step S13 of forming the source electrode 108, the drain electrode 109 and the third passivation layer 120 specifically includes: s131 to S132:
s131: depositing metal layers on the source region and the drain region respectively and annealing to form the source electrode 108 and the drain electrode 109; in one embodiment, in the process of annealing the metal layer of the source region or the drain region, the adopted gas is oxygen, the temperature is 500 ℃, and the time is 5min;
s132: depositing a passivation layer material on the surface of the p-GaN layer to form the third passivation layer 120.
In one embodiment, the material of the third passivation layer 120 is deposited by: PECVD (Plasma Enhanced Chemical Vapor Deposition-Plasma Enhanced Chemical Vapor Deposition)
In one embodiment, when the enhancement mode gallium nitride transistor device comprises a plurality of enhancement mode gallium nitride transistors, a plurality of enhancement mode gallium nitride transistors are isolated; step S13, before forming the source electrode 108, the drain electrode 109, and the third passivation layer 120, further includes:
forming an isolation layer 107; the isolation layer 107 is formed in the channel layer 104, the barrier layer 105, and the p-GaN layer; and the isolation layer 107 is formed at one end of the source region and the drain region far from the gate region.
In one embodiment, the isolation layer 107 is formed by ion implantation.
In another embodiment, the isolation layer 107 may be formed by mesa etching;
s14: etching the third passivation layer 120 of the gate region to form a gate opening and the first passivation layer 110;
the gas used for etching the third passivation layer 120 is SF 6 The device after step S14 is as shown in fig. 3;
s15: performing first treatment on the p-GaN layer of the gate region to form a first p-GaN layer 111;
s16: depositing a gate metal layer 112 on the top of the first p-GaN layer 111 to form a gate; the gate comprises the first p-GaN layer 111 and the gate metal layer 112 on top thereof; and
s17: forming a source metal inter-layer 113, a drain metal inter-layer 115 and a gate metal inter-layer 114; source metal pad 117, drain metal pad 119, and gate metal pad 118;
in one embodiment, step S17 is to form a source metal interconnection layer 113, a drain metal interconnection layer 115 and a gate metal interconnection layer 114; the source metal pad 117, the drain metal pad 119, and the gate metal pad 118 specifically include: S171-S174:
s171: forming a second passivation layer 116; the second passivation layer 116 is formed on top of the first passivation layer 110 and the gate metal layer 112;
s172: etching the first passivation layer 110 and the second passivation layer 116 on top of the source electrode 108 and the drain electrode 109; forming corresponding source interconnection holes and drain interconnection holes; etching the second passivation layer 116 on the top of the gate to form a gate interconnection hole;
s173: filling metal layers in the source interconnection hole, the drain interconnection hole and the gate interconnection hole to form a corresponding source metal interconnection layer 113, a corresponding drain metal interconnection layer 115 and a corresponding gate metal interconnection layer 114; and
s174: depositing metal layers on top of the source metal interconnection layer 113, the drain metal interconnection layer 115 and the gate metal interconnection layer 114 to form a source metal pad 117, a drain metal pad 119 and a gate metal pad 118;
wherein the first processing includes: and passivating the acceptor impurity Mg ions in the p-GaN layer to make the grid not be conducted at zero grid voltage, and finally forming a device as shown in FIG. 4.
The first p-GaN layer 111 is formed by passivating Mg ions in the p-GaN layer of the gate region, and since acceptor impurity Mg ions in the p-GaN layer of the gate region are passivated, the hole concentration of the gate region is reduced, so that the gate is not turned on at zero gate voltage.
The invention provides an enhanced gallium nitride transistor, which is characterized in that on the basis of a p-GaN layer formed on a barrier layer 105, a first p-GaN layer 111 is formed in a grid region in a mode of passivating acceptor impurity Mg ions in the p-GaN layer, and a second p-GaN layer 106 is formed on the p-GaN layer of Mg ions in a non-grid region, wherein the Mg ions are not passivated; depositing a gate metal layer 112 on top of the first p-GaN layer 111 to form a gate; a source electrode 108 and a drain electrode 109 are formed on the p-GaN layer at the same time; because acceptor impurity Mg ions in the first p-GaN layer 111 forming the grid electrode are passivated, the concentration of holes in the first p-GaN layer 111 is reduced, and finally the grid electrode is not conducted at zero grid voltage; to meet the functional requirements of enhancement mode gallium nitride transistors; and the first p-GaN layer 111 of the gate region becomes a high resistance p-GaN layer due to a large decrease in hole concentration, which contributes to a reduction in gate leakage current.
Therefore, according to the technical scheme provided by the invention, the first p-GaN layer 111 is formed in a mode of passivating acceptor impurity Mg ions in the p-GaN layer, so that a finally formed grid is not conducted when the grid voltage is zero, and the requirement on the function of the enhanced gallium nitride transistor is met; compared with the prior art that the first p-GaN layer 111 is formed by etching the p-GaN layer in the non-grid region, the method solves the problem of how to avoid etching damage of the first p-GaN layer 111 in the process of forming the first p-GaN layer 111, and improves the performance of the device.
In one embodiment, the method for passivating acceptor impurity Mg ions in the p-GaN layer comprises: thermal oxidation, oxygen plasma, and hydrogen plasma. The basic principle is as follows:
the method for passivating the acceptor impurity Mg ions in the p-GaN layer is as follows: thermal oxidation method, oxygen plasma method: the O element in the p-GaN layer is more prone to become a shallow level donor type impurity, and can be ionized to compensate for holes, or form a Mg-O neutral complex with Mg ions, thereby rendering the Mg ions ineffective.
The method for passivating Mg ions in the p-GaN layer is as follows: the hydrogen plasma method can passivate Mg ions in the p-GaN layer into Mg-H neutral compounds, thereby converting the p-GaN layer into high resistance.
In one embodiment, the thickness of the first p-GaN layer 111 is controllable.
In one embodiment, the thickness of the first p-GaN layer 111 is controlled to a first thickness; the first thickness characterizes the thickness of the barrier layer 105 and the p-GaN layer in the stacking direction.
In one embodiment, the first thickness is adjusted such that the distance between the first p-GaN layer 111 and the barrier layer 105 is controlled to be 5-10 nm.
In one embodiment, when the thermal oxidation method is used, the first thickness is achieved by adjusting a temperature, an oxygen flow rate, a pressure, or a time during the oxidation process; preferably, the first thickness meets the requirements of the enhanced gallium nitride transistor provided by the patent by comprehensively regulating and controlling the parameters;
when the oxygen plasma method or the hydrogen plasma method is adopted, the first thickness is realized by adjusting power, pressure intensity, gas flow or time; preferably, the first thickness meets the requirements of the enhancement mode gallium nitride transistor provided by the patent through comprehensively regulating and controlling the parameters.
Still further, according to another embodiment of the present invention, there is provided a method of manufacturing an electronic device, including: the method of fabricating an enhancement mode gan transistor according to any of the above embodiments of the present invention.
According to other embodiments of the present invention, there is also provided an electronic device including the enhancement mode gallium nitride transistor according to any one of the preceding embodiments of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (15)

1. An enhancement-mode gallium nitride transistor, comprising:
a substrate, and a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer formed on the substrate in a direction away from the substrate; wherein the p-GaN layer comprises a first p-GaN layer and a second p-GaN layer; the first p-GaN layer is formed on the grid region; the second p-GaN layer is formed on the non-grid region;
the source electrode, the grid electrode and the drain electrode are respectively formed on a source region, a grid electrode region and a drain region on the p-GaN layer; the grid electrode comprises the first p-GaN layer and a grid metal layer formed at the top end of the first p-GaN layer; and
a passivation layer for protecting the substrate from light,
wherein the first p-GaN layer comprises a neutral complex formed by passivation of acceptor impurity Mg ions; so that the gate is non-conductive at zero gate voltage.
2. The enhancement mode gallium nitride transistor according to claim 1, wherein said passivation layer comprises a first passivation layer and a second passivation layer; the first passivation layer is formed on the second p-GaN layer; the second passivation layer is formed on the first passivation layer and the gate metal layer.
3. The enhancement mode gallium nitride transistor according to claim 2, further comprising:
the source electrode metal interconnection layer, the drain electrode metal interconnection layer and the grid electrode metal interconnection layer; the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer are respectively formed at the top ends of the source, the drain and the gate;
a source metal pad, a drain metal pad and a gate metal pad; the source metal pad, the drain metal pad and the gate metal pad are formed at the top ends of the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer, respectively.
4. The enhancement mode GaN transistor according to claim 3,
the material of the nucleation layer is AlN, the material of the channel layer is GaN, and the material of the barrier layer is AlGaN.
5. A method for fabricating an enhancement mode GaN transistor, the method comprising:
providing a substrate;
sequentially forming a nucleating layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate along the direction far away from the substrate;
forming a source electrode, a drain electrode and a third passivation layer; the source electrode, the drain electrode and the third passivation layer are formed on the p-GaN layer, and the third passivation layer covers the source electrode and the drain electrode;
etching the third passivation layer in the gate region to form a gate opening and a first passivation layer;
performing first treatment on the p-GaN layer of the grid region to form a first p-GaN layer;
depositing a gate metal layer at the top end of the first p-GaN layer to form a gate; the gate comprises the first p-GaN layer and the gate metal layer on the top end of the first p-GaN layer; and
forming a source metal interconnection layer, a drain metal interconnection layer and a grid metal interconnection layer; a source metal pad, a drain metal pad and a gate metal pad;
wherein the first processing includes: and passivating the acceptor impurity Mg ions in the p-GaN layer so that the grid is not conducted at zero grid voltage.
6. The method of claim 5, wherein the first p-GaN layer has a controllable thickness.
7. The method according to claim 5, wherein the thickness of the first p-GaN layer is controlled to be a first thickness; the first thickness characterizes a thickness in a stacking direction of the barrier layer and the p-GaN layer.
8. The method according to claim 7, wherein the first thickness is adjusted so that the distance between the first p-GaN layer and the barrier layer is controlled to be 5-10 nm.
9. The method of claim 8, wherein the step of forming an enhancement mode GaN transistor,
the method for passivating Mg ions in the first p-GaN layer comprises the following steps: thermal oxidation, oxygen plasma, and hydrogen plasma.
10. The method of claim 9, wherein the first and second electrodes are formed on a substrate,
when the thermal oxidation method is adopted, the first thickness is realized by adjusting the temperature, the oxygen flow, the pressure or the time in the oxidation process;
when the oxygen plasma method or the hydrogen plasma method is employed, the first thickness is achieved by adjusting power, pressure, gas flow rate, or time.
11. The method of claim 10, wherein forming the source, the drain, and the third passivation layer comprises:
respectively depositing metal layers in the source region and the drain region and annealing to form the source electrode and the drain electrode;
depositing a passivation layer material on the surface of the p-GaN layer to form the third passivation layer.
12. The method of claim 11, further comprising, prior to forming the source, drain and third passivation layer:
forming an isolation layer; the isolation layer is formed in the channel layer, the barrier layer, and the p-GaN layer; and the isolation layer is formed at one end of the source region and the drain region far away from the gate region.
13. The method of claim 12, wherein a source metal interconnect layer, a drain metal interconnect layer and a gate metal interconnect layer are formed; the source metal pad, the drain metal pad and the gate metal pad specifically include:
forming a second passivation layer; the second passivation layer is formed on the top ends of the first passivation layer and the gate metal layer;
etching the first passivation layer and the second passivation layer on the top ends of the source electrode and the drain electrode; forming corresponding source electrode interconnection holes and drain electrode interconnection holes; etching the second passivation layer at the top end of the grid to form a grid interconnection hole;
filling metal layers in the source electrode interconnection hole, the drain electrode interconnection hole and the grid electrode interconnection hole to form a corresponding source electrode metal interconnection layer, a corresponding drain electrode metal interconnection layer and a corresponding grid electrode metal interconnection layer; and
and respectively depositing metal layers at the top ends of the source metal interconnection layer, the drain metal interconnection layer and the grid metal interconnection layer to form a source metal bonding pad, a drain metal bonding pad and a grid metal bonding pad which correspond to each other.
14. A method of making an electronic device, comprising: a method of fabricating an enhancement mode gallium nitride transistor according to any one of claims 5 to 13.
15. An electronic device comprising the enhancement mode gallium nitride transistor according to any one of claims 1 to 4.
CN202211255239.4A 2022-10-13 2022-10-13 Enhanced gallium nitride transistor, manufacturing method of device and device Pending CN115548094A (en)

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